Prosecution Insights
Last updated: August 17, 2026
Application No. 18/769,527

LIGHT EMITTING DEVICE

Non-Final OA §103
Filed
Jul 11, 2024
Priority
Sep 14, 2020 — JP 2020-153600 +2 more
Examiner
YECHURI, SITARAMARAO S
Art Unit
Tech Center
Assignee
NICHIA Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
77%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
766 granted / 894 resolved
+25.7% vs TC avg
Minimal -9% lift
Without
With
+-8.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
40 currently pending
Career history
921
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
61.8%
+21.8% vs TC avg
§102
18.7%
-21.3% vs TC avg
§112
15.3%
-24.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 894 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Allowable Subject Matter Claim 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 20120267671 A1) hereafter referred to as Jung in view of Kurimoto et al. (JP 2007300021 A) hereafter referred to as Kurimoto In regard to claim 1 Jung teaches a [“FIG. 11 is a perspective view illustrating a light emitting device package according to a seventh embodiment”] package comprising: a bottom portion [see Fig. 11 “The cavity 15 may be defined by the insulating layers 10a, 10b, 10c, and 10d. As illustrated in FIGS. 2 and 4, the first insulating layer 10a is a base insulating layer having no pattern, and the second and third insulating layers 10b and 10c have a central opening in which the light emitting diode 20 is mounted. The fourth insulating layer 10d disposed on the third insulating layer 10c has an opening greater than that of the third insulating layer 10c, so as to form the cavity 15” “the shape of the cavity 15 for mounting the light emitting diode 20 is not limited thereto, and thus, may be varied according to a design of the insulating layers 10a, 10b, 10c, and 10d”] having a mounting surface on which a light emitting element is arranged; and a lateral wall portion [see Fig. 11 “The cavity 15 may be defined by the insulating layers 10a, 10b, 10c, and 10d”] having a top surface and comprising: a lateral wall [see Fig. 11 “The body 10 is formed by stacking insulating layers 10a, 10b, 10c, and 10d” see rectangular shape] having a rectangular outer shape in a top view and surrounding [see Fig. 11] the mounting surface, and PNG media_image1.png 612 774 media_image1.png Greyscale a stepped portion [see stepped as shown in Fig. 11 reproduced above “The fourth insulating layer 10d disposed on the third insulating layer 10c has an opening greater than that of the third insulating layer 10c, so as to form the cavity 15”] formed along the lateral wall below the top surface, wherein: in the top view, the stepped portion includes a region [see Fig. 11 bottom right side, see the Zener diode on the stepped portion “Reverse current may be guided to the Zener diode 35 disposed within the cavity 15 to protect the light emitting diode 20. The Zener diode 35 is disposed on a dummy electrode 33”] on which a protecting element to protect the light emitting element is arranged and see in Fig. 11, see the three sides of the stepped portion which “does not have the region on which the protecting element is arranged”, but does not state: a wide portion and a narrow portion that are two regions having different widths, and the wide portion has a region on which a protecting element to protect the light emitting element is arranged and the narrow portion does not have the region on which the protecting element is arranged. See in Jung Fig. 11 see that on two of the stepped portions are the electrodes 31 and 33 however the other two stepped portions do not have anything on them, see paragraph 0006 “when a package size of UV LEDs is increased to improve heat dissipation efficiency, integration efficiency and economic efficiency are jeopardized”. See Kurimoto “In the LED device shown in FIGS. 1 to 6, the package 10 has a recess 10a for accommodating an element on the top surface of an insulating material, and a step portion 11 exists in the peripheral portion of the bottom surface 10b inside the recess” “On the bottom surface 10b, a light emitting element 16 that is a gallium nitride-based compound semiconductor and a protective element 17 having an appropriate Zener voltage for protecting the light emitting element 16 are mounted”, see in Fig. 1 that the width of the step portion 11 is different on each side. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Jung to include a wide portion and a narrow portion that are two regions having different widths, and the wide portion has a region on which a protecting element to protect the light emitting element is arranged and the narrow portion does not have the region on which the protecting element is arranged. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is that there is really no reason not to reduce the width of the stepped portion on the sides where there is nothing on the stepped portion, and the reduction need not be uniform on all sides and that reducing the width of the stepped portion on one or more sides helps reduce the size of the device and avoid wasted area inside the device and/or in any location that the device is placed. In regard to claim 2 Jung and Kurimoto as combined teaches wherein the stepped portion is formed along [see Jung Fig. 11] the entire circumference of the lateral wall. In regard to claim 3 Jung and Kurimoto as combined teaches wherein the narrow portion is formed on a portion [see combination the width of the stepped portion with nothing on them, on one or more sides can be reduced to save space ] along a one side of the entire circumference of the lateral wall. In regard to claim 4 Jung and Kurimoto as combined teaches wherein the wide portion is formed on a portion along three sides [see combination the width of the stepped portion with nothing on them, on one or more sides can be reduced to save space ] of the entire circumference of the lateral wall. In regard to claim 5 Jung and Kurimoto as combined teaches further comprising one or more wiring regions [see in Jung Fig. 11 see that on two of the stepped portions are the electrodes 31 and 33 however the other two stepped portions do not have anything on them] provided on a top surface of the stepped portion, wherein no wiring regions are provided on a top surface of the narrow [see combination the width of the stepped portion with nothing on them, on one or more sides can be reduced to save space ] portion of the top surface of the stepped portion. In regard to claim 6 Jung and Kurimoto as combined teaches further comprising a wiring region [see in Jung Fig. 11 see that on two of the stepped portions are the electrodes 31 and 33 however the other two stepped portions do not have anything on them] provided on a top surface of the wide portion, wherein a width of the wiring region in a same direction as the width of the wide portion is greater [see combination the width of the stepped portion with nothing on them, on one or more sides can be reduced to save space ] than the width of the narrow portion. Claim(s) 7-13, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 20120267671 A1) hereafter referred to as Jung in view of Kurimoto et al. (JP 2007300021 A) hereafter referred to as Kurimoto In regard to claim 7 Jung teaches a [“FIG. 11 is a perspective view illustrating a light emitting device package according to a seventh embodiment”] light emitting device comprising: a package [see Fig. 11] comprising: a bottom portion [see Fig. 11 “The cavity 15 may be defined by the insulating layers 10a, 10b, 10c, and 10d. As illustrated in FIGS. 2 and 4, the first insulating layer 10a is a base insulating layer having no pattern, and the second and third insulating layers 10b and 10c have a central opening in which the light emitting diode 20 is mounted. The fourth insulating layer 10d disposed on the third insulating layer 10c has an opening greater than that of the third insulating layer 10c, so as to form the cavity 15” “the shape of the cavity 15 for mounting the light emitting diode 20 is not limited thereto, and thus, may be varied according to a design of the insulating layers 10a, 10b, 10c, and 10d”] having a mounting surface; and a lateral wall portion [see Fig. 11 “The cavity 15 may be defined by the insulating layers 10a, 10b, 10c, and 10d”] having a top surface and comprising: a lateral wall [see Fig. 11 “The body 10 is formed by stacking insulating layers 10a, 10b, 10c, and 10d” see rectangular shape] having a rectangular outer shape in a top view and surrounding [see Fig. 11] the mounting surface, and PNG media_image1.png 612 774 media_image1.png Greyscale a stepped portion [see stepped as shown in Fig. 11 reproduced above “The fourth insulating layer 10d disposed on the third insulating layer 10c has an opening greater than that of the third insulating layer 10c, so as to form the cavity 15”] formed along the lateral wall below the top surface; a light emitting element [“the shape of the cavity 15 for mounting the light emitting diode 20 is not limited thereto, and thus, may be varied according to a design of the insulating layers 10a, 10b, 10c, and 10d”] arranged on the mounting surface; and a protecting element arranged [see Fig. 11 bottom right side, see the Zener diode on the stepped portion “Reverse current may be guided to the Zener diode 35 disposed within the cavity 15 to protect the light emitting diode 20. The Zener diode 35 is disposed on a dummy electrode 33”] on the stepped portion, the protecting element protecting the light emitting element, and see in Fig. 11, see the three sides of the stepped portion which “does not have the region on which the protecting element is arranged”, but does not state: wherein: in the top view, the stepped portion includes a wide portion and a narrow portion that are two regions having different widths, and the protecting element is arranged on the wide portion and no protecting elements are arranged on the narrow portion. See in Jung Fig. 11 see that on two of the stepped portions are the electrodes 31 and 33 however the other two stepped portions do not have anything on them, see paragraph 0006 “when a package size of UV LEDs is increased to improve heat dissipation efficiency, integration efficiency and economic efficiency are jeopardized”. See Kurimoto “In the LED device shown in FIGS. 1 to 6, the package 10 has a recess 10a for accommodating an element on the top surface of an insulating material, and a step portion 11 exists in the peripheral portion of the bottom surface 10b inside the recess” “On the bottom surface 10b, a light emitting element 16 that is a gallium nitride-based compound semiconductor and a protective element 17 having an appropriate Zener voltage for protecting the light emitting element 16 are mounted”, see in Fig. 1 that the width of the step portion 11 is different on each side. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Jung to include wherein: in the top view, the stepped portion includes a wide portion and a narrow portion that are two regions having different widths, and the protecting element is arranged on the wide portion and no protecting elements are arranged on the narrow portion. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is that there is really no reason not to reduce the width of the stepped portion on the sides where there is nothing on the stepped portion, and the reduction need not be uniform on all sides and that reducing the width of the stepped portion on one or more sides helps reduce the size of the device and avoid wasted area inside the device and/or in any location that the device is placed. In regard to claim 8 Jung and Kurimoto as combined teaches wherein the stepped portion is formed along [see Jung Fig. 11] the entire circumference of the lateral wall. In regard to claim 9 Jung and Kurimoto as combined teaches wherein the narrow portion is formed on a portion [see combination the width of the stepped portion with nothing on them, on one or more sides can be reduced to save space ] along a one side of the entire circumference of the lateral wall. In regard to claim 10 Jung and Kurimoto as combined teaches wherein the wide portion is formed on a portion along three sides [see combination the width of the stepped portion with nothing on them, on one or more sides can be reduced to save space ] of the entire circumference of the lateral wall. In regard to claim 11 Jung and Kurimoto as combined teaches further comprising a wiring region [see in Jung Fig. 11 see that on two of the stepped portions are the electrodes 31 and 33 however the other two stepped portions do not have anything on them] provided on a top surface of the stepped portion, wherein the wiring region is not provided on a top surface of the narrow [see combination the width of the stepped portion with nothing on them, on one or more sides can be reduced to save space ] portion of the top surface of the stepped portion. In regard to claim 12 Jung and Kurimoto as combined teaches further comprising a wiring region [see in Jung Fig. 11 see that on two of the stepped portions are the electrodes 31 and 33 however the other two stepped portions do not have anything on them] provided on a top surface of the wide portion, wherein a width of the wiring region in a same direction as the width of the wide portion is greater [see combination the width of the stepped portion with nothing on them, on one or more sides can be reduced to save space ] than the width of the narrow portion. In regard to claim 13 Jung and Kurimoto as combined teaches wherein the protecting element is arranged on [see Fig. 11 bottom right side, see the Zener diode on the electrode, “Reverse current may be guided to the Zener diode 35 disposed within the cavity 15 to protect the light emitting diode 20. The Zener diode 35 is disposed on a dummy electrode 33”] the wiring region. In regard to claim 16 Jung and Kurimoto as combined teaches further comprising: a wiring region [see in Jung Fig. 11 see that on two of the stepped portions are the electrodes 31 and 33 however the other two stepped portions do not have anything on them] provided on a top surface of the wide portion, and a first wire [“light emitting diode 20 may be adhered to the second electrode 32 through a conductive adhesive, and be electrically connected to the first electrode 31 through the wire 22”] electrically connecting the light emitting element to the wiring region, wherein, in the top view, the first wire is joined to the wiring region provided on a top surface of the wide portion formed along a side in contact with [see Fig. 11 see combination the width of the stepped portion with nothing on them, on one or more sides can be reduced to save space] a side along which the narrow portion is formed. Claim(s) 14, 17, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung and Kurimoto as combined and further in view of Kiyota et al. (US 20170122505 A1) hereafter referred to as Kiyota In regard to claim 14 Jung and Kurimoto as combined does not specifically teach wherein the narrow portion is formed at a position at which the narrow portion faces a light emitting surface of the light emitting element. See Jung Abstract “Provided is a light emitting device package, which includes a ceramic body, an ultraviolet light emitting diode, a support member, and a glass film”. See Kiyota Fig. 1C “the light emitting device 1 includes a base 10 defining a recess 10a that opens upward, a semiconductor laser element 20 arranged on a bottom surface 11 of the recess 10a, a light reflecting member 30 arranged on the bottom surface 11 and configured to reflect light from the semiconductor laser element 20” “The light emitting device 1 is, for example, an SMD type LD package. In the present specification, the “SMD type” refers to a surface-mounted device type, and the “LD” refers to a laser diode. SMD type LD packages can be used for automobile headlights, projectors, or the like” “The semiconductor laser element 20 is arranged on the bottom surface 11 of the recess 10a. Light emitted from the semiconductor laser element 20 advances in a direction substantially parallel to the bottom surface 11 of the recess 10a, and is reflected in a direction substantially perpendicular to the bottom surface 11 of the recess 10a by the light reflecting member 30”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Jung to include wherein the narrow portion is formed at a position at which the narrow portion faces a light emitting surface of the light emitting element. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is that laser diodes are known to a person of ordinary skill in the art to give excellent results to emit light efficiently and powerfully and that in Jung Fig. 11 the sides having stepped portions with nothing on them have space to place the light reflecting member of Kiyota. In regard to claim 17 Jung Kurimoto and Kiyota as combined teaches further comprising an optical member [see combination, see the light reflecting member of Kiyota] disposed between the light emitting element and the narrow portion in the top view. In regard to claim 18 Jung Kurimoto and Kiyota as combined teaches wherein the light emitting element is [see combination, see the laser diode of Kiyota] a semiconductor laser element. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt D Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jul 11, 2024
Application Filed
Jul 22, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
77%
With Interview (-8.7%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 894 resolved cases by this examiner. Grant probability derived from career allowance rate.

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