Prosecution Insights
Last updated: April 19, 2026
Application No. 18/769,753

METHOD FOR MANUFACTURING ACOUSTIC WAVE ELEMENT AND ACOUSTIC WAVE ELEMENT

Non-Final OA §103
Filed
Jul 11, 2024
Examiner
GLENN, KIMBERLY E
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co. Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
96%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
949 granted / 1057 resolved
+21.8% vs TC avg
Moderate +6% lift
Without
With
+6.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
38 currently pending
Career history
1095
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
24.6%
-15.4% vs TC avg
§102
38.0%
-2.0% vs TC avg
§112
30.9%
-9.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1057 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 7/11/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 and 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hori JP 2015-119219A in view of Yamamoto et al JP 201819286a ( both of record). Hori discloses example 1 :A Si substrate having a thickness of 500 μm was prepared as a first support substrate, and a LiNbO 3 substrate (per claim 5) (LN substrate) having a thickness of 230 μm was prepared as a piezoelectric substrate. The LN substrate was bonded to the Si substrate using an acrylic adhesive to obtain a bonded substrate. A polishing apparatus (see FIG. 3) provided with a surface plate and a ceramic substrate carrier (wafer ) is prepared, and the Si substrate side of the bonded substrate is fixed to the substrate carrier with wax so that the thickness of the LN substrate is 1.0 μm. A photolithography process was performed on the LN substrate side of the bonded substrate using a photomask prepared in advance to form a large number of electrodes. Next, an alkali-free glass substrate (wafer) having a thickness of 200 μm in which many cavities having a size of 1 mm square and a depth of 50 μm were formed was prepared as a second support substrate. Subsequently, the bonded substrate and the glass substrate were directly installed in the bonding apparatus . Then, the surface of the bonded substrate and the cavity forming surface of the glass substrate were irradiated with an argon ion beam to activate the surfaces, and both substrates were bonded under a load of about 200 kg. As a result, a three-layer structure in which the LN substrate was sandwiched between the Si substrate and the glass substrate was obtained. (i.e. preparing a wafer) The three-layer structure was taken out from the apparatus, the glass substrate side was attached to a dicing tape, and half dicing was performed. (i.e. attaching the wafer to a dicing tape and dicing the wafer to singulate the acoustic wave element) With regards to claim 4, the support substrate including a principal surface facing the piezoelectric material layer; and a bonding layer on the principal surface of the support substrate; and the hollow portion is provided in the bonding layer at a position overlapping a portion of the functional electrode in plain view as viewed in the lamination direction. Thus Hori is shown to teach all the limitations with the exception of abutting at least one pin against the acoustic wave element with the dicing tape interposed therebetween, to separate the acoustic wave element from the dicing tape and pick up the acoustic wave element; wherein a position at which the at least one pin is abutted against the acoustic wave element overlaps the hollow portion in the lamination direction, the functional electrode is an interdigital transducer (IDT) electrode. Yamamoto et al discloses in figure 2A shows an example of a surface acoustic wave element as the functional element 22. The substrate 20 is a piezoelectric substrate such as a lithium tantalate substrate or a lithium niobate substrate. The substrate 20 may be a substrate in which a piezoelectric substrate such as a lithium tantalate substrate or a lithium niobate substrate is bonded to the upper surface of a support substrate such as a sapphire substrate, a spinel substrate, an alumina substrate, or a silicon substrate. An IDT (Interdigital Transducer) 40 and a reflector 42 are formed on the substrate 10. The IDT 40 has a pair of comb electrodes 40a facing each other. The comb-shaped electrode 40a includes a plurality of electrode fingers 40b and a bus bar 40c that connects the plurality of electrode fingers 40b. The reflectors 42 are provided on both sides of the IDT 40. The IDT 40 excites surface acoustic waves on the substrate 10. The IDT 40 and the reflector 42 are formed of an aluminum layer or a metal layer such as copper. A protective film or a temperature compensation film made of an insulator may be provided on the IDT 40 and the reflector 42. Yamamoto et al discloses a surface on the opposite side of the functional element 22 of the device chip 21 is attached to the dicing tape 62. The device chip 21 is pushed up from below the dicing tape 62 with pins 64. The collet 60 is provided with a suction hole 61. By making negative pressure in the suction hole 61, the suction surface of the collet 60 sucks the surface of the device chip 21 on the functional element 22 side. One of ordinary skill in the art would have found it obvious to provide the method of Hori with a pin as taught by Yamamoto et al . The motivation for this modification would have been to provide an equivalent means for removing the diced substrate. One of ordinary skill in the art would have found it obvious to replace the general electrode of Hori with the interdigital electrode as taught by Yamamoto et al. The motivation for this modification would have been to provide equivalent electrode means. Allowable Subject Matter Claims 10-18 are allowed. Claims 2 3 and 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY E GLENN whose telephone number is (571)272-1761. The examiner can normally be reached M-F 8:00 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. December 12, 2025 /K.E.G/Examiner, Art Unit 2843 /ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Jul 11, 2024
Application Filed
Dec 12, 2025
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
96%
With Interview (+6.4%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 1057 resolved cases by this examiner. Grant probability derived from career allow rate.

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