DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 1/20/26, which has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (US 20130297888) in view of Sun (US 11086524).
With respect to claim 1, the Yamashita reference teaches a storage device, comprising:
a memory storage comprising a first storage region and a second storage region; (see fig. 4, memory 102, where there is CPU # 1 and CPU # 2 management areas)
a first controller configured to control the first storage region; (see fig. 4, CPU #1)
a second controller configured to control the second storage region; (see fig. 4, CPU #2) and
a host interface (e.g. address converters 104);
wherein the first data type of the first data is different from the second data type of the second data. (paragraphs 75-76, where the address converter 104#1 converts the address accessed in the memory 102 by the CPU #1 from the address of a single-core child thread 1 context area 406 to a child thread 1 context area 403; and where the address converter 104#2 converts the address accessed in the memory 102 by the CPU #2 from the address of a single-core child thread 2 context area 407 to a child thread 2 context area 405 [i.e. there are different threads for the different areas])
However, the Yamashita reference does not explicitly teach the memory storage is non-volatile; and the host interface is configured to: receive data and data type information representing a data type of the data from a host connected to the storage device; determine the data type of the data based on the data type information; provide, in response to the determination of the data type as a first data type, the data as first data to the first controller; and provide, in response to the determination of the data type as a second data type, the data as second data to the second controller.
The Sun reference teaches it is conventional to have the memory storage is non-volatile; (e.g. fig. 1, paragraph 38) and a host interface be configured to:
receive data and data type information representing a data type of the data from a host connected to the storage device; (column 5, lines 8-22, where there is operatively coupling each metadata shard to the operational thread pinned to the respective processor core in accordance with the mapping information contained in the processor core identification field of the I/O request for independent processing using the respective portions of the Data Storage System, memory pool and NVM-based storage sub-system exclusively assigned to the respective core)
determine the data type of the data based on the data type information; (column 5, lines 8-22, where there is operatively coupling each metadata shard to the operational thread pinned to the respective processor core in accordance with the mapping information contained in the processor core identification field of the I/O request for independent processing using the respective portions of the Data Storage System, memory pool and NVM-based storage sub-system exclusively assigned to the respective core [i.e. cores are assigned certain threads and therefore respective portions of the NVM])
provide, in response to the determination of the data type as a first data type, the data as first data to the first controller; (column 5, lines 8-22, where there is operatively coupling each metadata shard to the operational thread pinned to the respective processor core in accordance with the mapping information contained in the processor core identification field of the I/O request for independent processing using the respective portions of the Data Storage System, memory pool and NVM-based storage sub-system exclusively assigned to the respective core [i.e. a first core is assigned certain threads and therefore respective portions of the NVM]) and
provide, in response to the determination of the data type as a second data type, the data as second data to the second controller. (column 5, lines 8-22, where there is operatively coupling each metadata shard to the operational thread pinned to the respective processor core in accordance with the mapping information contained in the processor core identification field of the I/O request for independent processing using the respective portions of the Data Storage System, memory pool and NVM-based storage sub-system exclusively assigned to the respective core [i.e. a second core is assigned certain threads and therefore respective portions of the NVM])
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Yamashita reference to have the memory storage be non-volatile; and the host interface be configured to: receive data and data type information representing a data type of the data from a host connected to the storage device; determine the data type of the data based on the data type information; provide, in response to the determination of the data type as a first data type, the data as first data to the first controller; and provide, in response to the determination of the data type as a second data type, the data as second data to the second controller, as taught by the Sun reference.
The suggestion/motivation for doing so would have been to minimize latencies over all aspects of the metadata management and access path by leveraging core-affine resource partitioning with runtime environment providing lightweight user-level threads with low-latency context switching that execute within the exclusive context of a dedicated CPU core, and partitioned resources. (Sun, abstract)
Therefore it would have been obvious to combine the Yamashita and Sun references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 2, the combination of the Yamashita and Sun references teaches the storage device of claim 1, wherein the first controller is configured to: configure the first storage region into a plurality of stripe blocks, and access the first storage region in a unit of one stripe block of the plurality of stripe blocks, and wherein the first controller is configured to store the first data in a corresponding one stripe block among the plurality of stripe blocks. (Sun, column 13, line 1-14, where The metadata structures (objects, updates, original metadata) 54 can be instantiated multiple times within the memory sub-system 30 to enable: (a) Sharding and distributing of a single large metadata set, for example, metadata field 22, into a number of smaller sets (objects, shards) 54 across multiple storage devices NVMe 37 to achieve horizontal scalability across storage devices within a respective Data Storage Server 17 and across the set of all storage devices in a cluster of storage systems (as will be presented in further paragraphs); and (b) Achieving data redundancy by replicating a single metadata set 22 across multiple storage (NVMe) devices 37)
With respect to claim 3, the combination of the Yamashita and Sun references teaches the storage device of claim 2, wherein: the non-volatile memory storage comprises a plurality of non-volatile memory devices, each of the plurality of non-volatile memory devices having a plurality of memory blocks; and the one stripe block comprises one of the plurality of memory blocks in each non-volatile memory device of the plurality of non-volatile memory devices. (Sun, column 13, line 1-14, where The metadata structures (objects, updates, original metadata) 54 can be instantiated multiple times within the memory sub-system 30 to enable: (a) Sharding and distributing of a single large metadata set, for example, metadata field 22, into a number of smaller sets (objects, shards) 54 across multiple storage devices NVMe 37 to achieve horizontal scalability across storage devices within a respective Data Storage Server 17 and across the set of all storage devices in a cluster of storage systems (as will be presented in further paragraphs); and (b) Achieving data redundancy by replicating a single metadata set 22 across multiple storage (NVMe) devices 37)
Claim 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (US 20130297888) in view of Sun (US 11086524), and further view of Karr (US 20220405200).
With respect to claim 13, the combination of Yamashita and Sun references does not explicitly teach the storage device of claim 1, further comprising: a compression circuit configured to compress the first data received from the first controller and provide the compressed first data to the first storage region.
The Karr reference teaches it is conventional to have a compression circuit configured to compress the first data received from the first controller and provide the compressed first data to the first storage region. (paragraph 315, where the storage controller may assign input data blocks to a storage device within RAID stripe 610 by taking into account the space saved due to compression to ensure that each chunk of RAID stripe 610 has an equal amount of stored data)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of the Yamashita and Sun references to have a compression circuit configured to compress the first data received from the first controller and provide the compressed first data to the first storage region, as taught by the Karr reference.
The suggestion/motivation for doing so would have been to have taking into account the space saved due to compression to ensure that each chunk of RAID stripe 610 has an equal amount of stored data. (Karr, paragraph 315)
Therefore it would have been obvious to combine the Yamashita, Sun, and Karr references for the benefits shown above to obtain the invention as specified in the claim.
2. ALLOWABLE SUBJECT MATTER
Claims 4-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 recites the limitations of:
“the second data comprises a first sub-data having the second data type and a second sub-data having a third data type different from the first data type and the second data type; and
the second controller is configured to control the second storage region to store the first sub-data in a first memory block included in the second storage region, and store the second sub-data in a second memory block included in the second storage region.”
However, the closest prior art of record (see art applied above and art previously cited) does not explicitly teach or render obvious the limitations above, particularly in combination with the other limitations within the claims. The dependent claims (claims 5-12) are allowable for at least the same reasons as its respective parent claim (i.e. claim 4).
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
3. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 1-9 of the remarks) and amendments with respect to claims 1-3 and 13 have been considered, and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the Sun reference to teach the newly amended claim language as shown in the rejections above.
4. CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
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