DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/14/26 has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yi (US 20160291869).
With respect to claim 1, the Yi reference teaches a storage device, comprising:
a non-volatile memory storage comprising a first storage region and a second storage region; (e.g. fig. 1 memory cluster 400; and paragraph 48, where data storage device 300 includes a controller 310, a buffer 360, and memory cluster 400. The memory cluster 400 may be a group of memory chips, memory devices, memory packages, or scale-out storage devices (or multi-chip sets))
a first controller configured to control the first storage region to store first data in the first storage region; (e.g. fig. 3, scale out controller 411-1; paragraph 72, where first device 410-1 includes a first scale-out device 410-1A including a first scale-out controller 411-1 and a first volatile memory 413-1, channels CH11 through CH1m (where “m” is a natural number of at least 2), and first non-volatile memories NAND 470)
a second controller configured to control the second storage region to store second data in the second storage region; (e.g. fig. 3, scale out controller 411-2; paragraph 72, where second device 410-2 includes a second scale-out device 410-2A including a second scale-out controller 411-2 and a second volatile memory 413-2, channels CH21 through CH2m, and second non-volatile memories NAND 471) and
a host interface (e.g. fig. 1, interface 110 connected to controller 310) configured to:
receive data and data type information representing a data type of the data from a host connected to the storage device; (paragraph 66, where controller 310 or the at least one CPU 330 and/or 331 may define or determine a different memory management policy for each of the devices 410-1 through 410-4, 430-1 through 430-4, and 450-1 through 450-4 included in the memory cluster 400. The memory management policy may be differently defined or determined according to the control of a user or the host 200)
determine the data type of the data based on the data type information; (paragraph 66, where controller 310 or the at least one CPU 330 and/or 331 may define or determine a different memory management policy [analogous to ‘different type information’ as claimed] for each of the devices 410-1 through 410-4, 430-1 through 430-4, and 450-1 through 450-4 included in the memory cluster 400. The memory management policy may be differently defined or determined according to the control of a user or the host 200)
provide, in response to the determination of the data type as a first data type, the data as the first data to the first controller so that the first controller stores the first data in the first storage region; (paragraph 66, where the memory management policy may be differently defined or determined according to the control of a user or the host 200; and paragraph 68, where data may be classified as hot data or cold data based on an access frequency of the data written to or read from the memory cluster 400. The hot data may refer to data having a relatively high access frequency and the cold data may refer to data having a relatively low access frequency. The hot data may be stored in a first device in the memory cluster 400 and the cold data may be stored in a second device in the memory cluster 400) and
provide, in response to the determination of the data type as a second data type, the data as the second data to the second controller so that the second controller stores the second data in the second storage region, (paragraph 66, where the memory management policy may be differently defined or determined according to the control of a user or the host 200; and paragraph 68, where data may be classified as hot data or cold data based on an access frequency of the data written to or read from the memory cluster 400. The hot data may refer to data having a relatively high access frequency and the cold data may refer to data having a relatively low access frequency. The hot data may be stored in a first device in the memory cluster 400 and the cold data may be stored in a second device in the memory cluster 400)
wherein the first data type of the first data is different from the second data type of the second data. (paragraph 66, where the memory management policy may be differently defined or determined according to the control of a user or the host 200)
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yi (US 20160291869) in view of Bolkhovitin (US 20180341547).
With respect to claim 2, the Yi reference does not explicitly teach the storage device of claim 1, wherein the first controller is configured to: configure the first storage region into a plurality of stripe blocks, and access the first storage region in a unit of one stripe block of the plurality of stripe blocks, and wherein the first controller is configured to store the first data in a corresponding one stripe block among the plurality of stripe blocks.
The Bolkhovitin reference teaches it is conventional to have wherein the first controller is configured to: configure the first storage region into a plurality of stripe blocks, and access the first storage region in a unit of one stripe block of the plurality of stripe blocks, and wherein the first controller is configured to store the first data in a corresponding one stripe block among the plurality of stripe blocks. (paragraph 70, where memory 206 of main controller 130 further includes stripe map engine 650 for determining the non-volatile data storage devices 120 in which to store data and parity information for any given write command or set of write commands, for example when using a particular Redundancy Coding level (e.g., any predefined RAID level such as RAID0 to RAID6, RAID10, RAID01, and so on); and stripe map engine 650 works in conjunction with a stripe map 652 or stripe function for determining the particular data storage devices in which to store data and parity when performing any specified write operation or set of write operations)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Yi reference to have wherein wherein the first controller is configured to: configure the first storage region into a plurality of stripe blocks, and access the first storage region in a unit of one stripe block of the plurality of stripe blocks, and wherein the first controller is configured to store the first data in a corresponding one stripe block among the plurality of stripe blocks, as taught by the Bolkhovitin reference.
The suggestion/motivation for doing so would have been to store data and parity information for any given write command or set of write commands, for example when using a particular Redundancy Coding level (e.g., any predefined RAID level such as RAID0 to RAID6, RAID10, RAID01, and so on). (Bolkhovitin, paragraph 70)
Therefore it would have been obvious to combine the Yi and Bolkhovitin references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 3, the combination of the Yi and Bolkhovitin references teaches the storage device of claim 2, wherein: the non-volatile memory storage comprises a plurality of non-volatile memory devices, each of the plurality of non-volatile memory devices having a plurality of memory blocks; and the one stripe block comprises one of the plurality of memory blocks in each non-volatile memory device of the plurality of non-volatile memory devices. (Bolkhovitin, paragraph 70, where memory 206 of main controller 130 further includes stripe map engine 650 for determining the non-volatile data storage devices 120 in which to store data and parity information for any given write command or set of write commands, for example when using a particular Redundancy Coding level (e.g., any predefined RAID level such as RAID0 to RAID6, RAID10, RAID01, and so on); and stripe map engine 650 works in conjunction with a stripe map 652 or stripe function for determining the particular data storage devices in which to store data and parity when performing any specified write operation or set of write operations; and paragraph 45, where storage medium 330 includes memory devices (e.g., NVM 334-1, NVM 334-2, etc.), each of which include addressable and individually selectable blocks. Storage medium 330 includes individually selectable portions 331 (also referred to herein as a selected portion 331). In some embodiments, the individually selectable blocks (sometimes called erase blocks) are the minimum size erasable units in a flash memory device)
Claim 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yi (US 20160291869) in view of Karr (US 20220405200).
With respect to claim 13, the Yi reference does not explicitly teach the storage device of claim 1, further comprising: a compression circuit configured to compress the first data received from the first controller and provide the compressed first data to the first storage region.
The Karr reference teaches it is conventional to have a compression circuit configured to compress the first data received from the first controller and provide the compressed first data to the first storage region. (paragraph 315, where the storage controller may assign input data blocks to a storage device within RAID stripe 610 by taking into account the space saved due to compression to ensure that each chunk of RAID stripe 610 has an equal amount of stored data)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Yi reference to have a compression circuit configured to compress the first data received from the first controller and provide the compressed first data to the first storage region, as taught by the Karr reference.
The suggestion/motivation for doing so would have been to have taking into account the space saved due to compression to ensure that each chunk of RAID stripe 610 has an equal amount of stored data. (Karr, paragraph 315)
Therefore it would have been obvious to combine the Yi and Karr references for the benefits shown above to obtain the invention as specified in the claim.
2. ALLOWABLE SUBJECT MATTER
Claims 4-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 recites the limitations of:
“the second data comprises a first sub-data having the second data type and a second sub-data having a third data type different from the first data type and the second data type; and
the second controller is configured to control the second storage region to store the first sub-data in a first memory block included in the second storage region, and store the second sub-data in a second memory block included in the second storage region.”
However, the closest prior art of record (see art applied above and art previously cited) does not explicitly teach or render obvious the limitations above, particularly in combination with the other limitations within the claims. The dependent claims (claims 5-12) are allowable for at least the same reasons as its respective parent claim (i.e. claim 4).
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
3. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 1-9 of the remarks) and amendments with respect to claims 1-3 and 13 have been considered; and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the Yi reference to teach the newly amended claim language as shown in the rejections above.
4. CLOSING COMMENTS
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
Prosecution Insights