DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 21, 22, 27-29, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Oterhals et al. (US 9,881,401), “Oterhals”, in view of Huck (US 2003/0131205).
2. As per claim 21, Oterhals discloses a memory circuit [“memory” 2, figure 3]; and a control circuit [“memory controller” 4, figure 3] configured to store a plurality of data values to the memory circuit [“memory” 2, figure 3], wherein to store the plurality of data values, the control circuit is further configured to: compare a given one of the plurality of data values to one or more data patterns [comparing new data signatures to existing data signatures, abstract]; based on a determination that the given data value does not correspond to one of the one or more data patterns [if does not match, abstract], perform an associated write operation to store the given data value [writing a new tile value, abstract]; and based on a determination that the given data value corresponds to one of the one or more data patterns [if matches, abstract], bypass the associated write operation [no data write, abstract].
Oterhals does not disclose expressly that the data values are included in a received write operation.
Huck discloses specifier data values included in an data transfer instruction in the abstract.
Oterhals and Huck are analogous art because they are from the same field of endeavor of graphics storage system control.
Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Oterhals by including the data block system as taught by Huck in the abstract.
The motivation for doing so would have been data transfer efficiency as expressly taught by Huck in paragraph 8.
3. As per claim 22, Oterhals discloses wherein the control circuit is further configured to maintain an address table to track associated addresses of ones of the plurality of data values that correspond to one of the one or more data patterns [comparing new data signatures to existing data signatures, abstract] [Such comparing necessarily requires a data structure for maintaining (“tracking”) correspondence(s) between the new data signatures to the existing data signatures].
4. As per claim 27, Oterhals discloses a processor circuit [GPU 1, figure 1], and wherein the control circuit is further configured to: based on the determination that the given data value corresponds to one of the one or more data patterns [if matches, abstract], send an indication signal to the processor circuit [an indication of the write bypass, abstract].
5. As per claim 28, Oterhals discloses comparing, by a computer system [“memory controller” 4, figure 3], ones of a set of data to a data pattern [comparing new data signatures to existing data signatures, abstract]; writing, by the computer system [“memory controller” 4, figure 3] to a memory circuit [“memory” 2, figure 3], a first subset of the set of data that does not match the data pattern [writing a new tile value if it does not match, abstract]; and omitting, by the computer system, a second subset of the set of data that matches the data pattern [no data write if it matches, abstract].
Oterhals does not disclose expressly that the data values are included in a received write operation.
Huck discloses specifier data values included in an data transfer instruction in the abstract.
Oterhals and Huck are analogous art because they are from the same field of endeavor of graphics storage system control.
Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Oterhals by including the data block system as taught by Huck in the abstract.
The motivation for doing so would have been data transfer efficiency as expressly taught by Huck in paragraph 8.
6. As per claim 29, Oterhals discloses identifying, by the computer system, addresses associated with the second subset [comparing new data signatures to existing data signatures, abstract] [Such comparing necessarily requires a data structure for maintaining (“tracking”) correspondence(s) between the new data signatures to the existing data signatures].
7. As per claim 34, Oterhals disclose wherein the data pattern is associated with data that is repeatedly encountered in the set of data [a data signature associated with a new data and an existing data, abstract].
8. Claims 35-37, and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Candler (US 2006/0015686) in view of Oterhals et al. (US 9,881,401), “Oterhals” and Huck (US 2003/0131205).
9. As per claim 35, Candler discloses a graphic pixel in the abstract.
Candler does not disclose expressly a memory circuit; and a processor circuit configured to store data in the memory circuit; a control circuit configured to: prior to the data being stored in the memory circuit, compare the data to a data pattern; based on a determination that a given data does not match the data pattern, perform an associated write operation to store the data in the memory circuit; and based on a determination that the given data matches the data pattern, bypass the associated write operation.
Oterhals discloses a memory circuit [“memory” 2, figure 3]; and a processor circuit [GPU 1, figure 1] configured to store data in the memory circuit [“memory” 2, figure 3]; a control circuit [“memory controller” 4, figure 3] configured to: prior to the data being stored in the memory circuit, compare the data to a data pattern [comparing new data signatures to existing data signatures, abstract]; based on a determination that a given data does not match the data pattern [if does not match, abstract], perform an associated write operation to store the data in the memory circuit [writing a new tile value, abstract]; and based on a determination that the given data matches the data pattern [if matches, abstract], bypass the associated write operation [“no data is written to the frame buffer”, abstract].
Candler and Oterhals are analogous art because they are from the same field of endeavor of graphics system control.
Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Candler by including the write suppression system as taught by Oterhals in the abstract.
The motivation for doing so would have been better power management as expressly taught by Oterhals in column 1, lines 23-25.
Candler and Oterhals do not disclose expressly that the (pixel) data are included in the write operation(s).
Huck discloses specifier data values included in an data transfer instruction in the abstract.
Candler, Oterhals, and Huck are analogous art because they are from the same field of endeavor of graphics storage system control.
Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Candler and Oterhals by including the data block system as taught by Huck in the abstract.
The motivation for doing so would have been data transfer efficiency as expressly taught by Huck in paragraph 8.
10. As per claim 36, the cited prior arts disclose wherein the data pattern corresponds to a particular background pattern in the graphics data [comparing new data signatures to existing data signatures, abstract, Oterhals].
11. As per claim 37, the cited prior arts disclose wherein the control circuit is configured to track pixel locations of the graphics data that match the data pattern [comparing new data signatures to existing data signatures, abstract, Oterhals] [Such comparing necessarily requires a data structure for maintaining (“tracking”) correspondence(s) between the new data signatures to the existing data signatures].
12. As per claim 40, the cited prior arts disclose wherein the control circuit is further configured to: based on the determination that the given pixel matches the data pattern [if matches, abstract, Oterhals], send an indication signal to the processor circuit [an indication of the write bypass, abstract, Oterhals].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
A. Allowable Subject Matter
Claims 23-26, 30-33, 38, and 39 are objected to.
The closest prior art of record, “Oterhals” discloses a signature based write suppression in the abstract.
The primary reasons for allowance of claim 23 in the instant application is the combination with the inclusion in these claims that “wherein the control circuit is further configured to: receive a read operation to access one of the plurality of data values; and based on a determination that the read operation includes an associated address included in the address table, return a data value associated with one data pattern of the one or more data patterns”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 26 in the instant application is the combination with the inclusion in these claims that “wherein the control circuit is further configured to: receive a read operation to access one of the plurality of data values; based on a determination that the read operation includes an associated address that is not included in the address table, use the associated address to access a stored data value from the memory circuit; and return the stored data value”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 30 in the instant application is the combination with the inclusion in these claims that “receiving, by the computer system, a command to access a given address; and based on determining that the given address is associated with the second subset, returning, by the computer system, a data value associated with the data pattern”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 33 in the instant application is the combination with the inclusion in these claims that “receiving, by the computer system, a command to access a given address; and based on determining that the given address is not associated with the second subset, reading, by the computer system based on the given address, a stored value from the memory circuit”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 38 in the instant application is the combination with the inclusion in these claims that “wherein the control circuit is further configured to: receive, from the processor circuit, a read operation to access a particular pixel location in the memory circuit; and based on a determination that the particular pixel location is associated with a pixel that matches the data pattern, return a default value for the particular pixel location”. The prior art of record neither anticipates nor renders obvious the above recited combination.
As allowable subject matter has been indicated, applicant's response must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 C.F.R. § 1.111(b) and § 707.07(a) of the MPEP.
B. Claims Rejected
Claims 21, 22, 27-29, 34-37, and 40 are rejected.
C. Direction for Future Remarks
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAE UN YU whose telephone number is (571)272-1133. The examiner can normally be reached M-F 9-5.
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/JAE U YU/Primary Examiner, Art Unit 2138
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