Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set
forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
application is eligible for continued examination under 37 CFR 1.114, and the fee set
forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
04/06/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/21/2026 is being
considered by the examiner. The submission is in compliance with the provisions of 37 CFR 1.97.
Response to Amendment
The office action is responding to the arguments filed on 04/06/2026. Claims 1-
20 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4,6-10 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over RICHTER et al. (US 20220043570 A1) in view of Benisty et al. (US 20180321987 A1) and further in view of Benisty et al. (US 11461052 B1) hereinafter RICHTER and Benisty1 and Benisty4.
Regarding claim 1, RICHTER teaches A data storage device, comprising: a
memory device; and a controller coupled to the memory device, (see Fig 2A, paragraph [0030], illustrates a storage system with NNVM memory and controller)
wherein the controller is configured to: detect that a number of entries in a submission queue (SQ) doorbell in is greater than a number of entries in a controller memory buffer (CMB) doorbell; (see Fig 3A, paragraph [0019] and [0049], illustrates memory device may determine if it requires number of new commands fetching from submission queue be greater or equal to a threshold to aggregate fetching of the commands where controller memory buffer may hold submission and completion queue)
fetch a number of commands, wherein the number of commands is equal to or less than the number of entries in the CMB doorbell; and (see Fig 3A, paragraph [0049] and [0052], illustrates memory device uses tail address to determine new commands in submission queue in determining whether to fetch commands and in step 3 performs fetching after arbitration)
decrease the number of entries in the SQ doorbell and the number of entries in the CMB doorbell by the number of commands fetched. (see Fig 3A, paragraph [0050], illustrates host device 300 updates doorbell registers correlating submission queues)
RICHTER teaches Flash storage doorbell command queue management above. However, RICHTER does not explicitly teach
wherein the controller comprises a CMB disposed in the controller, wherein a SQ is disposed in the CMB, wherein the CMB doorbell is associated with the CMB, and wherein the SQ doorbell is associated with the SQ, wherein the CMB doorbell avoids a race condition between the SQ doorbell and commands
On the other hand, Benisty1 which also relates to storage control method for
command queue management teaches wherein the controller comprises a CMB disposed in the controller, wherein a SQ is disposed in the CMB, (see Fig 4, paragraph [0070] and [0072], illustrates CQ and SQ can be resident in Controller Memory Buffer (CMB) which is inside memory controller 422 and where host can send or dispose write request to SQ)
wherein the CMB doorbell is associated with the CMB, and wherein the SQ doorbell is associated with the SQ, (see Fig 3 and 4, paragraph [0076] and [0079], illustrates writing to relevant doorbell registers for SQ and CQ where doorbell registers belong to NVMe controller)
wherein the CMB doorbell avoids a race condition between the SQ doorbell and commands (see Fig 3, paragraph [0052], illustrates at step 3 memory device controller may arbitrate between the various submission queues to select the particular submission queue from which to fetch the command, in other words to avoid race memory controller may arbitrate various submission queues to fetch particular command)
Both RICHTER and Benisty1 relate storage control method for command queue
Management (see RICHTER, abstract, and see Benisty1, abstract, regarding doorbell command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine RICHTER with Benisty1 by incorporating doorbell command queue management with SQ and CMB, as taught by
Benisty1, to enable CQ and SQ which can be resident in Controller Memory Buffer (CMB) which is inside memory controller 422 and where host can send or dispose write request to SQ and writing to relevant doorbell registers for SQ and CQ where doorbell registers belong to NVMe controller and also at step 3 memory device controller may arbitrate between the various submission queues to select the particular submission queue from which to fetch the command, in other words to avoid race memory controller may arbitrate various submission queues to fetch particular command. The combined system of RICHTER – Benisty1 allows the host device to place the submission queues and completion queues in controller memory as mentioned in paragraph [0015]. Therefore, the combination of RICHTER - Benisty1 improves performance. See Benisty1, paragraph [0020].
RICHTER in view of Benisty1 teaches Flash storage doorbell command queue management above. However, RICHTER - Benisty1 combination does not explicitly teach wherein the SQ doorbell is a doorbell that a host device rings, wherein the CMB doorbell is invisible to the host device and rung once data is in the SQ, and wherein the controller will retrieve data from the SQ only if both the SQ doorbell and the CMB doorbell have been rung
On the other hand, Benisty4 which also relates to storage control method for
command queue management teaches wherein the CMB doorbell is invisible to the host device (see Fig 3 and 4, col 8 line 39-40, illustrates the second doorbell register which maybe CMB doorbell are hidden or invisible from host 300)
wherein the SQ doorbell is a doorbell that a host device rings, (see Fig 3 and 7, col 9 line 14-16, illustrates at step 720 host rings first doorbell which maybe SQ doorbell and updates first doorbell register)
and rung once data is in the SQ, and wherein the controller will retrieve data from the SQ only if both the SQ doorbell and the CMB doorbell have been rung (see Fig 1, 3 and 8, col 9 line 37-39, illustrates at step 830 after commands is queued in first doorbell register and validated and then at step 850 controller 102 rings second doorbell register which maybe CMB doorbell to fetch command and data to be executed. In other words, when both doorbell register is rung, only then data is retrieved)
Both RICHTER, Benisty1 and Benisty4 relate storage control method for command queue Management (see RICHTER, abstract, and see Benisty1, abstract, and see Benisty4, abstract, regarding doorbell command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine RICHTER, Benisty1 with Benisty4 by incorporating doorbell command queue management with SQ and CMB, as taught by
Benisty4, to enable the second doorbell register which maybe CMB doorbell to be hidden or invisible from host 300 and at step 720 host to ring first doorbell which maybe SQ doorbell and updates first doorbell register and at step 830 after commands is queued in first doorbell register and validated and then at step 850 controller 102 to ring second doorbell register which maybe CMB doorbell to fetch command and data to be executed. The combined system of RICHTER – Benisty1 - Benisty4 allows a storage system with first and second submission queue doorbell registers to be associated with a submission queue and means for fetching and executing a command from the submission queue in the host only in response to both the first and second submission queue doorbell registers being written as mentioned in col 2, line 2-8. Therefore, the combination of RICHTER - Benisty1 - Benisty4 improves various memory management. See Benisty4, col 2, line 65-66.
Regarding claim 2, RICHTER in view of Benisty1 and further in view of Benisty4 teaches Flash storage doorbell command queue management in claim 1. However, RICHTER - Benisty1 - Benisty4 combination does not explicitly teach The data storage device of claim 1, wherein the controller is further configured to increase the number of entries in the CMB doorbell by 1 each time a new command is written to the CMB
On the other hand, RICHTER which also relates to storage control method for
command queue management teaches The data storage device of claim 1, wherein the controller is further configured to increase the number of entries in the CMB doorbell by 1 each time a new command is written to the CMB. (see Fig 3B, paragraph [0064], illustrates host device may increment tail pointers entry which are doorbell registers after submitting new entry for completion queue)
The same motivation that was utilized for combining RICHTER, Benisty1 and
Benisty4 as set forth in claim 1 is equally applicable to claim 2.
Regarding claim 3, RICHTER in view of Benisty1 and further in view of Benisty4 teaches Flash storage doorbell command queue management in claim 1. However, RICHTER - Benisty1 - Benisty4 combination does not explicitly teach The data storage device of claim 1, wherein the controller is further configured to increase the number of entries in the SQ doorbell by 1 each time a new doorbell is written to a SQ doorbell register
On the other hand, RICHTER which also relates to storage control method for
command queue management teaches The data storage device of claim 1, wherein the controller is further configured to increase the number of entries in the SQ doorbell by 1 each time a new doorbell is written to a SQ doorbell register. (see Fig 3B, paragraph [0064], illustrates host device may increment tail pointers entry which are doorbell registers after submitting new entry for submission queue)
The same motivation that was utilized for combining RICHTER, Benisty1 and
Benisty4 as set forth in claim 1 is equally applicable to claim 3.
Regarding claim 4, RICHTER in view of Benisty1 and further in view of Benisty4 teaches Flash storage doorbell command queue management in claim 1. However, RICHTER - Benisty1 - Benisty4 combination does not explicitly teach The data storage device of claim 1, wherein the controller is configured to determine whether a SQ resides in CMB
On the other hand, Benisty1 which also relates to storage control method for
command queue management teaches The data storage device of claim 1, wherein the controller is configured to determine whether a SQ resides in CMB. (see Fig 3, paragraph [0050], illustrates host device may make determination of SQ being resident in CMB to make update in SQ by sending transport layer packets)
The same motivation that was utilized for combining RICHTER, Benisty1 and
Benisty4 as set forth in claim 1 is equally applicable to claim 4.
Regarding claim 6, RICHTER in view of Benisty1 and further in view of Benisty4 teaches Flash storage doorbell command queue management in claim 1. However, RICHTER - Benisty1 - Benisty4 combination does not explicitly teach The data storage device of claim 1, wherein the controller includes a host interface module (HIM) that includes a SQ write monitor, a SQ command fetcher, and two non-volatile memory express (NVMe) doorbells
On the other hand, RICHTER which also relates to storage control method for
command queue management teaches The data storage device of claim 1, wherein the controller includes a host interface module (HIM) that includes a SQ write monitor, a SQ command fetcher, and two non-volatile memory express (NVMe) doorbells. (see Fig 3 and 4, paragraph [0070] - [0078], illustrates command fetcher 426, doorbell registers 440, hist interface 432, access control working as write monitor 438)
The same motivation that was utilized for combining RICHTER, Benisty1 and
Benisty4 as set forth in claim 1 is equally applicable to claim 6.
Regarding claim 7, RICHTER in view of Benisty1 and further in view of Benisty4 teaches Flash storage doorbell command queue management in claim 6. However, RICHTER - Benisty1 - Benisty4 combination does not explicitly teach The data storage device of claim 6, wherein the two NVMe doorbells comprise the SQ doorbell and the CMB doorbell
On the other hand, RICHTER which also relates to storage control method for
command queue management teaches The data storage device of claim 6, wherein the two NVMe doorbells comprise the SQ doorbell and the CMB doorbell. (see Fig 3, paragraph [0048] and [0063], illustrates 2 doorbell registers one being SQ tail doorbell register and another one being CQ head doorbell register)
The same motivation that was utilized for combining RICHTER, Benisty1 and
Benisty4 as set forth in claim 1 is equally applicable to claim 7.
Regarding claim 8, RICHTER in view of Benisty1 and further in view of Benisty4 teaches Flash storage doorbell command queue management in claim 6. However, RICHTER - Benisty1 - Benisty4 combination does not explicitly teach The data storage device of claim 6, wherein the SQ write monitor is configured to monitor write access towards SQs implemented in CMB
On the other hand, Benisty1 which also relates to storage control method for
command queue management teaches The data storage device of claim 6, wherein the SQ write monitor is configured to monitor write access towards SQs implemented in CMB. (see Fig 4, paragraph [0073], illustrates command parser configured to monitor buses to CMB and further configured to parse NVMe commands access from host)
The same motivation that was utilized for combining RICHTER, Benisty1 and
Benisty4 as set forth in claim 1 is equally applicable to claim 8.
Regarding claim 9, RICHTER in view of Benisty1 and further in view of Benisty4 teaches Flash storage doorbell command queue management in claim 8. However, RICHTER - Benisty1 - Benisty4 combination does not explicitly teach The data storage device of claim 8, wherein when a host device writes a new command, an entry is made in the CMB doorbell
On the other hand, RICHTER which also relates to storage control method for
command queue management teaches The data storage device of claim 8, wherein when a host device writes a new command, an entry is made in the CMB doorbell. (see Fig 4, paragraph [0073], illustrates host device issues write command to CQ doorbell register and reviews CQ entry)
The same motivation that was utilized for combining RICHTER, Benisty1 and
Benisty4 as set forth in claim 1 is equally applicable to claim 9.
Regarding claim 10, RICHTER in view of Benisty1 and further in view of Benisty4 teaches Flash storage doorbell command queue management in claim 6. However, RICHTER - Benisty1 - Benisty4 combination does not explicitly teach The data storage device of claim 6, wherein the SQ command fetcher is configured to fetch commands when both doorbells indicate that a command is pending in a relevant SQ
On the other hand, RICHTER which also relates to storage control method for
command queue management teaches The data storage device of claim 6, wherein the SQ command fetcher is configured to fetch commands when both doorbells indicate that a command is pending in a relevant SQ. (see Fig 3, paragraph [0051], illustrates in step 2 memory device is notified of pending commands in SQ and step 3 fetches command based on arbitration)
The same motivation that was utilized for combining RICHTER, Benisty1 and
Benisty4 as set forth in claim 1 is equally applicable to claim 10.
Regarding claim 18, RICHTER teaches A data storage device, comprising: means to store data; and a controller coupled to the means to store data, (see Fig 2A, paragraph [0030], illustrates a storage system with NNVM memory and controller)
wherein the controller is configured to: maintain a first doorbell corresponding to a submission queue (SQ); maintain a second doorbell corresponding to a controller memory buffer (CMB); and (see Fig 3, paragraph [0048] and [0063], illustrates 2 doorbell registers one being SQ tail doorbell register and another one being CQ head doorbell register)
fetch a number of commands from the CMB, wherein the number of commands is equal to or less than a number of entries in the second doorbell. (see Fig 3A, paragraph [0049] and [0052], illustrates memory device uses tail address to determine new commands in submission queue in determining whether to fetch commands and in step 3 performs fetching after arbitration)
RICHTER teaches Flash storage doorbell command queue management above. However, RICHTER does not explicitly teach
wherein the SQ is disposed in the CMB and wherein the CMB is disposed in the controller, wherein the second doorbell avoids a race condition between the first doorbell and commands
On the other hand, Benisty1 which also relates to storage control method for
command queue management teaches wherein the SQ is disposed in the CMB and wherein the CMB is disposed in the controller, (see Fig 4, paragraph [0070] and [0072], illustrates CQ and SQ can be resident in Controller Memory Buffer (CMB) which is inside memory controller 422 and where host can send or dispose write request to SQ)
wherein the second doorbell avoids a race condition between the first doorbell and commands (see Fig 3, paragraph [0052], illustrates at step 3 memory device controller may arbitrate between the various submission queues to select the particular submission queue from which to fetch the command, in other words to avoid race memory controller may arbitrate various submission queues to fetch particular command)
Both RICHTER and Benisty1 relate storage control method for command queue
Management (see RICHTER, abstract, and see Benisty1, abstract, regarding doorbell command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine RICHTER with Benisty1 by incorporating doorbell command queue management with SQ and CMB, as taught by
Benisty1, to enable CQ and SQ which can be resident in Controller Memory Buffer (CMB) which is inside memory controller 422 and also at step 3 memory device controller may arbitrate between the various submission queues to select the particular submission queue from which to fetch the command, in other words to avoid race memory controller may arbitrate various submission queues to fetch particular command. The combined system of RICHTER – Benisty1 allows the host device to place the submission queues and completion queues in controller memory as mentioned in paragraph [0015]. Therefore, the combination of RICHTER - Benisty1 improves performance. See Benisty1, paragraph [0020].
RICHTER in view of Benisty1 teaches Flash storage doorbell command queue management above. However, RICHTER - Benisty1 combination does not explicitly teach wherein the first doorbell is a doorbell that a host device rings, wherein the second doorbell is invisible to the host device and rung once data is in the SQ, and wherein the controller will retrieve data from the SQ only if both the SQ doorbell and the CMB doorbell have been rung
On the other hand, Benisty4 which also relates to storage control method for
command queue management teaches wherein the second doorbell is invisible to the host device, (see Fig 3 and 4, col 8 line 39-40, illustrates the second doorbell register which maybe CMB doorbell are hidden or invisible from host 300)
wherein the first doorbell is a doorbell that a host device rings, (see Fig 3 and 7, col 9 line 14-16, illustrates at step 720 host rings first doorbell which maybe SQ doorbell and updates first doorbell register)
and rung once data is in the SQ, and wherein the controller will retrieve data from the SQ only if both the first doorbell and the second doorbell have been rung (see Fig 1, 3 and 8, col 9 line 37-39, illustrates at step 830 after commands is queued in first doorbell register and validated and then at step 850 controller 102 rings second doorbell register which maybe CMB doorbell to fetch command and data to be executed. In other words, when both doorbell register is rung, only then data is retrieved)
Both RICHTER, Benisty1 and Benisty4 relate storage control method for command queue Management (see RICHTER, abstract, and see Benisty1, abstract, and see Benisty4, abstract, regarding doorbell command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine RICHTER, Benisty1 with Benisty4 by incorporating doorbell command queue management with SQ and CMB, as taught by
Benisty4, to enable the second doorbell register which maybe CMB doorbell to be hidden or invisible from host 300 and at step 720 host to ring first doorbell which maybe SQ doorbell and updates first doorbell register and at step 830 after commands is queued in first doorbell register and validated and then at step 850 controller 102 to ring second doorbell register which maybe CMB doorbell to fetch command and data to be executed. The combined system of RICHTER – Benisty1 - Benisty4 allows a storage system with first and second submission queue doorbell registers to be associated with a submission queue and means for fetching and executing a command from the submission queue in the host only in response to both the first and second submission queue doorbell registers being written as mentioned in col 2, line 2-8. Therefore, the combination of RICHTER - Benisty1 - Benisty4 improves various memory management. See Benisty4, col 2, line 65-66.
Regarding claim 19, RICHTER in view of Benisty1 and further in view of Benisty4 teaches Flash storage doorbell command queue management in claim 18. However, RICHTER - Benisty1 - Benisty4 combination does not explicitly teach The data storage device of claim 18, wherein the SQ is disposed in the CMB
On the other hand, RICHTER which also relates to storage control method for
command queue management teaches The data storage device of claim 18, wherein the SQ is disposed in the CMB. (see Fig 3A, paragraph [0044], illustrates SQ maybe stored in controller memory buffer CMB)
The same motivation that was utilized for combining RICHTER, Benisty1 and
Benisty4 as set forth in claim 18 is equally applicable to claim 19.
Regarding claim 20, RICHTER in view of Benisty1 and further in view of Benisty4 teaches Flash storage doorbell command queue management in claim 18. However, RICHTER - Benisty1 - Benisty4 combination does not explicitly teach The data storage device of claim 18, wherein the controller is configured to monitor write access towards the SQ
On the other hand, Benisty1 which also relates to storage control method for
command queue management teaches The data storage device of claim 18, wherein the controller is configured to monitor write access towards the SQ (see Fig 4, paragraph [0073], illustrates command parser configured to monitor buses to CMB and further configured to parse NVMe commands access from host)
The same motivation that was utilized for combining RICHTER, Benisty1 and
Benisty4 as set forth in claim 18 is equally applicable to claim 20.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable
over RICHTER in view of Benisty1 and further in view of Benisty4 and further in view of BENISTY et al. (US 20210042039 A1) hereinafter BENISTY2.
Regarding claim 5, RICHTER in view of Benisty1 and further in view of Benisty4 teaches Flash storage doorbell command queue management in claim 1. However, RICHTER - Benisty1 - Benisty4 combination does not explicitly teach The data storage device of claim 1, wherein the controller is configured to not fetch a number of commands that is greater than the number of entries in the CMB doorbell
On the other hand, BENISTY2 which also relates to storage control method for
command queue management teaches The data storage device of claim 1, wherein the controller is configured to not fetch a number of commands that is greater than the number of entries in the CMB doorbell. (see Fig 3 and 4, paragraph [0066] and [0072], illustrates host device keeps track entry to completion queue and issues TLP to CQ doorbell register indicating entry review of completion queue and command executer 436 is configured to arbitrate and execute commands there were fetched and parsed from SQ. In other words, command executer arbitrates the entries from SQ)
Both RICHTER, Benisty1, Benisty4 and BENISTY2 relate storage control method for command queue Management (see RICHTER, abstract, see Benisty1, abstract, see Benisty4, abstract, and see BENISTY2, abstract, regarding doorbell command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine RICHTER - Benisty1 - Benisty4 combination with BENISTY2 by incorporating doorbell command queue management with SQ and CMB, as taught by BENISTY2, to enable command executer arbitration of the entries from SQ. The combined system of RICHTER – Benisty1 - Benisty4 - BENISTY2 allows host device to send the notice that the entry has been retrieved from the completion queue as mentioned in paragraph [0019]. Therefore, the combination of RICHTER– Benisty1 - Benisty4 - BENISTY2 improves execution performance. See BENISTY2, paragraph [0019].
Claim(s) 11-17 are rejected under 35 U.S.C. 103 as being unpatentable
over RICHTER in view of Benisty1 and further in view of Benisty4 and further in view of Benisty et al. (US 20210182219 A1) hereinafter Benisty3.
Regarding claim 11, RICHTER teaches A data storage device, comprising: a memory device; and a controller coupled to the memory device, (see Fig 2A, paragraph [0030], illustrates a storage system with NNVM memory and controller)
wherein the controller is configured to: receive an indication that a host has issued a doorbell for a submission queue (SQ); (see Fig 3, paragraph [0048], illustrates in step 2 host writes to SQ tail doorbell register in memory device)
determine that the SQ is managed in a controller memory buffer (CMB); (see Fig 2A, paragraph [0031], illustrates SQ may be stored and managed in controller memory buffer)
fetch commands from the SQ. (see Fig 3A, paragraph [0049] and [0052], illustrates in step 3 performs fetching after arbitration)
RICHTER teaches Flash storage doorbell command queue management above. However, RICHTER does not explicitly teach
wherein the SQ is disposed in the CMB, and wherein the CMB is disposed in the controller, wherein the CMB doorbell avoids a race condition between the doorbell for the SQ and commands
On the other hand, Benisty1 which also relates to storage control method for
command queue management teaches wherein the SQ is disposed in the CMB, and wherein the CMB is disposed in the controller, (see Fig 4, paragraph [0070] and [0072], illustrates CQ and SQ can be resident in Controller Memory Buffer (CMB) which is inside memory controller 422 and where host can send or dispose write request to SQ)
wherein the CMB doorbell avoids a race condition between the doorbell for the SQ and commands (see Fig 3, paragraph [0052], illustrates at step 3 memory device controller may arbitrate between the various submission queues to select the particular submission queue from which to fetch the command, in other words to avoid race memory controller may arbitrate various submission queues to fetch particular command)
Both RICHTER and Benisty1 relate storage control method for command queue
Management (see RICHTER, abstract, and see Benisty1, abstract, regarding doorbell command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine RICHTER with Benisty1 by incorporating doorbell command queue management with SQ and CMB, as taught by
Benisty1, to enable CQ and SQ which can be resident in Controller Memory Buffer (CMB) which is inside memory controller 422 and also at step 3 memory device controller may arbitrate between the various submission queues to select the particular submission queue from which to fetch the command, in other words to avoid race memory controller may arbitrate various submission queues to fetch particular command. The combined system of RICHTER – Benisty1 allows the host device to place the submission queues and completion queues in controller memory as mentioned in paragraph [0015]. Therefore, the combination of RICHTER - Benisty1 improves performance. See Benisty1, paragraph [0020].
RICHTER in view of Benisty1 teaches Flash storage doorbell command queue management. However, RICHTER - Benisty1 combination does not explicitly teach choose a minimum between a number of commands written by a host device and a number of commands having a doorbell issued for the SQ;
reduce the minimum from both the number of commands written by the host device and the number of commands having a doorbell issued for the SQ; and
On the other hand, Benisty3 which also relates to storage control method for
command queue management teaches choose a minimum between a number of commands written by a host device and a number of commands having a doorbell issued for the SQ; (see Fig 7, paragraph [0115], illustrates host defines minimum value of command queued in SQ)
reduce the minimum from both the number of commands written by the host device and the number of commands having a doorbell issued for the SQ; and (see Fig 7, paragraph [0116], illustrates minimum value of CID may be decremented by one for each new command queued in SQ)
Both RICHTER, Benisty1 and Benisty3 relate storage control method for command queue Management (see RICHTER, abstract, see Benisty1, abstract, and see Benisty3, abstract, regarding doorbell command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine RICHTER - Benisty1 combination with Benisty3 by incorporating doorbell command queue management with SQ and CMB, as taught by Benisty3, to enable host defining minimum value of command queued in SQ and minimum value of CID may be decremented by one for each new command queued in SQ. The combined system of RICHTER - Benisty1 – Benisty3 allows queue manager which is configured to manage a submission queue identifier (SQID) and to determine a submission queue fetch error as mentioned in paragraph [0011]. Therefore, the combination of RICHTER - Benisty1 - Benisty3 improves reliability. See Benisty3, paragraph [0007].
RICHTER in view of Benisty1 and further in view of Benisty3 teaches Flash storage doorbell command queue management above. However, RICHTER - Benisty1 - Benisty3 combination does not explicitly teach wherein the SQ doorbell is a doorbell that the host rings, wherein the CMB doorbell is invisible to the host and rung once data is in the SQ, and wherein the controller will retrieve data from the SQ only if both the SQ doorbell and the CMB doorbell have been rung
On the other hand, Benisty4 which also relates to storage control method for
command queue management teaches wherein the CMB doorbell is invisible to the host (see Fig 3 and 4, col 8 line 39-40, illustrates the second doorbell register which maybe CMB doorbell are hidden or invisible from host 300)
wherein the SQ doorbell is a doorbell that the host rings, (see Fig 3 and 7, col 9 line 14-16, illustrates at step 720 host rings first doorbell which maybe SQ doorbell and updates first doorbell register)
and rung once data is in the SQ, and wherein the controller will retrieve data from the SQ only if both the SQ doorbell and the CMB doorbell have been rung (see Fig 1, 3 and 8, col 9 line 37-39, illustrates at step 830 after commands is queued in first doorbell register and validated and then at step 850 controller 102 rings second doorbell register which maybe CMB doorbell to fetch command and data to be executed. In other words, when both doorbell register is rung, only then data is retrieved)
Both RICHTER, Benisty1, Benisty3 and Benisty4 relate storage control method for command queue Management (see RICHTER, abstract, and see Benisty1, abstract, and see Benisty3, abstract, and see Benisty4, abstract, regarding doorbell command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine RICHTER, Benisty1, Benisty3 with Benisty4 by incorporating doorbell command queue management with SQ and CMB, as taught by Benisty4, to enable the second doorbell register which maybe CMB doorbell to be hidden or invisible from host 300 and at step 720 host to ring first doorbell which maybe SQ doorbell and updates first doorbell register and at step 830 after commands is queued in first doorbell register and validated and then at step 850 controller 102 to ring second doorbell register which maybe CMB doorbell to fetch command and data to be executed. The combined system of RICHTER – Benisty1 - Benisty3 - Benisty4 allows a storage system with first and second submission queue doorbell registers to be associated with a submission queue and means for fetching and executing a command from the submission queue in the host only in response to both the first and second submission queue doorbell registers being written as mentioned in col 2, line 2-8. Therefore, the combination of RICHTER - Benisty1 - Benisty3 - Benisty4 improves various memory management. See Benisty4, col 2, line 65-66.
Regarding claim 12, RICHTER in view of Benisty1 and further in view of Benisty4 and further in view Benisty3 of teaches Flash storage doorbell command queue management in claim 11. However, RICHTER - Benisty1 - Benisty4 – Benisty3 combination does not explicitly teach The data storage device of claim 11, wherein a number of commands fetched is equal to the minimum
On the other hand, Benisty3 which also relates to storage control method for
command queue management teaches The data storage device of claim 11, wherein a number of commands fetched is equal to the minimum. (see Fig 7, paragraph [0116], illustrates minimum value of CID in SQ command queue which is fetched)
The same motivation that was utilized for combining RICHTER - Benisty1 - Benisty4 combination with Benisty3 as set forth in claim 11 is equally applicable to claim 12.
Regarding claim 13, RICHTER in view of Benisty1 and further in view of Benisty4 and further in view Benisty3 of teaches Flash storage doorbell command queue management in claim 11. However, RICHTER - Benisty1 - Benisty4 – Benisty3 combination does not explicitly teach The data storage device of claim 11, wherein the number of command written by the host device is equal to a number of command doorbells
On the other hand, RICHTER which also relates to storage control method for
command queue management teaches The data storage device of claim 11, wherein the number of command written by the host device is equal to a number of command doorbells. (see Fig 3A, paragraph [0049], illustrates host indicates tail doorbell register to point to number of commands in SQ)
The same motivation that was utilized for combining RICHTER - Benisty1 - Benisty4 combination with Benisty3 as set forth in claim 11 is equally applicable to claim 13.
Regarding claim 14, RICHTER in view of Benisty1 and further in view of Benisty4 and further in view Benisty3 of teaches Flash storage doorbell command queue management in claim 11. However, RICHTER - Benisty1 - Benisty4 – Benisty3 combination does not explicitly teach The data storage device of claim 11, wherein the controller is further configured to maintain two doorbells
On the other hand, RICHTER which also relates to storage control method for
command queue management teaches The data storage device of claim 11, wherein the controller is further configured to maintain two doorbells. (see Fig 3, paragraph [0048] and [0063], illustrates 2 doorbell registers one being SQ tail doorbell register and another one being CQ head doorbell register)
The same motivation that was utilized for combining RICHTER - Benisty1 - Benisty4 combination with Benisty3 as set forth in claim 11 is equally applicable to claim 14.
Regarding claim 15, RICHTER in view of Benisty1 and further in view of Benisty4 and further in view Benisty3 of teaches Flash storage doorbell command queue management in claim 14. However, RICHTER - Benisty1 - Benisty4 – Benisty3 combination does not explicitly teach The data storage device of claim 14, wherein one doorbell of the two doorbells is for the number of commands written by the host device
On the other hand, RICHTER which also relates to storage control method for
command queue management teaches The data storage device of claim 14, wherein one doorbell of the two doorbells is for the number of commands written by the host device. (see Fig 3A, paragraph [0049], illustrates tail doorbell register 312 is used to indicate number of commands from host to SQ)
The same motivation that was utilized for combining RICHTER - Benisty1 - Benisty4 combination with Benisty3 as set forth in claim 11 is equally applicable to claim 15.
Regarding claim 16, RICHTER in view of Benisty1 and further in view of Benisty4 and further in view Benisty3 of teaches Flash storage doorbell command queue management in claim 15. However, RICHTER - Benisty1 - Benisty4 – Benisty3 combination does not explicitly teach The data storage device of claim 15, wherein a second doorbell of the two doorbells is for the number of commands doorbelled for the SQ by the host device
On the other hand, RICHTER which also relates to storage control method for
command queue management teaches The data storage device of claim 15, wherein a second doorbell of the two doorbells is for the number of commands doorbelled for the SQ by the host device. (see Fig 3A, paragraph [0062], illustrates second doorbell register indicating number of SQ commands processed from completion queue)
The same motivation that was utilized for combining RICHTER - Benisty1 - Benisty4 combination with Benisty3 as set forth in claim 11 is equally applicable to claim 16.
Regarding claim 17, RICHTER in view of Benisty1 and further in view of Benisty4 and further in view Benisty3 of teaches Flash storage doorbell command queue management in claim 15. However, RICHTER - Benisty1 - Benisty4 – Benisty3 combination does not explicitly teach The data storage device of claim 14, wherein one doorbell of the two doorbells is defined in a non-volatile memory express (NVMe) standard and a second doorbell of the two doorbells is based on write and read accesses of the SQ
On the other hand, RICHTER which also relates to storage control method for
command queue management teaches The data storage device of claim 14, wherein one doorbell of the two doorbells is defined in a non-volatile memory express (NVMe) standard and a second doorbell of the two doorbells is based on write and read accesses of the SQ. (see Fig 3A, paragraph [0054], illustrates memory device uses NVMe standard to obtain command from SQ and in step 4 memory device processes read and write command using completion queue doorbell register)
The same motivation that was utilized for combining RICHTER - Benisty1 - Benisty4 combination with Benisty3 as set forth in claim 11 is equally applicable to claim 17.
Response to Arguments
Applicant’s arguments filed on 04/06/2026 have been fully considered but they
are not persuasive.
Applicant’s first argument is claims 1, 11 and 18 amendments mapping by
Primary and secondary references in page 7 of the response: Applicant respectfully submits that Benisty 1, Benisty 2, and Benisty 3 are silent regarding a CMB doorbell that is invisible to a host device.
Therefore, Richter et al., Benisty 1, Benisty 2, and Benisty 3, alone or in combination, do not teach, show, or suggest a SQ doorbell that a host device rings, a CMB doorbell that is invisible to the host device and rung once data is in the SQ, and the controller will retrieve data from the SQ only if both the SQ doorbell and the CMB doorbell have been rung, as recited in claims 1, 11, and 18, and claims dependent thereon. Withdrawal of the rejection is respectfully requested
In summary, applicant argued that primary and secondary references do not teach amended limitation CMB doorbell is invisible to host and host device rings SQ doorbell where controller will retrieve data from the SQ only if both the SQ doorbell and the CMB doorbell have been rung. The amendment necessitates adding secondary reference Benisty4 in this regard. For further clarification examiner cites portion from Benisty4. Also, for applicant’s understanding examiner would like to explain the teachings of Benisty4 and examiner’s interpretation in more detail here. See Fig 3 and 4, col 8 line 39-40, Benisty4 teaches the second doorbell register which maybe CMB doorbell are hidden or invisible from host 300. Also see Fig 3 and 7, col 9 line 14-16, Benisty4 teaches at step 720 host rings first doorbell which maybe SQ doorbell and updates first doorbell register. Also see Fig 1, 3 and 8, col 9 line 37-39, Benisty4 teaches at step 830 after commands is queued in first doorbell register and validated and then at step 850 controller 102 rings second doorbell register which maybe CMB doorbell to fetch command and data to be executed. In other words, when both doorbell register is rung, only then data is retrieved. In the cited portions along with figures clearly teaches CMB doorbell is invisible from host and host device rings 1st doorbell and controller will retrieve data from the SQ only if both doorbells have been rung. Thus, the rejection of amended claims 1, 11 and 18 are maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBIR K CHOWDHURY whose telephone number is (703)756-1207. The examiner can normally be reached Monday-Friday 8:30 - 5:00 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
Prosecution Insights