DETAILED ACTION
This office action is in response to application filed on 7/11/2026.
Claims 1 – 20 are pending.
Priority is claimed to Chinese application CN202311423839.1 (filed on 10/30/2023).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 7, 9, 11 15, 17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Qu et al (US 20230168937, hereinafter Qu).
As per claim 1, Qu discloses: A method of controlling a virtual machine, comprising:
obtaining, during a physical machine starting process, processor configuration information of the physical machine from a memory of the physical machine, the processor configuration information indicating a to-be-configured processor in the physical machine, and the to-be-configured processor being a physical processor bound to a virtual processor of a virtual machine; (Qu figure 7 and [0074]: “In response to the request, the virtual machine management service may evaluate 704 the virtual machine image profile provided in the request (either within the virtual machine image package or as a standalone profile provided in the request) to determine the CPU pinning requirements for the one or more vCPUs of the VNFs or other virtual machine that is to be implemented using the virtual machine image. For instance, the virtual machine image profile may specify a requirement that the VNFs are to be implemented with low latency throughput. This may serve as an indication that the vCPUs of the VNFs are to be implemented on dedicated, non-shareable processor cores. Further, the virtual machine image profile may specify a requirement that data plane vCPUs of the VNFs are to be maintained in separate processor cores.”)
determining the to-be-configured processor based on the processor configuration information; and configuring the to-be-configured processor into a first state, when being in the first state, the to-be-configured processor being isolated from the physical machine and supporting an invocation by a virtual machine in the physical machine. (Qu [0077]: “Based on this identification of the current assignments on the server CPU sockets, the virtual machine management service may determine 708 whether there is available CPU capacity that can be allocated for instantiation of the virtual machine image and to implement the VNFs.”; [0082]: “if the virtual machine management service determines that the available processor capacity, if used, would satisfy the set of requirements set forth in the virtual machine image profile, the virtual machine management service instantiates 714 the virtual machine image using the available processor capacity subject to the CPU pinning requirements specified in the virtual machine image profile. For instance, if the CPU pinning requirements indicate that a dedicated processor core is required for each vCPU (e.g., data plane vCPU, control plane vCPU, etc.) of a VNF, the virtual machine management service may allocate at least two processor cores that may be used to implement the VNF. Any unused capacity of these at least two processor cores may be reserved for the VNF such that, in response to subsequent requests to instantiate another virtual machine image, the virtual machine management service may determine that these at least two processor cores and the CPUs therein are unavailable for use in instantiating the other virtual machine image.”)
As per claim 3, Qu further discloses:
The method of claim 1, further comprising, after configuring the to-be-configured processor into the first state: configuring the virtual machine in the physical machine into a second state, when being in the second state, the virtual machine performing data processing by using processor resources of the to-be-configured processor. (Qu [0064])
As per claim 7, Qu further discloses:
The method of claim 3, further comprising: after configuring the virtual machine in the physical machine into the second state, controlling the virtual machine to perform data processing by using processor resources of a target to-be-configured processor, the target to-be-configured processor being a physical processor that is in the first state and has an association with the virtual machine. (Qu [0082])
As per claim 9, it is the device variant of claim 1 and is therefore rejected under the same rationale.
As per claim 11, it is the device variant of claim 3 and is therefore rejected under the same rationale.
As per claim 15, it is the device variant of claim 7 and is therefore rejected under the same rationale.
As per claim 17, it is the non-transitory computer-readable storage medium variant of claim 1 and is therefore rejected under the same rationale.
As per claim 19, it is the non-transitory computer-readable storage medium variant of claim 3 and is therefore rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 10 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Qu, in view of Teng et al (USPAT 12299455, hereinafter Teng).
As per claim 2, Qu did not teach:
The method of claim 1, wherein configuring the to-be-configured processor into the first state comprises: taking the to-be-configured processor offline; and controlling, according to virtual machine configuration information stored in the memory of the physical machine, the offline to-be-configured processor to perform initialization to configure the to-be-configured processor into the first state, the offline to-be-configured processor being not registered with a scheduler of the physical machine during initialization.
However, Teng teaches:
The method of claim 1, wherein configuring the to-be-configured processor into the first state comprises: taking the to-be-configured processor offline; and controlling, according to virtual machine configuration information stored in the memory of the physical machine, the offline to-be-configured processor to perform initialization to configure the to-be-configured processor into the first state, the offline to-be-configured processor being not registered with a scheduler of the physical machine during initialization. (Teng col 13, lines 45 – col 16, line 17.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Teng into that of Qu in order to have the configuring the to-be-configured processor into the first state comprises: taking the to-be-configured processor offline; and controlling, according to virtual machine configuration information stored in the memory of the physical machine, the offline to-be-configured processor to perform initialization to configure the to-be-configured processor into the first state, the offline to-be-configured processor being not registered with a scheduler of the physical machine during initialization. Teng has shown that the claimed limitations are merely commonly known and used steps for configuring processors to be used by VMs, and thus applicants have merely claimed the combination of known parts in the field to achieve predictable results and allocate resources to VM and is therefore rejected under 35 USC 103.
As per claim 10, it is the device variant of claim 2 and is therefore rejected under the same rationale.
As per claim 18, it is the non-transitory computer-readable storage medium variant of claim 2 and is therefore rejected under the same rationale.
Claim(s) 4, 5, 12, 13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Qu, in view of Kaplan et al (US 20170220369, hereinafter Kaplan).
As per claim 4, Qu did not teach:
The method of claim 3, wherein the processor resources comprise at least one of a register, a predetermined instruction, and an interrupt controller.
However, Kaplan teaches:
The method of claim 3, wherein the processor resources comprise at least one of a register, a predetermined instruction, and an interrupt controller. (Kaplan [0023]: interrupt control units.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kaplan into that of Qu in order to have the processor resources comprise at least one of a register, a predetermined instruction, and an interrupt controller. Kaplan [0023] has shown that the claimed limitations are merely commonly known and used part of allocating resources to VMs, and thus applicants have merely claimed the combination of known parts in the field to achieve predictable results and allocate resources to VM and is therefore rejected under 35 USC 103.
As per claim 5, the combination of Qu and Kaplan further teach:
The method of claim 4, wherein configuring the virtual machine in the physical machine into the second state comprises: establishing an association between the virtual machine in the physical machine and at least one to-be-configured processor; and closing an interrupt trap-out configuration of the virtual machine, and passing through a register in the at least one to-be-configured processor to the virtual machine. (Kaplan [0029] – [0031])
As per claim 12, it is the device variant of claim 4 and is therefore rejected under the same rationale.
As per claim 13, it is the device variant of claim 5 and is therefore rejected under the same rationale.
As per claim 20, it is the non-transitory computer-readable storage medium variant of claim 5 and is therefore rejected under the same rationale.
Claim(s) 6 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Qu and Kaplan, and further in view of Das (US 20240134669).
As per claim 6, the combination of Qu and Kaplan did not teach:
The method of claim 5, wherein configuring the virtual machine in the physical machine into the second state further comprises: starting a predetermined thread synchronization instruction of the virtual machine.
However, Das teaches:
The method of claim 5, wherein configuring the virtual machine in the physical machine into the second state further comprises: starting a predetermined thread synchronization instruction of the virtual machine. (Das [0030])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Das into that of Qu and Kaplan in order to have the configuring the virtual machine in the physical machine into the second state further comprises: : establishing an association between the virtual machine in the physical machine and at least one to-be-configured processor; and closing an interrupt trap-out configuration of the virtual machine, and passing through a register in the at least one to-be-configured processor to the virtual machine. Das [0030] has shown that the claimed limitations are merely commonly known and used part of allocating resources to VMs, and thus applicants have merely claimed the combination of known parts in the field to achieve predictable results and allocate resources to VM and is therefore rejected under 35 USC 103.
As per claim 14, it is the device variant of claim 6 and is therefore rejected under the same rationale.
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Qu, in view of Saidi et al (US 11042494, hereinafter Saidi).
As per claim 8, Qu did not teach:
The method of claim 7, wherein the processor resources comprise an interrupt controller, and controlling the virtual machine to perform data processing by using the processor resources of the target to-be-configured processor comprises: controlling the virtual machine to send and receive an interrupt instruction via the interrupt controller in the target processor.
However, Saidi teaches:
The method of claim 7, wherein the processor resources comprise an interrupt controller, and controlling the virtual machine to perform data processing by using the processor resources of the target to-be-configured processor comprises: controlling the virtual machine to send and receive an interrupt instruction via the interrupt controller in the target processor. (Saidi col 3, lines 37 – 52.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Saidi into that of Qu in order to have the processor resources comprise an interrupt controller, and controlling the virtual machine to perform data processing by using the processor resources of the target to-be-configured processor comprises: controlling the virtual machine to send and receive an interrupt instruction via the interrupt controller in the target processor. Saidi col 3, lines 37 – 52 has shown that the claimed limitations are merely commonly known and used part of allocating resources to VMs, and thus applicants have merely claimed the combination of known parts in the field to achieve predictable results and allocate resources to VM and is therefore rejected under 35 USC 103.
As per claim 16, it is the device variant of claim 8 and is therefore rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Alverson et al (US 20230315191) teaches “a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.”;
Hinnershitz (US 20220245255) teaches “The secure initialization memory includes initialization instructions for launching a security runtime environment before operating systems and cryptographic keying for security handoffs. The processors are configured to retrieve the initialization instructions from the secure initialization memory at startup, execute the initialization instructions to launch the security runtime environment and retrieve at least a portion of the cryptographic keying, and generate specific keying for chip-level resources the processors by combining instruction sets of the chip-level resources and the cryptographic keying. The processors are further configured to initialize a plurality of isolated enclaves on the security runtime environment and pin chip-level resources to the plurality of enclaves according to the specific keying and by establishing exclusive cryptographic links between the chip-level resources and the plurality of enclaves.”;
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M SWIFT whose telephone number is (571)270-7756. The examiner can normally be reached Monday - Friday: 9:30 AM - 7PM.
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/CHARLES M SWIFT/Primary Examiner, Art Unit 2196
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