DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the voltage control circuit comprises: a first voltage control circuit connected between the third switch element and the fourth switch element; and a second voltage control circuit connected between the first switch element and the second switch element” as recited in claim 3 in combination with “the voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” as recited in claim 1;and
“the voltage control circuit comprises: a first transistor pair that comprises a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, and is connected between the third switch element and the fourth switch element; and a second transistor pair that comprises a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, and is connected between the first switch element and the second switch element” as recited in claim 5 in combination with the “voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” as recited in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The amendment filed 11/24/25 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows:
With respect to claim 3, the recitation of “the voltage control circuit comprises: a first voltage control circuit connected between the third switch element and the fourth switch element; and a second voltage control circuit connected between the first switch element and the second switch element” as recited in claim 3 in combination with “the voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” as recited in claim 1 is not supported by the original disclosure.
With respect to claim 5, the recitation of “the voltage control circuit comprises: a first transistor pair that comprises a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, and is connected between the third switch element and the fourth switch element; and a second transistor pair that comprises a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, and is connected between the first switch element and the second switch element” as recited in claim 5 in combination with the “voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” as recited in claim 1 is not supported by the original disclosure.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3 and 5 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
With respect to claim 3, the recitation of “the voltage control circuit comprises: a first voltage control circuit connected between the third switch element and the fourth switch element; and a second voltage control circuit connected between the first switch element and the second switch element” as recited in claim 3 in combination with “the voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” as recited in claim 1 is not supported by the original disclosure.
As far as can be understood claim 3 recites limitations directed towards Fig. 5 and/or 8 of Applicant’s instant drawings. Whereas the recitation of “the voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” is drawn to one of 6 of Fig. 3 and/or 6B1 of Fig. 6. It can be seen that Figs. 3 and 6 do not include “the voltage control circuit comprises: a first voltage control circuit connected between the third switch element and the fourth switch element; and a second voltage control circuit connected between the first switch element and the second switch element” as recited in claim 3. Furthermore, the drawing of Figs. 5 and 8 do not include “the voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” as recited in claim 1.
With respect to claim 5, the recitation of “the voltage control circuit comprises: a first transistor pair that comprises a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, and is connected between the third switch element and the fourth switch element; and a second transistor pair that comprises a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, and is connected between the first switch element and the second switch element” as recited in claim 5 in combination with the “voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” as recited in claim 1 is not supported by the original disclosure.
As far as understood claim 5 is drawn to circuit as constructed in Fig. 8. It can be seen that the circuit of Fig. 8 does not include “the voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” as recited in claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 3, the recitation of “the voltage control circuit comprises: a first voltage control circuit connected between the third switch element and the fourth switch element; and a second voltage control circuit connected between the first switch element and the second switch element” as recited in claim 3 in combination with “the voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” as recited in claim 1 cannot be understood, since is not supported by the original disclosure.
As far as can be understood claim 3 recites limitations directed towards Fig. 5 and/or 8 of Applicant’s instant drawings. Whereas the recitation of “the voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” is drawn to one of 6 of Fig. 3 and/or 6B1 of Fig. 6. It can be seen that Figs. 3 and 6 do not include “the voltage control circuit comprises: a first voltage control circuit connected between the third switch element and the fourth switch element; and a second voltage control circuit connected between the first switch element and the second switch element” as recited in claim 3. Furthermore, the drawing of Figs. 5 and 8 do not include “the voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” as recited in claim 1.
With respect to claim 5, the recitation of “the voltage control circuit comprises: a first transistor pair that comprises a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, and is connected between the third switch element and the fourth switch element; and a second transistor pair that comprises a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, and is connected between the first switch element and the second switch element” as recited in claim 5 in combination with the “voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” as recited in claim 1 cannot be understood, since is not supported by the original disclosure.
As far as understood claim 5 is drawn to circuit as constructed in Fig. 8. It can be seen that the circuit of Fig. 8 does not include “the voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element” as recited in claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aoike (USPN 7,417,461).
With respect to claim 1, Aoike discloses, in Figs. 2 and 3, a semiconductor device (Fig. 2, details of 143 and 141 disclosed in Fig. 3) outputting differential signals (signals on 1121 and 1122), the semiconductor device comprising:
first upper and lower arms (1111 with 1113) that comprise a first switch element (1111) and a second switch element (1113) and output a first signal (1121) by operating the first switch element and the second switch element complementarily (1111 and 11113 are operated complementary, see Col. 5 lines 44-51 and Col. 6 lines 30-34), wherein the first switch element is on a side of a first potential (upper rail voltage connected to 1101), and the second switch element is on a side of a second potential lower than the first potential (lower rail voltage, e.g., ground, connected to 1102) and is connected in series with the first switch element (switches 1111 and 1113 are serially connected);
second upper and lower arms that are disposed in parallel with the first upper and lower arms (1112 with 1114), comprise a third switch element (1112) and a fourth switch element (1114), and generate and output a second signal (1122) having a potential that changes complementarily with respect to the first signal by operating the third switch element and the fourth switch element complementarily (the circuit operates as claimed due to the complementary activation of 1112 with 1114 respective to 1111 and 1113, see Col. 5 lines 44-51 and Col. 6 lines 30-34), wherein the third switch element is on the side of the first potential (upper rail voltage via 1101), and the fourth switch element is on the side of the second potential (lower rail voltage via 1102) and is connected in series with the third switch element (1112 and 1114 are serially connected); and
a voltage control circuit (Fig. 3, e.g., 1203 and 1205, of Fig. 3) that is connected to the first upper and lower arms and the second upper and lower arms (via 1144 and 1142) and limits voltage amplitudes of the first signal and the second signal based on a bias voltage (at least one of the bias voltages of the gate to drain voltage of 1201 supplied to the gate of 1203 and the gate to drain voltage of 1204 supplied to the gate of 1205. The above bias voltages set the gate voltage of 1203/1205 thus limiting the voltage amplitudes according to the amount of output current. For instance, when 1203 and 1205 are active via 1144 and 1142, during the normal state, the amplitude of the output of Fig. 2 is limited compared to the preempahsis operation when a larger amplitude flows through the circuit of Fig. 2, see Col. 1 lines 46-52 and Col. 6 lines 54-67), wherein
the voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element (1205 of Fig. 3 is connected as claimed when 142 is closed and 1141of Fig. 2/drain of 1205 of Fig. 3 is connected between current source 1101, the upper rail voltage, and the first and third switches 1111 with 1112).
With respect to claim 4, the semiconductor device according to claim 1, wherein the voltage control circuit (1203 and 1205 of Fig. 3 in place of 1143 and 1141 of Fig. 2) comprises:
a first voltage control circuit (1205 of Fig. 3/1141 of Fig. 2) comprising a first conductivity type transistor (NMOS transistor 1205) that is connected (when 1142 is closed) between a first current source (1101) provided at the first potential (upper rail voltage) and the first switch element (1111) and is connected between the first current source (1101) and the third switch element (1112); and
a second voltage control circuit (1203 of Fig. 3/1143 of Fig. 2) comprising a second conductivity type transistor (PMOS transistor 1203) that is connected between (when 1144 is closed) a second current source (1102) provided at the second potential (lower supply rail/ground) and the second switch element (1113) and is connected between the second current source (1102) and the fourth switch element (1114).
Allowable Subject Matter
Allowable subject matter could not be determined due to the issues discussed above with respect to the new matter and rejections under 35 U.S.C. section 112.
Response to Arguments
Applicant's arguments filed 11/24/2025 have been fully considered but they are not persuasive.
Applicant’s arguments that “Aoike's ‘preemphasis circuit’ is not a voltage-control circuit that sets/limits steady-state amplitude” is not persuasive. It is noted that terminals 1121 and 1122 include an external terminating resistance to “allow current to flow from the output terminal 1121 to the output terminal 1222” (see Col. 5 lines 57-61). Thus, the voltage across the above terminals, i.e., the output voltage, will be proportional to the current sourced to and/or sunk from 1121 and 1222 due to Ohm’s law, i.e., (V=IR where V equals voltage, I equals current and R equals resistance). Furthermore, during a preempahsis (i.e., “at the timing of a transition of the input/output signal”, see Col. 6 lines 13-14) when switch 1145 is closed and switches 1144 and 1142 of Fig. 2 are open a current equal to I+∆I will be applied to the terminals of 1121 and 1122 (see Col. 6 lines 58-60). Furthermore, during stead state (after preemphasis) the 1144 and 11442 are closed and 1145 is open (see Col. 6 lines 41-42) such that the output current is equal to ∆I (see Col. 6 lines 54-57) which is lower than I+∆I by a value of ∆I. Therefore, during preemphasis the currents 1143 and 1141 are not connected to 1101 and 1102 and the output current has the larger value of I+∆I. This would cause the output voltage across the termination resistance to be equal to (I+∆I)*R, where R is the resistance value of the termination resistance. Furthermore, during steady state 1143 and 1141 are connected to 1101 and 1102 such the output current is the lower ∆I causing the output voltage across the termination resistance to be equal to ∆I*R. Thus, the output voltage is larger during preemphasis by a I*R value than it is in the steady state operation. Furthermore, the current is reduced in the steady state operation according to the connection of 1143 and 1141 to 1101 and 1102 (further details of 1141-1145 disclosed in Fig. 3). Therefore it can be seen it is the operation of 1141-1144 that reduces the output current amplitude, and thus the output voltage amplitude across the termination resistance. Thus, the above circuitry operates to limit both the current and voltage amplitude of the circuit of Fig. 2 during steady state.
The arguments that “the claimed circuit is designed to limit the steady-state voltage amplitude, whereas Aoike's circuits (1203, 1205) are designed to increase the current during signal transitions to achieve pre-emphasis” and that the “Office's interpretation conflates ‘limiting amplitude’ with ‘providing transient current enhancement,’ which are two technically opposite concepts” are not persuasive. This is because, as discussed above, the current limiting during the stead state operation is provided by 1141-1144 becoming operative to reduce the output current amplitude and proportionally the output voltage amplitude across the external termination resistance. Therefore, the reducing of the current in the steady state provides for such a voltage amplitude limiting during the steady state operation when compared to the preemphasis operation. Thus, the concepts are not “opposite” as alleged, since a limiting of current (during steady state) will limit voltage due to Ohm’s law.
Applicant states:
“Aoike teaches that, during the steady state, a current (∆I) among the current flowing through the current sources 1101 and 1102 flows through the current source 1141 or 1143; and during the preemphasis, all the current flowing through the current sources 1101 and 1102 flows between the output terminals 1121 and 1122. The output amplitude is therefore (I+∆I)”.
Examiner agrees with Applicant’s above statement. It can be seen that Aoike describes reducing the current amplitude (through the operation of 1141-144) during the stead state operation as compared to the full current operation during preemphasis when 1141 and 1142 are removed from the circuit by opening 1142 and 1144.
Examiner disagrees with the statement that “Aoike's transistors 1203 and 1205 constitute a preemphasis circuit, whose purpose is to inject additional current ∆I during the preemphasis to suppress dulling of edge portions while keeping the power consumption of the entire output circuit”. Aoikes’ transistors 1203 and 1205 do not provide for preemphasis since 1142 and 1144 are open during preemphasis (see Col. 6 lines 41-43). Rather, 1203 and 1205 are connected via 1142 and 1144 during the steady state (see Col. 6 lines 41-43 and lines 54-57). Therefore, it is 1203 and 1205 that are responsible for reducing the output current amplitude level during the steady state and thus reducing the output voltage amplitude across the external termination resistance. Whereas, during preemphasis 1142 and 1142 are open such that the full value of 1101 and 1102 are provided at the output (see Col. 6 lines 58-61). Therefore, it can be seen that the amplitude boosting during preemphasis is provided by applying the full values of 1101 and 1102, and the level reducing in the steady state is caused by connected 1141 and 1143 to 1101 and 1102 to provide for the reduced levels during stead state operation. Thus, 1203 and 1205 of Fig. 3 (i.e.., 1143 and 1141) do not inject additional current during preemphasis as alleged by Applicant.
The argument that the circuit of Aoike “does not set or limit the steady-state amplitude, and therefore differs from the voltage control circuit as recited in amended claim 1 that limits voltage amplitude based on a bias voltage” is not persuasive for the reasons discussed above. Mainly that it is the circuitry of Fig. 3 within Fig. 2 that reduces the current during the steady state and that a reduction in current will proportionately reduce the output voltage across the termination resistance.
The argument “as shown in FIG. 2 of Aoike, the current source 1141 is connected in parallel with the main current source 1101, and they together provide current to the differential pair, rather than one being connected in series with the other” and therefore fails to teach or disclose the features ‘the voltage control circuit is connected between a current source provided at the first potential and the first switch element, and is connected between the current source and the third switch element’ as recited in amended claim 1” is not persuasive.
This is because current sources 1101 and 1141 are serially connected when 1142 is closed (i.e., during the steady state operation) and current flows from 1101 into 1141, thus 1141 sinking/removing a ∆I current from 1101 when 1142 is closed. Current sources 1101 and 1141 are not connected in parallel as applicant alleges. Thus, the circuit is connected and operative as claimed via the third switch element 1142. See Examiner’s markup of Figs. 2 and 3 below which shows the current flow from 1101 to 1141 (1205 of Fig. 3).
Examiner’s Markup of Fig. 2 showing current flow
PNG
media_image1.png
392
570
media_image1.png
Greyscale
Examiner’s Markup of Fig. 3 showing current flow
PNG
media_image2.png
428
741
media_image2.png
Greyscale
Cited Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Williams et al. (USPN 5,896,069) discloses a switched circuit having four switches that operate in a complementary fashion (i.e., Q1-Q4 of Fig. 3) and two voltage control circuits (Q13 and Q14) that are controlled to limit the voltage amplitude (i.e., clamp the voltage swing, see Col. 3 lines 32-67) of the circuit and are connected substantially similar to that of the voltage control circuits of Fig.3 and 6 of Applicant’s instant invention.
Shing (USPN 6,005,438) discloses a voltage control circuit (207 of Fig. 2) for limiting the voltage amplitude of a switched device (201 of Fig. 2).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS J. HILTUNEN/ Primary Examiner, Art Unit 2849