The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Embodiment A1: Figure 1A and Embodiment B1: Figure 3A in the reply filed on 12/15/2025 is acknowledged. The applicant stated that claims 1-7, 9-17 and 19-20 corresponds to Fig.1A and claims 1-9, 11-19 corresponds to Fig.3A. Upon further review, claims 9-10 and 19-20 do not correspond to elected Fig.3A as these claims are directed to the trigger signal being generated according to an output change of the first power unit or a load prediction signal of the first power unit of non-elected Fig.3B (and do not require the detection circuit+ slew rate of elected Fig.3A, claims 8, 18) as discussed in applicant’s published disclosure in pars [0012, 0039-0041]. Fig.1A is a generic system to Figs.3A and 3B. Fig.3A is directed to claims 8, 18 and requires a detection circuit within the second power unit and requires the trigger signal to be generated within the second power unit. Fig.3B, however, is directed to claims 9-19, 19-20, which does not require the detection circuit within the second power unit, and the trigger signal is generated external to the second power unit. Accordingly, claims 9-10 and 19-20 directed to non-elected Fig.3B have been herein withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 7, 11-13, 15, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Colombi et al. (2022/0224149 A1) in view of Toyoda (2017/0163088 A1).
Regarding Claim 1,
Colombi (Fig.1) teaches a power supply system, comprising:
at least one first power unit (items 126, 128; the recitation of “power unit” is nominal and structurally not limiting. 126 and 128 read on the broadest reasonable interpretation of “first power unit” as they provide power to the load) coupled between a power source (102) and an electrical load (104) to provide power to the electrical load (pars [36, 40]); and
a second power unit (116, 118, 122) coupled in parallel to the at least one first power unit (see fig.1, par [36]), and coupled between the power source (102) and the electrical load (104), wherein the second power unit comprises:
an energy storage (122);
a first-stage converter (116) coupled between the power source (102) and the energy storage (122);
a second-stage converter (118) coupled between the energy storage (122) and the electrical load (104); and
a processor (processor of 130, pars [22, 90]) coupled to the first-stage converter (see fig.1, see line from 130 to 116) and the second-stage converter (see fig.1, see line from 130 to 118);
wherein when the second power unit is in a standby mode (pars [40-41, 44-45]; i.e., when the load demand is smaller than the power supply and the power supply has a surplus to supply power to the load and charge storage 122, the second power unit including inverter 118 of the second power unit is in “standby mode”/deactivated and not in the inverter mode where the energy storage 122 is discharged through it to the load. Additionally, no power is being supplied to the load from the second power unit when the load demand is smaller than the power supply and the power supply has a surplus to supply power to the load and charge storage 122, which meets the broadest reasonable interpretation of (BRI) of standby mode. Note: it is understood that the second power unit is in standby mode when the inverter is not in power supply inverter mode. See the secondary reference Toyoda below, pars [63, 65] that teaches the inverter is in standby state before being switched to inverter power supply mode), the processor is configured to switch the second power unit to a power supply mode (pars [37-39, 44-45]; the processor activates the inverter 118 so that it is in a “power supply mode”/inverter mode);
wherein when the second power unit is in the power supply mode, the processor is configured to disable the first-stage converter (116), and the energy storage (122) is configured to provide power to the load electrical load by the second-stage converter (118, pars [41, 44-45]; Colombi teaches in par 41 the first stage-converter 116 is “activated” to charge storage 122 and in par 44 in the power supply mode “if there is a power shortfall… and if the energy storage 112 was charged before the shortfall, the charging is suspended”- thus, the processor disables 116 from charging the storage in the inverter mode/power supply mode and discharges the storage to provide power to the load by 118).
Colombi teaches two functionalities in control device 130/ “the processor”: (1) comparing the load demand to a power supply of the grid and detecting a power shortfall (pars [37-39, 44-45]; and (2) the controller activates the inverter in a power supply mode/inverter mode according to the power shortfall detection (pars [37, 44-45]).
Colombi, however, does not teach that first processor functionality (1) sends a “trigger signal” to the second processor functionality (2). Colombi further does not teach the energy storage is a capacitor.
Toyoda, however, teaches it is known to separate the detection and control into two distinct controllers with a trigger signal created by (1) to inform (2) of when it needs to take programmed actions. Toyoda teaches it is known to have a controller (17) that detects a condition and outputs a trigger signal (par [65]; generating a starting command for starting the inverter in the standby state) and for the processor (19) to activate the second power unit/inverter (9) to a power supply mode according to the trigger signal (par [65]; 19 activates inverter 9 according to the trigger signal). Furthermore, Colombi teaches the energy storage is a capacitor (54, par [100]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have made Colombi’s event detection (1) separate from the inverter control (2), as taught by Toyoda. The motivation would have been since it has been held by the courts making an integral structure separable (e.g. in a plurality of pieces), if so is desired, would require only ordinary skill. In re Dulberg, 129 USPQ 348, 349 (CCPA 1961). Modifying Colombi’s energy storage/battery to instead be a capacitor would have been obvious since both a battery and a capacitor are well-known power storage elements that store DC power and one skilled in the art would have selected the capacitor according to their intended use and design.
Examiner Note: the claim does not define the “standby mode”. It is only recited in the context of being switched to a power supply mode. The applicant is encouraged to further define the system and how it operates.
Regarding Claim 2,
The combination teaches the claimed subject matter in claim 1 and further teaches wherein before the processor receives the trigger signal (Colombi, pars [40-41, 53-54, 55-56]; Colombi first teaches that the power demand is low and there is surplus of power to charge the energy storage S10-S16, which is before the processor receives the trigger signal/power shortfall in step S18, S20), the processor is configured to enable the first-stage converter, and charge the energy storage capacitor according to a power provided by the power source (Colombi, pars [39-41, 53-54] and Toyoda, pars [57, 100]).
Regarding Claim 3,
Modified Colombi teaches the claimed subject matter in claim 1 and further teaches the energy storage capacitor provides power to the electrical load by the second-stage converter, and the processor receives a standby signal (Colombi, pars [41, 44-45] and Toyoda, par [100]; standby signal read on by when the power demand of the load becomes smaller than power supply again).
While it is understood in modified Colombi that when the power demand becomes smaller than the power supply, the capacitor would no longer be needed (as the first power unit can provide power to the load on its own) and the capacitor would be controlled to stop discharging, Modified Colombi does not explicitly disclose the processor is configured to control the energy storage capacitor to stop discharging, so that the second power unit resumes the standby mode.
Toyoda, however, teaches when the energy storage capacitor provides power to the load by the second-stage inverter (9, see figs.5 and 7; pars [86, 100]), the processor is configured to control the energy storage capacitor to stop discharging, so that the second power unit resumes the standby mode (fig.2, pars [86-87, 94-96]; upon returning from the inverter power supply mode in which the storage is being discharged to the eco-mode/standby mode, the processor stops the operation of second-stage converter 9 and thereby controls the energy storage to stop discharging so that the standby mode is resumed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Colombi to that of Toyoda. The motivation would have been to fill in the gaps in Colombi and further illustrate that once the load demand becomes small again and discharging the storage is no longer needed, the storage would obviously be stopped and the second power unit would obviously resume standby mode.
Regarding Claim 5,
The combination teaches the claimed subject matter in claim 3 and further teaches wherein after the second power unit resumes the standby mode, the processor is configured to charge the energy storage capacitor according to the power provided by the power source in a subsequent plurality of power periods (Colombi, pars [41-42, 54] and Toyoda, pars [87-88, 96, 98, 100, 123] and related discussion;
The combination teaches charging the energy storage capacitor as modified by Toyoda in a plurality of power periods that happen over the lifetime of the system after the second-stage converter/inverter of the second power unit resumes the standby mode. Every period the capacitor is charged after the standby mode resumes over the lifetime of the system reads on “subsequent plurality of power periods”).
Regarding Claim 7,
The combination teaches the claimed subject matter in claim 1 and further teaches wherein when the second power unit is in the standby mode, the energy storage capacitor stops discharging, and the second power unit does not provide power to the load (Colombi, pars [40-41, 44-45] and Toyoda, pars [57, 96, 100]; in the combination when the second power unit is in the standby mode/inverter 118 is deactivated, and the storage capacitor stops discharging, and the second power unit does not provide power to the load, because the first power supply is providing power to the load and power surplus is used to charge the capacitor) or a power supply of the second power unit is less than a preset value (limitation is written in the alternative).
Regarding Claim 11,
Colombi teaches a control method applied to a power supply system, wherein the power supply system comprises at least one first power unit (items 126, 128; the recitation of “power unit” is nominal and structurally not limiting. 126 and 128 read on the broadest reasonable interpretation of “first power unit” as they provide power to the load) and a second power unit (116, 118, 122), and the at least one first power unit is configured to provide power to an electrical load (104) according to a power provided by a power source (102), the control method comprises:
detecting a load status of the power supply system (pars [37-39]; power demand of the load is compared to power supply of the grid to detect the load status);
when the load status is determined to be a peak load (pars [37-39, 44-45]; peak load read on by the load demand being greater than the power supply/power shortfall), disabling a first-stage converter (116) in the second power unit (pars [41, 44-45]; Colombi teaches in par 41 the first stage-converter 116 is “activated” to charge storage 122 and in par 44 in response to the peak load to place the second power unit in the power supply inverter mode “if there is a power shortfall… and if the energy storage 112 was charged before the shortfall, the charging is suspended”- thus, the Colombi disables 116 from charging the storage in the inverter mode/power supply mode), and controlling an energy storage (122) in the second power unit to provide power to the electrical load (pars [41, 44-45]; activating the inverter 118 and discharging the storage 122 to provide power to the load), wherein the energy storage (122) is coupled between the first-stage inverter (116) and a second-stage converter (118) in the second power unit (see fig.1).
Colombi teaches two functionalities in control device 130/ “the processor”: (1) comparing the load demand to a power supply of the grid and detecting a power shortfall (pars [37-39, 44-45]; and (2) the controller activates the inverter in a power supply mode/inverter mode (pars [44-45]) and disables the first-stage converter (pars [37, 41, 44-45]; charging of the storage is suspended by deactivating the first stage converter 116).
Colombi, however, does not teach that first processor functionality (1) generating a “trigger signal” to the second processor functionality (2). Colombi further does not teach the energy storage is a capacitor.
Toyoda, however, teaches it is known to separate the detection and control into two distinct controllers with a trigger signal generated by (1) to inform (2) of when it needs to take programmed actions. Toyoda teaches it is known to have a controller (17) that detects a condition and outputs a trigger signal (par [65]; generating a starting command for starting the inverter) and for the processor (19), in response to the trigger signal to take actions (par [65]; 19 activates inverter 9 in response to the trigger signal and rectifier 5 is disabled in the combination). Furthermore, Colombi teaches the energy storage is a capacitor (54, par [100]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have made Colombi’s event detection (1) separate from the inverter and rectifier control (2), as taught by Toyoda. The motivation would have been since it has been held by the courts making an integral structure separable (e.g. in a plurality of pieces), if so is desired, would require only ordinary skill. In re Dulberg, 129 USPQ 348, 349 (CCPA 1961). Modifying Colombi’s energy storage/battery to instead be a capacitor would have been obvious since both a battery and a capacitor are well-known power storage elements that store DC power and one skilled in the art would have selected the capacitor according to their intended use and design.
Regarding Claim 12,
The combination teaches the claimed subject matter in claim 11 and further teaches when the load status is not determined to be the peak load (Colombi, pars [40-41, 53-54, 55-56]; Colombi teaches that the power demand is low and there is surplus of power to charge the energy storage which reads on “not determined to be the peak load”), enabling the first-stage converter, and charging to the energy storage capacitor according to the power provided by the power source (Colombi, pars [39-41, 53-54] and Toyoda, pars [57, 100]; Colombi teaches enabling the first-stage converter 116 to charge the energy storage).
Regarding Claim 13,
Modified Colombi teaches the claimed subject matter in claim 11 and further teaches the energy storage capacitor provides power to the electrical load, and the second power unit receives a standby signal (Colombi, pars [41, 44-45] and Toyoda, par [100]; standby signal read on by when the power demand of the load becomes smaller than power supply again and the processor of the second power unit receives the indication).
While it is understood in modified Colombi that when the power demand becomes smaller than the power supply, the capacitor would no longer be needed (as the first power unit can provide power to the load on its own) and the capacitor would be controlled to stop discharging, so that the second power unit is switched from a power supply mode to a standby mode, modified Colombi does not explicitly disclose controlling the energy storage capacitor to stop discharging, so that the second power unit is switched from a power supply mode to a standby mode.
Toyoda, however, teaches when the energy storage capacitor provides power to the load by the second-stage inverter in a power supply inverter mode (9, see figs.5 and 7; pars [86, 100]), controlling the energy storage capacitor to stop discharging, so that the second power unit is switched from the power supply mode to a standby mode (figs.2, 5, 7, pars [86-87, 94-96, 100]; switching from the inverter power supply mode to a standby mode/eco-mode in which discharging the storage/capacitor is stopped by stopping the operation of the of the second-stage converter 9 of the second power unit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Colombi to that of Toyoda. The motivation would have been to fill in the gaps in Colombi and further illustrate that once the load demand becomes small again and discharging the storage is no longer needed, the storage would obviously be stopped and the second power unit would be switched from a power supply mode to a standby mode.
Regarding Claim 15,
The combination teaches the claimed subject matter in claim 13 and further teaches wherein after the second power unit is switched from the power supply mode to the standby mode, in a subsequent plurality of power periods, charging the energy storage capacitor according to the power provided by the power source (Colombi, pars [41-42, 54] and Toyoda, pars [57, 87-88, 96, 98, 100, 123] and related discussion; The combination teaches charging the energy storage capacitor as modified by Toyoda in a plurality of subsequent power periods that happen over the lifetime of the system after the second-stage converter/inverter of the second power unit returns to the standby mode/eco-mode in Toyoda. Every period the capacitor is charged after the standby mode resumes over the lifetime of the system reads on “subsequent plurality of power periods”).
Regarding Claim 17,
Claim 17 recites the same limitations as discussed above in the rejection of claim 7 and is therefore rejected in the same fashion.
Claim(s) 4, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Colombi et al. (2022/0224149 A1) in view of Toyoda (2017/0163088 A1) in further view of Cohen et al. (2010/0045107 A1).
Regarding Claim 4,
The combination teaches the claimed subject matter in claim 3 and further teaches wherein after the second power unit resumes the standby mode, the processor is configured to enable the first-stage converter to change to charge the energy storage capacitor according to the power provided by the power source (Colombi, pars [pars [40-41] and Toyoda, pars [88, 95-96, 98, 100]; Colombi teaches the processor enables the first stage converter to charge the storage in the standby mode and Toyoda teaches upon returning/resuming the standby mode, the first stage converter 5 is enabled to charge the capacitor).
The combination does not explicitly disclose a reset time.
Cohen, however, teaches a reset time (pars [16-17]; timer delay) and connecting conversion circuitry of a UPS to an AC power line after the reset time (pars [16-17]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Colombi in view of Toyoda’s enabling of the first stage converter to be after a reset time. The motivation would have been to avoid inrush current (component protection), to avoid uncontrolled charging current to the capacitor and to ensure system stability before enabling the first-stage converter.
Examiner Note: Yashiro (2011/0064445 A1), figs.3, 5-6, par [72] also teaches after a reset time S13 is yes, first stage converter/AC-DC rectifier is enabled to charge the capacitor (S18, S19).
Regarding Claim 14,
The combination teaches the claimed subject matter in claim 13 and further teaches when the second power unit is switched from the power supply mode to the standby mode (Colombi, pars [pars [40-41, 44-45] and Toyoda, pars [88, 95-96, 98, 100]; The combination teaches returning to the standby mode from an inverter power supply mode), enabling the first-stage converter to change to charge the energy storage capacitor according to the power provided by the power source (Colombi, pars [pars [40-41] and Toyoda, pars [88, 95-96, 98, 100]; Colombi teaches the processor enables the first stage converter to charge the storage in the standby mode and Toyoda teaches upon returning/resuming the standby mode, the first stage converter 5 is enabled to charge the capacitor).
The combination does not explicitly disclose a reset time.
Cohen, however, teaches a reset time (pars [16-17]; timer delay) and connecting conversion circuitry of a UPS to an AC power line after the reset time (pars [16-17]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Colombi in view of Toyoda’s enabling of the first stage converter to be after a reset time. The motivation would have been to avoid inrush current (component protection), to avoid uncontrolled charging current to the capacitor and to ensure system stability before enabling the first-stage converter.
Examiner Note: Yashiro (2011/0064445 A1), figs.3, 5-6, par [72] also teaches after a reset time S13 is yes, first stage converter/AC-DC rectifier is enabled to charge the capacitor (S18, S19)
Claim(s) 6, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Colombi et al. (2022/0224149 A1) in view of Toyoda (2017/0163088 A1) in further view of Matsumura et al. (2010/0219769 A1).
Regarding Claim 6,
The combination teaches the claimed subject matter in claim 5 and teaches wherein the second power unit charges the energy storage capacitor (see rejection of claim 5).
The combination does not explicitly disclose uses a set current value to charge the energy storage capacitor.
Matsumura, however, teaches it is known in the art to use a set current value to charge the energy storage capacitor (par [12]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of references to that of Matsumura of setting a current value to charge the capacitor. The motivation would have bene to control how fast the capacitor charges and to keep the circuit safe and predictable.
Regarding Claim 16,
The combination teaches the claimed subject matter in claim 15 and teaches in the subsequent plurality of power periods, to charge the energy storage capacitor (see rejection of claim 15).
The combination does not explicitly disclose using a set current value to charge the energy storage capacitor.
Matsumura, however, teaches it is known in the art to use a set current value to charge the energy storage capacitor (par [12]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of references to that of Matsumura of setting a current value to charge the capacitor. The motivation would have bene to control how fast the capacitor charges and to keep the circuit safe and predictable.
Claim(s) 8, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Colombi et al. (2022/0224149 A1) in view of Toyoda (2017/0163088 A1) in further view of Muccini et al. (2021/0089106 A1).
Regarding Claim 8,
The combination teaches the claimed subject matter in claim 1 and the combination further teaches wherein the second power unit further comprises: a detection circuit (Colombi, 132, par [37]) coupled to the processor (Colombi, see fig.1), configured to detect a power quality, load demand of the power supply system (Colombi, pars [37, 41, 44-45]).
The combination does not explicitly disclose the detection circuit configured to detect a slew rate of the at least one first power unit, and determine whether the slew rate is greater than a peak threshold.
Muccini, however, teaches it is known in the art for the detection circuit to detect a slew rate of a power unit (pars [21, 24-25] and related discussion), and determine whether the slew rate is greater than a peak threshold (pars [21, 24-25, 28]; determine whether the slew rate exceeds a peak threshold read on by the slew rate threshold).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of modified Colombi to that of Muccini so that the slew rate of modified Colombi’s first power unit is detected and whether the slew rate is greater than a peak threshold is determined. The motivation would have been to have a more robust system that is capable of monitoring a critical parameter in the slew rate when monitoring the power quality of the power supply to the load and the load demand of the power supply system. The more parameters that are detected that are related to the power quality of the power supplied to the load, the more accurate the system is.
Regarding Claim 18,
The combination teaches the claimed subject matter in claim 11 and further teaches detecting, by a detection circuit (Colombi, 132, par [37), the power quality of the power supply to the load and the load status of the power supply system (Colombi, par [37] and rejection of claim 11); and when the load status is a peak load, generating the trigger signal (combination of Colombi in view of Toyoda, see rejection of claim 11).
The combination does not explicitly disclose detecting a slew rate of the at least one first power unit, and when the slew rate is greater than a peak threshold, generating a signal.
Muccini, however, teaches it is known in the art to detect a slew rate of a power unit (pars [21, 24-25] and related discussion), and when the slew rate is greater than a peak threshold, generating a signal (pars [21, 24-25, 28]; determine whether the slew rate exceeds a peak threshold read on by the slew rate threshold and generating an indication signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of modified Colombi to that of Muccini so that the slew rate of modified Colombi’s first power unit is detected and when the slew rate is greater than a peak threshold is determined, to generate the trigger signal. The motivation would have been to have a more robust system that is capable of monitoring a critical parameter in the slew rate when determining the status of the load and the power quality of the power supply to the load when generating the trigger signal in modified Colombi. The more parameters that are detected that are related to the power quality of the power supplied to the load, the more accurate the system is.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RASEM MOURAD whose telephone number is (571)270-7770. The examiner can normally be reached M-F 9:00-6.
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/RASEM MOURAD/Examiner, Art Unit 2836
/REXFORD N BARNIE/Supervisory Patent Examiner, Art Unit 2836