DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' application filed on 07/12/24. Claims 1-17 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-8, 11-17 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawagoe (US 20120105029 A1)
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Regarding claim 1. Kawa teaches a control circuit for a power converter [fig 1], wherein the control circuit comprises: a loop compensation unit [feedback circuit] for obtaining a compensation amount for a switching control signal [i.e. for high/low switches] according to a voltage feedback signal of an output voltage [i.e. FB];
a switching cycle calculation unit [14, difference calculated by 14] for allocating the compensation amount as a switching cycle compensation amount according to a first preset weight [output preset value greater than 1];
an on-time calculation unit [13, implicit on time control for output of 13 setting to drive main switches] for allocating the compensation amount as an on-time compensation amount according to a second preset weight [i.e. 2nd preset value greater than 1 applied to controller];
and a hybrid modulator [A replicated above] for generating the switching control signal according to the switching cycle compensation amount and the on-time compensation amount [output of A is based on 13 and 14].
Regarding claim 2. Kawa teaches the control circuit according to claim 1, wherein, in continuous switching cycles, the control circuit synchronously and dynamically adjusts a switching cycle and an on-time of the switching control signal as a load state changes [¶8].
Regarding claim 3. Kawa teaches the control circuit according to claim 1, wherein at least one of the first preset weight and the second preset weight is greater than zero [output is 13 and 14 is inherently greater than 0 volt], according to values of the first preset weight and the second preset weight, a modulation mode of the control circuit is one of PWM mode, PFM mode and hybrid modulation mode [as shown in 13/14].
Regarding claim 4. Kawa teaches the control circuit according to claim 1, wherein a sum of the first preset weight and the second preset weight is equal to or greater than 1 [output is 13 and 14 is inherently greater than 1 volt], so that a compensation mode [i.e. compensation modes to compensate light or heavy loads] of the control circuit is one of accurate compensation mode and over compensation mode.
Regarding claim 7. Kawa teaches the control circuit according to claim 1, wherein the hybrid modulator performs a numerical calculation [i.e. calculation set by latch circuit giving by equation Qnext = S+R*Q, S = latch sets, R = latch resets and Q = output] based on the switching cycle compensation amount and the on-time compensation amount, and performs a digital-to-analog conversion [driver outputs analogue signal] to generate the switching control signal.
Regarding claim 8. Kawa teaches the control circuit according to claim 1, wherein the hybrid modulator comprises an RS flip-flop, and the hybrid modulator generates a reset signal [i.e. signal applied to R input] based on the switching cycle compensation amount [FB indirectly drives all components of controller and is based on switching cycle], generates a set signal based on the on-time compensation amount [i.e. same rational can be applied as above], and the RS flip-flop generates the switching control signal based on the reset signal and the 9 set signal.
Regarding claim 11. Kawa teaches a power converter, comprising: an input terminal [vin] and an output terminal for receiving an input voltage and providing an output voltage [vout], respectively;
an inductor and a transistor [LX, high/low switches] coupled between the input terminal and the output terminal;
and the control circuit according to claim 1, wherein the control circuit is configured to generate a switching control signal [output of driver] of the transistor, charge the inductor with the input voltage when the transistor is in on state, and discharge the inductor when the transistor is in off state, so as to generate the output voltage on the output terminal [function of buck converter of fig 1].
Regarding method claims 12-17, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device "inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 rejected under 35 U.S.C. 103 as being unpatentable over Kawa in view of Guam (US 20180131275 A1)
Regarding claim 10. Kawa teaches the control circuit according to claim 1, wherein the loop compensation unit comprises: an error amplifier [12] for converting an error signal between the voltage feedback signal and a reference voltage into a differential current.
However, Kawa does not explicitly mention a circuit comprising: a capacitor connected to an output terminal of the error amplifier, wherein the capacitor is charged with the differential current to obtain the compensation amount for the switching control signal.
Guan teaches a circuit comprising: a capacitor [C3, fig 1] connected to an output terminal of the error amplifier [i.e. 7], wherein the capacitor is charged with the differential current to obtain the compensation amount for the switching control signal.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Guan in order to provide the error signal more stable and less jitter signal adjustment.
Allowable Subject Matter
Claims 5-6 and 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838