DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/09/2016 has been entered.
Response to Amendment
The office action is responding to the amendments filed on 01/09/2026. Claims 1, 12 and 21 have been amended. Claims 11 and 22-23 were previously cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 12 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. [US 2022/0206938 A1] in view of XIE et al. [US 2022/0405001 A1].
Claim 1, is rejected over Shin and XIE.
Shin teaches “A storage device comprising: a non-volatile memory device including a plurality of memory blocks; and” as “According to an aspect of the inventive concept, there is provided an operating method of a memory controller configured to control a memory device including memory blocks” [¶0008]
“a memory controller configured to control a garbage collection operation of copying valid data of a source block among the plurality of memory blocks to a destination block,” as “Embodiments of the inventive concept provide an operating method of a memory controller which efficiently performs garbage collection ” [¶0007]
“determine a validity of user data stored in the page included in the source block based on the logical address that is stored in the page,” as “According to an embodiment, as DATA is written in a storage area, the validity of a page included in each of the plurality of memory blocks 210 of the memory device 200 may vary before DATA is written therein.” [¶0096] (The validity of the page is checked within the page)
“read the valid data, which includes the user data determined to be valid, from the non-volatile memory device, and perform a write operation on the destination block by transferring the read valid data to the non-volatile memory device.” as “In operation S150, the memory controller 100 may perform garbage collection GC on the basis of the fragmentation ratio FR. According to an embodiment, the memory controller 100 may select a source block BLK_S sequentially from a memory block having a low fragmentation ratio FR, and thus, sequential read may be ensured, whereby the I/O efficiency of the storage device 10 including the memory controller 100 may be enhanced.” [¶0111]
Shin does not explicitly teach wherein the memory controller is configured to, read, from the non-volatile memory device, a logical address stored in a page included in the source block,
However, XIE teaches “wherein the memory controller is configured to, read, from the non-volatile memory device, a logical address stored in a page included in the source block,” as “The data storage device 206 includes a partial mapping table (PMT) 208, a NAND 216, which may be the NVM 110 of FIG. 1, and a flash translation layer (FTL) mapping table (FTLMT) 220.” [¶0035] (The mapping table and the FTL are located inside the NAND storage. A NAND storage is non-volatile memory.)
Shin and XIE are analogous arts because they teach storage system and memory control methods.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shin and XIE before him/her, to modify the teachings of Shin to include the teachings of XIE with the motivation of only part of the data storage device capacity requires garbage collection, such as in hybrid SSDs, where the NAND or part of the NAND is used as a cache before data is routed to the main memory device to be stored. [XIE, ¶0061]
Claim 2, is rejected over Shin and XIE.
Shin teaches “wherein the memory controller is configured to map information between a physical address and the logical address, the physical address indicating a location at which the user data is stored in the non-volatile memory device,” as “The metadata may include mapping table information which is used to translate a logical address to a physical page address of each of flash memories 310 to 330, and moreover, may include pieces of information for managing a storage area of the memory device (200 of FIG. 1).” [¶0064]
“identify validity of the physical address corresponding to the logical address based on the mapping information, and” as “the control logic 230 may provide the flash translation layer 300 with valid page information VI which is information about the validity of pages included in the plurality of memory blocks 210.” [¶0096]
“determine the user data corresponding to a valid physical address to be the valid data.” as “control data (e.g., a command) from the UFS host 2100 to the UFS device 2200 and user data to be stored in or read from the NVM 2220 of the UFS device 2200 by the UFS host 2100 may be transmitted through the same lane. ” [¶00233]
Claim 3, is rejected over Shin and XIE.
Shin teaches “wherein the non-volatile memory device further comprises a data buffer configured to output the user data sensed by the plurality of memory blocks,” as “Referring to FIG. 4 with reference to FIG. 2, the memory device 200 may include a control logic 230, a memory cell array 220, a page buffer 240” [¶0080]
“wherein the memory controller is configured to transfer the user data stored in the page and the logical address corresponding to the user data from the page of the source block to the data buffer, and read the logical address among the user data and the logical address transferred to the data buffer.” as “ DATA may be buffered in the page buffer 240 and then may be sequentially stored in a certain storage area (for example, a page) among a plurality of memory blocks 210 in response to a signal of the column address Y-ADDR output from the control logic 230.” [¶0095]
Claim 4, is rejected over Shin and XIE.
Shin teaches “wherein the memory controller is configured to determine whether a valid data count indicating an amount of entire valid data stored in the source block is equal to or greater than a threshold, and” as “Garbage collection based on a valid page count VPC may be used, but may not be an optimal method of selecting the source block BLK_S 211.” [¶0104]
“control the garbage collection operation different according to whether the valid data count is equal to or greater than the threshold.” as “ According to an embodiment, the GC manager 350 may be provided with the fragmentation ratio FR based on the page validity information VI which is validity information about a page corresponding to a storage area storing DATA, select a block having a lowest fragmentation ratio FR as the source block BLK_S 211, and perform garbage collection GC in ascending order of fragmentation ratios FR.” [¶0104]
Claim 12, is rejected over Shin and XIE.
Shin teaches “A storage device comprising: a non-volatile memory device including a plurality of memory blocks; and” as “According to an aspect of the inventive concept, there is provided an operating method of a memory controller configured to control a memory device including memory blocks” [¶0008]
“a memory controller configured to control a garbage collection operation of copying valid data of a source block among the plurality of memory blocks to a destination block,” as “Embodiments of the inventive concept provide an operating method of a memory controller which efficiently performs garbage collection ” [¶0007]
“wherein the memory controller is configured to determine whether a detection condition for performing a garbage collection operation on the source block is satisfied,” as “the FR calculator 330 may detect sequential bits of one memory block in a valid page bitmap, group the sequential bits, and calculate the number of groups having the same validity condition, thereby calculating a fragmentation degree FD (as illustrated in FIG. 14). ” [¶0101]
“in response to the detection condition being satisfied, perform the garbage collection operation according to a first process,” as “The FR calculator 330 may provide the GC manager 350 with the fragmentation ratio FR or the fragmentation ratio FR and a fragmentation degree FD.” [¶0101]
“in response to the detection condition not being satisfied, perform the garbage collection operation according to a second process,” as “In the flash translation layer 300, mapping for allocating a logical address LBA, generated by a file system, as a physical address PBA of the memory device 200 may be performed. The flash translation layer 300 may count a write count per block of the memory device 200 and may perform wear leveling for performing distribution so that a write degree between a plurality of blocks is uniform. Also, the flash translation layer 300 may perform garbage collection of realigning data so as to solve an increase in an invalid area (i.e., garbage) caused by the writing or deleting of data which is repeated in a storage area.” [¶0089]
Shin does not explicitly teach in which a logical address stored in a page included in the source block is read from the non-volatile memory device,
in which the logical address and user data stored in the page included in the source block are read from the non-volatile memory device.
However, XIE teaches “in which a logical address stored in a page included in the source block is read from the non-volatile memory device,” as “The data storage device 206 includes a partial mapping table (PMT) 208, a NAND 216, which may be the NVM 110 of FIG. 1, and a flash translation layer (FTL) mapping table (FTLMT) 220.” [¶0035] (The mapping table and the FTL are located inside the NAND storage. A NAND storage is non-volatile memory.)
“in which the logical address and user data stored in the page included in the source block are read from the non-volatile memory device.” as “The data storage device 206 includes a partial mapping table (PMT) 208, a NAND 216, which may be the NVM 110 of FIG. 1, and a flash translation layer (FTL) mapping table (FTLMT) 220.” [¶0035] (The mapping table and the FTL are located inside the NAND storage. A NAND storage is non-volatile memory.)
Shin and XIE are analogous arts because they teach storage system and memory control methods.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shin and XIE before him/her, to modify the teachings of Shin to include the teachings of XIE with the motivation of only part of the data storage device capacity requires garbage collection, such as in hybrid SSDs, where the NAND or part of the NAND is used as a cache before data is routed to the main memory device to be stored. [XIE, ¶0061]
Claim 21 is rejected over Shin and XIE under the same rationale of rejection of claim 1.
Claim(s) 5-6 and 13-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. [US 2022/0206938 A1] in view of XIE et al. [US 2022/0405001 A1] and in further view of BYUN [US 2020/0065259 A1].
Claim 5 is rejected over Shin, XIE and BYUN.
The combination of Shin and XIE does not explicitly teach wherein in response to the valid data count of the source block being less than the threshold with respect to each of a plurality of pages comprised in the source block, the memory controller is configured to, read the logical address, and after identifying the valid data by using the logical address, reading the valid data from the non-volatile memory device and writing the read valid data to the destination block perform the garbage collection operation.
However, BYUN teaches “wherein in response to the valid data count of the source block being less than the threshold with respect to each of a plurality of pages comprised in the source block, the memory controller is configured to, read the logical address, and after identifying the valid data by using the logical address, reading the valid data from the non-volatile memory device and writing the read valid data to the destination block perform the garbage collection operation.” as “Meanwhile, when it turns out in the step S1001 that the valid page count VPC included in the first memory block is less than or equal to the threshold value (“YES”), the controller 130 may decide in step S1005 that the first memory block is a memory block where a garbage collection operation is to be shortly performed and list the first memory block in the candidate block list CBL.” [¶0142]
Shin, XIE and BYUN are analogous arts because they teach data processing system with storage device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shin, XIE and BYUN before him/her, to modify the teachings of combination of Shin and XIE to include the teachings of BYUN with the motivation of operating the data processing system exhibiting reduced complexity and performance deterioration, and increased utility efficiency of a memory device of the data processing system. [BYUN, ¶0005]
Claim 6 is rejected over Shin, XIE and BYUN.
Shin teaches “after reading the logical address and the user data, the memory controller is configured to identify the valid data among the read user data, and by writing the identified valid data among the read user data to the destination block performs the garbage collection operation.” as “According to an embodiment, the GC manager 350 may be provided with the fragmentation ratio FR based on the page validity information VI which is validity information about a page corresponding to a storage area storing DATA, select a block having a lowest fragmentation ratio FR as the source block BLK_S 211, and perform garbage collection GC in ascending order of fragmentation ratios FR.” [¶0104]
The combination of Shin and XIE does not explicitly teach in response to the valid data count stored in the source block being equal to or greater than the threshold, with respect to each of a plurality of pages comprised in the source block,
However, BYUN teaches “in response to the valid data count stored in the source block being equal to or greater than the threshold, with respect to each of a plurality of pages comprised in the source block,” as “it is decided whether the read count RC of the first memory block is equal to or greater than the threshold value.” [¶0143]
Shin, XIE and BYUN are analogous arts because they teach data processing system with storage device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shin, XIE and BYUN before him/her, to modify the teachings of combination of Shin and XIE to include the teachings of BYUN with the motivation of operating the data processing system exhibiting reduced complexity and performance deterioration, and increased utility efficiency of a memory device of the data processing system. [BYUN, ¶0005]
Claim 13 is rejected over Shin, XIE and BYUN under the same rationale of rejection of claim 5.
Claim 14 is rejected over Shin, XIE and BYUN under the same rationale of rejection of claim 5.
Claim 15 is rejected over Shin, XIE and BYUN.
The combination of Shin and XIE does not explicitly teach wherein the detection condition is based on whether a valid data count indicating an amount of entire valid data stored in the source block is less than a threshold, and in response to the valid data count being less than the threshold, the memory controller is configured to determine that the detection condition is satisfied.
However, BYUN teaches “wherein the detection condition is based on whether a valid data count indicating an amount of entire valid data stored in the source block is less than a threshold, and in response to the valid data count being less than the threshold, the memory controller is configured to determine that the detection condition is satisfied.” as “Meanwhile, when it turns out in the step S1001 that the valid page count VPC included in the first memory block is less than or equal to the threshold value (“YES”), the controller 130 may decide in step S1005 that the first memory block is a memory block where a garbage collection operation is to be shortly performed and list the first memory block in the candidate block list CBL.” [¶0142]
Shin, XIE and BYUN are analogous arts because they teach data processing system with storage device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shin, XIE and BYUN before him/her, to modify the teachings of combination of Shin and XIE to include the teachings of BYUN with the motivation of operating the data processing system exhibiting reduced complexity and performance deterioration, and increased utility efficiency of a memory device of the data processing system. [BYUN, ¶0005]
Claim 16 is rejected over Shin, XIE and BYUN.
The combination of Shin and XIE does not explicitly teach in response to the valid data count being less than the threshold, the memory controller is configured to perform the garbage collection operation on each of a plurality of pages comprised in the source block according to the first process, and
in response to the valid data count being equal to or greater than the threshold, the memory controller is configured to perform the garbage collection operation on each of a plurality of pages comprised in the source block according to the second process.
However, BYUN teaches “in response to the valid data count being less than the threshold, the memory controller is configured to perform the garbage collection operation on each of a plurality of pages comprised in the source block according to the first process, and” as “Meanwhile, when it turns out in the step S1001 that the valid page count VPC included in the first memory block is less than or equal to the threshold value (“YES”), the controller 130 may decide in step S1005 that the first memory block is a memory block where a garbage collection operation is to be shortly performed and list the first memory block in the candidate block list CBL.” [¶0142]
“in response to the valid data count being equal to or greater than the threshold, the memory controller is configured to perform the garbage collection operation on each of a plurality of pages comprised in the source block according to the second process.” as “it is decided whether the read count RC of the first memory block is equal to or greater than the threshold value.” [0143]
Allowable Subject Matter
Claims 7 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8-10 and 18-20 are also objected as their parent claims 7 and 17 respectively are considered to contain allowable subject matter.
Response to Arguments
Applicant’s arguments with respect to amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132