DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-12 in the reply filed on 1/23/2026 is acknowledged. Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant did not provide any grounds for the traversal; therefore the requirement is still deemed proper and is made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 5, 6, 7, 8, 11, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Upputuri et al (US Pat. 12,025,661; hereinafter referred to as Upputuri) in view of Kwon et al (US Pat. Pub. 2011/0320896; hereinafter referred to as Kwon).
As per claim 1: Upputuri teaches an integrated circuit comprising:
a functional data path (col. 7, lines 8-10); and
a scan-data path, at least a portion of which is separate from the functional data path (Fig. 1, scan channels 501-520);
wherein the portion of the scan-data path which is separate from the functional data path comprises a combined gating/delay element (Fig. 1, 105) for preventing a scan-data signal from reaching any elements downstream of the combined gating/delay element during a scan mode (col. 5, lines 45-53).
Not explicitly disclosed is the gating/delay element providing some or all of a desired signal delay in the portion of the scan-data path which is separate from the functional data path. However, Kwon in an analogous art teaches a scan path (Fig. 5, 540) comprising a gating/delay element (Fig. 5, 542) for providing signal delay in the scan-data path (Fig. 5, 543; paragraph 33).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the scan path of Kwon in the circuit of Upputuri. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have provided a known means for lowering power consumption in the scan path (paragraph 31).
As per claim 7: Upputuri teaches a method comprising:
inserting a combined gating / delay element (Fig. 1, 105) into a portion of a scan-data path of an integrated circuit that is separate from a functional data path of the integrated circuit (Fig. 1, scan channels 501-520);
wherein the combined gating / delay element prevents a scan-data signal from reaching any elements downstream of the combined gating / delay element during a scan mode (col. 5, lines 45-53).
Not explicitly disclosed is the gating/delay element providing some or all of a desired signal delay in the portion of the scan-data path which is separate from the functional data path. However, Kwon in an analogous art teaches a scan path (Fig. 5, 540) comprising a gating/delay element (Fig. 5, 542) for providing signal delay in the scan-data path (Fig. 5, 543; paragraph 33).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the scan path of Kwon in the circuit of Upputuri. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have provided a known means for lowering power consumption in the scan path (paragraph 31).
As per claims 2, 8: Upputuri further teaches the integrated circuit of claim 1 and method of claim 7, wherein the combined gating / delay element comprises an AND gate, a NAND gate, or a NOR gate (col. 5, lines 45-49; Fig. 1, 105).
As per claims 5, 11:
Kwon further teaches the integrated circuit of claim 1 and method of claim 7, wherein the scan-data path further comprises one or more delay elements downstream of the combined gating / delay element (Fig. 5, 543); and wherein the combined gating / delay element and the one or more delay elements downstream of the combined gating / delay element together provide all of the desired signal delay in the portion of the scan-data path which is separate from the functional data path (See Fig. 5, 543 providesd necessary delay for the scan path 540 which is separate from data path D).
As per claims 6, 12:
Kwon further teaches the integrated circuit of claim 5 and method of claim 7, wherein the one or more delay elements downstream of the combined gating / delay element comprise one or more buffers (Fig. 5, 562) and/or one or more inverters (Fig. 5, 561).
Claim(s) 3, 4, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Upputuri in view of Kwon in view of Datta et al (US Pat. Pub. 2016/0124043; hereinafter referred to as Datta).
As per claims 3, 9: Upputuri et al teach the integrated circuit of claim 2 and method of claim 8 above. Not explicitly disclosed is wherein the combined gating / delay element comprises a NAND gate comprising a first and second transistors in series, the second transistor being closer to a ground connection than is the first transistor; and wherein a scan-enable source of the integrated circuit is connected to an input of the NAND gate leading to the first transistor. However, Datta in an analogous art teaches a NAND gate (Fig. 9, 810) comprising a first and second transistors in series (Fig. 9, 925 and 930), the second transistor being closer to a ground connection than is the first transistor (Fig. 9, 930); and wherein a scan-enable source of the integrated circuit is connected to an input of the NAND gate leading to the first transistor (Fig. 9, 925).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the NAND gate of Datta in the circuit of Upputuri. This modification would have been obvious for one of ordinary skill in the art at the time of filing because any suitable logic gate could have been used to perform the functionality required by Upputuri while providing expected results.
As per claims 4, 10: Upputuri et al teach the integrated circuit of claim 2 and method of claim 8 above. Not explicitly disclosed is wherein the combined gating / delay element comprises a NOR gate comprising a first and second transistors in series, the first transistor being closer to a source voltage connection than is the second transistor; and wherein a scan-enable source of the integrated circuit is connected to an input of the NOR gate leading to the second transistor. However, Datta in an analogous art teaches a NOR gate (Fig. 11, 1010) comprising a first and second transistors in series (Fig. 11, 1110 and 1115), the first transistor being closer to a source voltage connection than is the second transistor (Fig. 11, 1110 is closer to Vdd); and wherein a scan-enable source of the integrated circuit is connected to an input of the NOR gate leading to the second transistor (Fig. 11, 1120).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the NOR gate of Datta in the circuit of Upputuri. This modification would have been obvious for one of ordinary skill in the art at the time of filing because any suitable logic gate could have been used to perform the functionality required by Upputuri while providing expected results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art are generally directed to power saving features for scan chain circuits.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111