DETAILED ACTION
This office action is in response to a Request for Continued Examination (RCE) filed 6/17/2026 for application 18/770,982 filed 7/12/2024 that claims priority to provisional 63/526,517 filed 7/13/2023.
Claims 1, 13, and 20 were amended. Claims 23-30 are new. Claims 2-4, 9-11, 14-16, 19, and 21-22 are cancelled. Thus claims 1, 5-8, 12-13, 17-19, and 20-30 have been examined.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-8, 12-13, 18, 20, 24-25, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Ramalingam (RAMALINGAM US 2016/0283116 A1) in view of Subraya (Subraya US 2020/0042236 A1).
Regarding claim 1, Ramalingam teaches A system comprising: (Ramalingam Fig. 1 and
para [0008] discloses the solution is directed to a computing system)
a plurality of submission queues configured to receive command requests from a host system; (Ramalingam [0002] discloses each processing node (host) has one or more submission queues to receive command requests from the processor nodes. Ramalingam Fig. 1 and para [0026] discloses the Computing System 100 may be a personal computer, a mainframe, a telephony device, a smart phone, etc. thus Computing System 100 may represent a host device.) a command queue configured to store command requests awaiting execution on the system; (Ramalingam [0003] discloses the share storage has a controller that receives the storage commands and stores the storage commands in a in a common pending storage command queue to await execution by the shared storage.)
a memory device; (Ramalingam Fig. 1 and para [0024] discloses Nonvolatile Storage 120 that is an example of a memory device.)
and a processing device, operatively coupled to the memory device, configured to perform operations comprising: (Ramalingam [0024] discloses Block Storage Controller 110 with Solid State Drive 106, that is an example of a processing device coupled to the memory device. See also Ramalingam [0090]-]0093] that discloses the controller is configure to perform the operations.)
retrieving, from a submission queue of the plurality of submission queues, a command request, the submission queue being associated with a queue identifier; (Ramalingam Fig. 2 and para [0027] discloses that the Block Storage Controller 110 receives command requests from the submission queues at the nodes and places them in a common transmission (i.e. submission) queue depicted in Fig. 2 of Ramalingam that shows each command request in the common submission queues is associated with a queued identifier (i.e. the Queue Entry Field 714b that identifies the submission queue id for the request).)
storing an entry for the command request in the command queue, the entry comprising a command queue sequence identifier, the queue identifier associated with the submission queue from which the command request is retrieved, a namespace identifier associated with the command request, and a memory address of the command request, the memory address corresponding to a memory location on the memory device; (Ramalingam Fig. 2 and paras [0027]-[0028] and [0056] that shows the entries in the Block Storage Controller queue contain a submission queue id associated with the submission queue from which the command was retrieved and a logical block address for the command)
determining, in the command queue, a plurality of command requests of a common command type to be executed with respect to a sequence of memory addresses, (Ramalingam Figs. 7 and 8 and paras [0055]-[0084] most notable [0057] that discloses write stream management within the controller identifies write commands (a common command type) that have matching parameters such as 714b (the sequential queue id) and 714C (the address) where the address is identified as sequential for a plurality of commands to be executed.)
the determining being based on memory addresses of the plurality of command requests, queue identifiers of the plurality of command requests, and namespace identifiers of the plurality of command requests provided by respective entries stored in the command queue, (Ramalingam Figs. 7 and 8 and paras [0055]-[0084] most notable [0057] that discloses write stream management within the controller identifies write commands (a common command type) that have matching parameters such as 714b (the sequential queue id) and 714C (the address) where the address is identified as sequential for a plurality of commands to be executed.)
… the plurality of command requests corresponding to two or more sub-sequences of entries within the command queue; (Ramalingam Figs. 7 and 8 and paras [0055]-[0084] most notable [0057] that discloses write stream management within the controller identifies write commands (a common command type) that have matching parameters such 714C (the address) where the address is identified as sequential for a plurality of commands to be executed.)
and causing execution of a preconditioned operation based on the plurality of command requests. (Ramalingam Figs. 7 and 8 and paras [0055]-[0084] that identifies a sequence of commands that are determined to be sequential within a single stream id and Fig. 3 and para [0044] discloses that these identified collection of commands are placed/written to a region assigned to the sequential write stream.)
Ramalingam [0016] discloses the write streams may be assigned different identification names that may be assigned to a particular storage area or region. However, Ramalingam does not explicitly tie the storage stream name with a namespace, nor does Ramalingam explicitly disclose a storage namespace. Thus Ramalingam does not explicitly teach the command request in the command queue, the entry comprising … a namespace identifier associated with the command request, and a memory address of the command request, … determining, in the command queue, a plurality of command requests of a common command type to be executed with respect to a sequence of memory addresses, the determining being based on memory addresses of the plurality of command requests, queue identifiers of the plurality of command requests, and namespace identifiers of the plurality of command requests provided by respective entries stored in the command queue, … the determining comprising filtering the command queue based on a single common queue identifier and a single common namespace identifier such that the plurality of command requests is commonly associated with both the single common queue identifier and the single common namespace identifier,
Subraya, of a similar field of endeavor, further discloses the command request in the command queue, the entry comprising … a namespace identifier associated with the command request, and a memory address of the command request, (Subraya Fig. 1 and [0010] discloses a Memory controller that writes data to separate storage areas, where each storage area is a namespace defined by a memory address range and associated with a specific queue id. The queue id is created by the memory controller and is associated with the namespace where the association is maintained by the memory controller in a HBA Driver Table as shown in Fig. 2 of Subraya. Thus when Ramalingam writes data to separate writes streams as shown in Fig. 4 of Ramalingam, the solution of Ramalingam in view of Subraya would create separate queues, each queue associated with a queue id and a namespace as shown in Fig. 2 of Subraya.)
… determining, in the command queue, a plurality of command requests of a common command type to be executed with respect to a sequence of memory addresses, the determining being based on memory addresses of the plurality of command requests, queue identifiers of the plurality of command requests, and namespace identifiers of the plurality of command requests provided by respective entries stored in the command queue, (Subraya Fig. 1 and [0010] discloses each queue is associated with a queue id and a namespace as tracked in the table shown in Fig. 2 of Subraya. See also Subraya [0026]-[0032] that details how the table in Fig. 2 is created & used. Subraya [0016] discloses one submission queue is generally sufficient for a single namespace. Thus while a single namespace might be associated with two or more queues, it is generally not required and there is a 1-to-1 association with queue ids and namespaces. Thus Subraya suggests the address provided in the command is associated with both a single namespace id and a single queue ID. Subraya [0021] discloses many arbitration mechanisms are available to execute the commands in the queue, including scheduling all of the commands in a high priority queue and then moving to a next queue and scheduling all of the commands in a second/lower priority queue. Thus Ramalingam in view of Subraya would schedule/determine to select for scheduling all the commands associated with a specific high priority queue id and its associated namespace. Thus Ramalingam in view of Subraya would
determine a plurality of command requests .. to be executed with respect to a sequence of memory addresses, the determining being based on memory addresses of the plurality of command requests, queue identifiers of the plurality of command requests, and namespace identifiers of the plurality of requests.)
… the determining comprising filtering the command queue based on a single common queue identifier and a single common namespace identifier such that the plurality of command requests is commonly associated with both the single common queue identifier and the single common namespace identifier, (Subraya Fig. 1 and [0010] discloses each queue is associated with a queue id and a namespace as tracked in the table shown in Fig. 2 of Subraya. See also Subraya [0026]-[0032] that details how the table in Fig. 2 is created & used. As detailed above, Subraya suggests the address provided in the command is associated with both a single namespace id and a single queue ID. Subraya [0021] discloses many arbitration mechanisms are available to execute the commands in the queue, including scheduling all of the commands in a high priority queue and then moving to a next queue and scheduling all of the commands in a second/lower priority queue. Thus the solution will schedule commands from the highest priority queue (from a single queue id that is associated with a single namespace where the commands to schedules are associated with both the common queue id and common namespace.)
Ramalingam and Subraya are in a similar field of endeavor as both relate to supporting storage in a NMVe environment. Thus it would have been obvious to a person of ordinary skill in the art to incorporate the priority of the storage areas, identified by namespaces and associated with a specific queue id, and handled by a user defined priority as taught by Subraya into the solution of Ramalingam that schedules writing data to specific storage areas identified by a name. Thus combining prior art elements according to known methods to yield predictable results (to enable the hosts of Ramalingam that writes data to named storage areas, to write to specific namespaces associated with a queue id for that namespace that is assigned by the user to a given priority level.
The motivation to combine Subraya into the solution of Ramalingam for claims 5-8, and 12 are the same as set forth in claim 1 above.
Regarding claim 7, Ramalingam and Subraya teaches all of the limitations of claim 1 above. Ramalingam further teaches wherein the preconditioned operation comprises a merging operation configured to merge the plurality of command requests into a single command request to be executed on the sequence of memory addresses. (Ramalingam [0044] discloses once a sequence of commands are identified as belong to a sequential write stream the system aggregates (i.e. merges) the data to write (the write data) and writes the data to a storage area or region assigned to the sequential write stream, thus merges the aggregated data to write into a single command request for the write stream.)
Regarding claim 8, the combination of Ramalingam and Subraya teaches all of the limitations of claim 7 above. Ramalingam further teaches wherein the common command type is a read command type. (Ramalingam [0044] discloses once a sequence of commands are identified as belong to a sequential write stream the system aggregates (i.e. merges) the data to write (the write data) and writes the data to a storage area or region assigned to the sequential write stream, thus merges the aggregated data to write into a single command request for the write stream.)
Regarding claim 12, Ramalingam and Subraya teaches all of the limitations of claim 1 above. Ramalingam further teaches wherein the submission queue is a select submission queue, wherein the queue identifier is a select queue identifier, (Examiner notes that the instant application does not contain an explicit definition for the term “select submission queue” and Examiner has interpreted a “select submission queue” to be a “queue that contains entries that are selected” and a “select queue identifier” is an identifier of a queue for an entry in the select submission queue.. Ramalingam Fig. 2 and paras [0027]-[0028] and [0056] that shows the entries in the Block Storage Controller queue that is an example of a submission queue that contain a submission queue id for each command entry (i.e. a select queue identifier) and the system selects items from the queue to create a sequential write stream request.)
and wherein the operations comprise: receiving a set of command requests from the host system, (Ramalingam [0002] discloses each processing node (host) has one or more submission queues to receive command requests from the processor nodes. Ramalingam Fig. 1 and para [0026] discloses the Computing System 100 may be a personal computer, a mainframe, a telephony device, a smart phone, etc. thus Computing System 100 may represent a host device.)
each individual command request in the set of command requests including an individual queue identifier, (Ramalingam Fig. 2 and para [0027] discloses that the Block Storage Controller 110 receives command requests from the submission queues at the nodes and places them in a common queue depicted in Fig. 2 of Ramalingam that shows each command request in the common submission queues is associated with a queued identifier (i.e. the Queue Entry Field 714b that identifies the submission queue id for the request.)
the individual command request being stored to an individual submission queue of the plurality of submission queues, the individual submission queue associated with the individual queue identifier. (Ramalingam Figs. 1 and 2 and paras [0002] and [0023]-[0029] discloses there are a plurality of nodes and there may be a submission queue per node, thus discloses an individual submission queue (per node) for the plurality of submission queues.
Regarding claim 13, Ramalingam teaches At least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processing device of a memory sub-system, cause the processing device to perform operations comprising: * Ramalingam [0141] teaches that the solution may be implemented as a computer program production maintained in a computer readable storage medium, where a processor may read and execute the code causing the processor to implement the solution.)
The remainder of claim 13 recites limitations described in claim 1 above, where a memory device is an example of a memory sub-system as the memory device of claim is within the solid state drive of Ramalingam, and thus is rejected based on the teaching and rationale of claim 1 above.
Regarding claim 18, Ramalingam and Subraya teaches all of the limitations of claim 13 above.
The remainder of claim 18 recites limitations described in claim 7 above, and thus is rejected based on the teaching and rationale of claim 7 above.
Regarding claim 20, Ramalingam teaches A method comprising: (Ramalingam [0155] teaches the solution may be implemented as a method.)
retrieving, by a processing device of a memory sub-system and from a submission queue of the memory sub-system, a command request, (Ramalingam Fig. 2 and para [0027] discloses that the Block Storage Controller 110 receives command requests from the submission queues at the nodes and places them in a common queue depicted in Fig. 2 of Ramalingam. The Block Storage Controller is within the Solid State Drive 106, thus within a processing device.)
the submission queue being associated with a queue identifier; (Ramalingam Fig. 2 and paras [0027]-[0028] that discloses the completion queue on the storage controller contains entries from a plurality of submission queue id’s, thus is associated with one or more queue identifiers.)
storing, by the processing device, an entry for the command request in a command queue of the memory sub-system, the entry comprising a command queue sequence identifier, the queue identifier associated with the submission queue from which the command request is retrieved, a namespace identifier associated with the command request, and a memory address of the command request, the memory address corresponding to a memory location on the memory sub-system; (Ramalingam Fig. 2 and paras [0027]-[0028] and [0056] that shows the entries in the Block Storage Controller queue contain a submission queue id associated with the submission queue from which the command request was retrieved and a logical block address for the command and the Solid State drive 106 (the processing device) maintains this in an ordered circular queue managed by head pointer, thus each index for each entry into the table is an example of a command queue sequence identifier.)
determining, by the processing device and in the command queue, a plurality of command requests of a common command type to be executed with respect to a sequence of memory addresses, (Ramalingam Figs. 7 and 8 and paras [0055]-[0084] most notable [0057] that discloses write stream management within the controller (i.e. within the Solid State Drive 106 that is the processing device) identifies write commands (a common command type) that have matching parameters such as 714b (the sequential queue id) and 714C (the address) where the address is identified as sequential for a plurality of commands to be executed.)
The remainder of claim 20 is disclosed in claim 1 above and thus is rejected based on the teaching and rationale of claim 1 above.
Regarding claim 24, Ramalingam and Subraya teaches all of the limitations of claim 18 above.
The remainder of claim 18 recites limitations described in claim 8 above, and thus is rejected based on the teaching and rationale of claim 8 above.
Regarding claim 25, Ramalingam and Subraya teaches all of the limitations of claim 13 above.
The remainder of claim 25 recites limitations described in claim 12 above, and thus is rejected based on the teaching and rationale of claim 12 above.
Regarding claim 30, Ramalingam and Subraya teaches all of the limitations of claim 20 above.
The remainder of claim 30 recites limitations described in claim 12 above, and thus is rejected based on the teaching and rationale of claim 12 above.
Claims 5-6, 17, 23, and 26-29 are rejected under 35 U.S.C. 103 as being unpatentable over Ramalingam (RAMALINGAM US 2016/0283116 A1) in view of Subraya (Subraya US 2020/0042236 A1) as detailed in claims 113, and 20 above and further in view of Navon (Navon et al., US 2020/0242037 A1).
Regarding claim 5, Ramalingam and Subraya teaches all of the limitations of claim 1 above. Ramalingam further teaches wherein the common command type is a read command type, (Ramalingam [0026] discloses the system may queue read, write or other storage commands, thus the command type may be a read command type.)
However, the combination does not explicitly teach and wherein the preconditioned operation comprises a read-ahead operation configured to prefetch stored data from a set of memory addresses based on the sequence of memory addresses.
Navon, of a similar field of endeavor, further teaches and wherein the preconditioned operation comprises a read-ahead operation configured to prefetch stored data from a set of memory addresses based on the sequence of memory addresses. (Navon [0034] teaches that in order to improve performance of a storage device the system may look for a pattern match between one or more current commands to find one or more read commands that previously matched that pattern to prefetch the one or more read commands that match the pattern. Thus the solution of Ramalingam in view of Navon would look for a series of read requests that match a particular pattern, compare it to a previous pattern, and prefetch data according to that match.)
Ramalingam, Subraya, and Navon are in a similar field of endeavor as both relate to scheduling requests managed in NVMe submission queues. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate aggregating reads including the reading of prefetch data (including data with a common namespace) as taught by Navon into the solution of Ramalingam and Subraya that aggregates sequential data requests to improve the efficiency of processing the data to/from the storage device, thus combining prior art elements according to known methods to yield predictable results (improve the efficiencies of read requests as well as write requests).
The motivation to combine Navon into the solution of Ramalingam and Subraya for claim 6 is the same as set forth in claim 1 above.
Regarding claim 6, the combination of Ramalingam, Subraya, and Navon teaches the limitations of claim 5 above.
Navon further teaches wherein the sequence of memory addresses is a first sequence of memory addresses, and wherein the set of memory addresses comprises a second sequence of memory addresses. (Navon [0034] teaches that in order to improve performance of a storage device the system may look for a pattern match between one or more current commands to find one or more read commands that previously matched that pattern to prefetch the one or more read commands that match the pattern. Thus the solution of Ramalingam in view of Navon would look for a series of read requests that match a particular pattern, compare it to a previous pattern, and prefetch data according to that match and the one or more current commands to merge are an example of a first sequence of memory addresses and the one or more prefetch read requests are an example of a second sequence of memory addresses.)
The motivation to combine Navon into the existing combination is the same as set forth in claim 5 above.
Regarding claim 17, Ramalingam and Subraya teaches all of the limitations of claim 13 above.
The remainder of claim 17 recites limitations described in claim 5 above, and thus is rejected based on the teaching and rationale of claim 5 above.
Regarding claim 23, Ramalingam and Subraya teaches all of the limitations of claim 17 above.
The remainder of claim 23 is disclosed in claim 6 above and thus is rejected based on the teaching and rationale of claim 6 above.
Regarding claim 26, Ramalingam and Subraya teaches all of the limitations of claim 20 above.
The remainder of claim 26 recites limitations described in claim 5 above, and thus is rejected based on the teaching and rationale of claim 5 above.
Regarding claim 27, Ramalingam, Subraya, and Navon teaches all of the limitations of claim 26 above.
The remainder of claim 27 recites limitations described in claim 6 above, and thus is rejected based on the teaching and rationale of claim 6 above.
Regarding claim 28, Ramalingam, Subraya, and Navon teaches all of the limitations of claim 27 above.
The remainder of claim 28 recites limitations described in claim 7 above, and thus is rejected based on the teaching and rationale of claim 7 above.
Regarding claim 29, Ramalingam, Subraya, and Navon teaches all of the limitations of claim 28 above.
The remainder of claim 29 recites limitations described in claim 8 above, and thus is rejected based on the teaching and rationale of claim 8 above.
Response to Remarks
Examiner thanks Applicant for their claim amendments and remarks on pages 8-9 of their filing 6/17/2026. They have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration and in response to the claims as amended, a new ground(s) of rejection is made in view of newly cited Subraya as detailed above.
Conclusion
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138
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