DETAILED ACTION
This office action is in response to an Amendment/Request For Reconsideration After Non-Final rejection filed 12/10/2025 for application 18/770,982 filed 7/12/2024 that claims priority to provisional 63/526,517 filed 7/13/2023.
Claims 1, 10-11, 13, and 20 have been amended. Claims 9 and 19 are cancelled. Claims 21-22 are new. Thus claims 1-8, 10-18, and 20-22 have been examined.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-18, and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Ramalingam (RAMALINGAM US 2016/0283116 A1) in view of Navon (Navon et al., 2020/0242037 A1).
Regarding claim 1, Ramalingam teaches A system comprising: (Ramalingam Fig. 1 and
para [0008] discloses the solution is directed to a computing system)
a plurality of submission queues configured to receive command requests from a host system; (Ramalingam [0002] discloses each processing node (host) has one or more submission queues to receive command requests from the processor nodes. Ramalingam Fig. 1 and para [0026] discloses the Computing System 100 may be a personal computer, a mainframe, a telephony device, a smart phone, etc. thus Computing System 100 may represent a host device.)
a command queue configured to store command requests awaiting execution on the system; (Ramalingam [0003] discloses the share storage has a controller that receives the storage commands and stores the storage commands in a in a common pending storage command queue to await execution by the shared storage.)
a memory device; (Ramalingam Fig. 1 and para [0024] discloses Nonvolatile Storage 120 that is an example of a memory device.)
and a processing device, operatively coupled to the memory device, configured to perform operations comprising: (Ramalingam [0024] discloses Block Storage Controller 110 with Solid State Drive 106, that is an example of a processing device coupled to the memory device. See also Ramalingam [0090]-]0093] that discloses the controller is configure to perform the operations.)
retrieving, from a submission queue of the plurality of submission queues, a command request, the submission queue being associated with a queue identifier; (Ramalingam Fig. 2 and para [0027] discloses that the Block Storage Controller 110 receives command requests from the submission queues at the nodes and places them in a common transmission (i.e. submission) queue depicted in Fig. 2 of Ramalingam that shows each command request in the common submission queues is associated with a queued identifier (i.e. the Queue Entry Field 714b that identifies the submission queue id for the request).)
storing an entry for the command request in the command queue, the entry comprising a command queue sequence identifier, the queue identifier associated with the submission queue from which the command request is retrieved, … and a memory address of the command request, the memory address corresponding to a memory location on the memory device; (Ramalingam Fig. 2 and paras [0027]-[0028] and [0056] that shows the entries in the Block Storage Controller queue contain a submission queue id associated with the submission queue from which the command was retrieved and a logical block address for the command and the system maintains this in an ordered circular queue managed by head pointer, thus each index for each entry into the table is an example of a command queue sequence identifier.)
determining, in the command queue, a plurality of command requests of a common command type to be executed with respect to a sequence of memory addresses, the determining being based on memory addresses of the plurality of command request, … and queue identifiers of the plurality of command requests; (Ramalingam Figs. 7 and 8 and paras [0055]-[0084] most notable [0057] that discloses write stream management within the controller identifies write commands (a common command type) that have matching parameters such as 714b (the sequential queue id) and 714C (the address) where the address is identified as sequential for a plurality of commands to be executed.)
and causing execution of a preconditioned operation based on the plurality of command requests. (Ramalingam Figs. 7 and 8 and paras [0055]-[0084] that identifies a sequence of commands that are determined to be sequential within a single stream id and Fig. 3 and para [0044] discloses that these identified collection of commands are placed/written to a region assigned to the sequential write stream.)
However, Ramalingam does not explicitly teach a namespace, thus does not explicitly teach storing an entry in the command queue, the entry comprising a namespace identifier associated with the command request … and determining .. a common command type .. based on … and namespace identifiers of the plurality of command requests provided by respective entries stored in the command queue.
Navon, of a similar field of endeavor, further teaches storing an entry in the command queue, the entry comprising a namespace identifier associated with the command request (Navon [0127]-[0128] and [0131] teaches that an address space may be assigned to a namespace and command sequencies may be identified by a namespace identifier which may be used to identify matching patterns, where the pattern is a match if the requests are to the same namespace. Navon [0127] discloses the submission queues feeding a common submission queue may provide a namespace identifier when making requests. Thus the solution of Ramalingam in view of Navon would track the namespace in the table of Ramalingam Fig. 2 and use the namespace to determine if the commands had matching parameters to better identify related data that is more generally sequential that may be combined (per Ramalingam [0030].)
and determining .. a common command type .. based on … and namespace identifiers of the plurality of command requests provided by respective entries stored in the command queue. (Navon [0127]-[0128] and [0131] as detailed immediately above, where the solution of Ramalingam in view of Navon would track the namespace in the table of Ramalingam Fig. 2 and use the namespace to determine if the commands had matching parameters to better identify related data that is more generally sequential that may be combined (per Ramalingam [0030].)
Ramalingam and Navon are in a similar field of endeavor as both relate to scheduling requests managed in NVMe submission queues. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate aggregating reads including the reading of prefetch data (including data with a common namespace) as taught by Navon into the solution of Ramalingam that aggregates sequential data requests to improve the efficiency of processing the data to/from the storage device, thus combining prior art elements according to known methods to yield predictable results (improve the efficiencies of read requests as well as write requests).
The motivation to combine Navon into the solution of Ramalingam for claims 2-8, and 10-12 are the same as set forth in claim 1 above.
Regarding claim 2, Ramalingam and Navon teaches all of the limitations of claim 1 above. Ramalingam further teaches wherein the determining of the plurality of command requests comprises filtering command requests in the command queue based on at least one queue identifier. (Examiner interprets ‘filtering’ to mean ‘selection of the plurality of command requests for requests that match’ the queue identifier. Ramalingam Figs. 7 and 8 and paras [0055]-[0084] most notable [0057]-[0058] discloses the that block controller selects for inclusion in the sequential write stream only the request that match the parameter 714b, the sequential stream id. )
Regarding claim 3, Ramalingam and Navon teaches all of the limitations of claim 1 above. Ramalingam further teaches wherein the plurality of command requests corresponds to two or more sub-sequences of entries in the command queue. (Consistent with paragraph [0058] two or more sub-sequences of entries are interpreted to be two or more commands that are directed to sequentially addressable memory. Ramalingam Fig. 7 and 8 and paras [0055]-[0084] most notable [0057]-[0058] that discloses the sequential write stream detection logic in the block stream controller is looking for sequential addresses (two or more) based on the queue entry field 714c (the logical block address field) being sequential.)
Regarding claim 4, Ramalingam and Navon teaches all of the limitations of claim 1 above. Ramalingam further teaches wherein the queue identifiers of the plurality of command requests comprise a single queue identifier. (Ramalingam Fig. 7 and 8 and paras [0055]-[0084] most notable [0057]-[0058] and [0060] that discloses the sequential write stream detection logic in the block stream controller is looking for matching parameters that are a matching submission queue id, thus a single queue identifier.
Regarding claim 5, Ramalingam and Navon teaches all of the limitations of claim 1 above. Ramalingam further teaches wherein the common command type is a read command type, (Ramalingam [0026] discloses the system may queue read, write or other storage commands, thus the command type may be a read command type.)
Navon further teaches and wherein the preconditioned operation comprises a read-ahead operation configured to prefetch stored data from a set of memory addresses based on the sequence of memory addresses. (Navon [0034] teaches that in order to improve performance of a storage device the system may look for a pattern match between one or more current commands to find one or more read commands that previously matched that pattern to prefetch the one or more read commands that match the pattern. Thus the solution of Ramalingam in view of Navon would look for a series of read requests that match a particular pattern, compare it to a previous pattern, and prefetch data according to that match.)
The motivation to combine Navon into the solution of Ramalingam is the same as set forth in claim 1 above.
Regarding claim 6, Ramalingam and Navon teaches all of the limitations of claim 5 above.
Navon further teaches wherein the sequence of memory addresses is a first sequence of memory addresses, and wherein the set of memory addresses comprises a second sequence of memory addresses. (Navon [0034] teaches that in order to improve performance of a storage device the system may look for a pattern match between one or more current commands to find one or more read commands that previously matched that pattern to prefetch the one or more read commands that match the pattern. Thus the solution of Ramalingam in view of Navon would look for a series of read requests that match a particular pattern, compare it to a previous pattern, and prefetch data according to that match and the one or more current commands to merge are an example of a first sequence of memory addresses and the one or more prefetch read requests are an example of a second sequence of memory addresses.)
The motivation to combine Navon into the existing combination is the same as set forth in claim 1 above.
Regarding claim 7, Ramalingam and Navon teaches all of the limitations of claim 1 above. Ramalingam further teaches wherein the preconditioned operation comprises a merging operation configured to merge the plurality of command requests into a single command request to be executed on the sequence of memory addresses. (Ramalingam [0044] discloses once a sequence of commands are identified as belong to a sequential write stream the system aggregates (i.e. merges) the data to write (the write data) and writes the data to a storage area or region assigned to the sequential write stream, thus merges the aggregated data to write into a single command request for the write stream.)
Regarding claim 8, Ramalingam and Navon teaches all of the limitations of claim 7 above.
Navon further discloses wherein the common command type is a read command type. (Navon [0034] teaches that in order to improve performance of a storage device the system may look for a pattern match between one or more current commands to find one or more read commands that previously matched that pattern to prefetch the one or more read commands that match the pattern. Thus the solution of Ramalingam in view of Navon would look for a series of read requests that match a particular pattern, compare it to a previous pattern, and prefetch data according to that match and the one or more current commands to merge are an example of a first sequence of memory addresses and the one or more prefetch read requests are an example of a second sequence of memory addresses.)
The motivation to combine Navon into the existing combination is the same as set forth in claim 1 above.
Regarding claim 10, Ramalingam and Navon teaches all of the limitations of clam 1 above.
Ramalingam in view of Navon further teaches wherein the determining of the plurality of command requests comprises filtering command requests in the command queue based on at least one queue identifier and at least one namespace identifier. (Examiner interprets ‘filtering’ to mean ‘selection of the plurality of command requests for requests that match’ the queue identifier. Navon [0127]-[0128] and [0131] discloses using a namespace to identify a series of requests belonging to a single source and thus may be sequential. Ramalingam Figs. 7 and 8 and paras [0055]-[0084] most notable [0057]-[0058] discloses the that block controller selects for inclusion in the sequential wrote stream only the request that match the parameter, thus the solution of Ramalingam in view of Navon would include only requests that match a namespace parameter, thus filter on a namespace parameter.)
The motivation to combine Navon into the existing solution is the same as set forth in claim 1 above.
Regarding claim 11, The solution of Ramalingam and Navon teaches all of the limitations of clam 1 above.
Ramalingam in view of Navon further teaches wherein the namespace identifiers of the plurality of command requests comprise a single namespace identifier. (Ramalingam Fig. 7 and 8 and paras [0055]-[0084] most notable [0057]-[0058] and [0060] that discloses the sequential write stream detection logic in the block stream controller is looking for matching parameters that are a matching submission queue id, thus a single queue identifier. Navon [0127]-[0128] and [0131] discloses using a namespace to identify a series of requests belonging to a single source and thus are potentially sequential. Thus the solution of Ramalingam in view of Navon would look for requests that have a common namespace, thus comprise a single namespace to aggregate as a single sequential request.)
The motivation to combine Navon into the existing solution is the same as set forth in claim 1 above.
Regarding claim 12, Ramalingam and Navon teaches all of the limitations of claim 1 above. Ramalingam further teaches wherein the submission queue is a select submission queue, wherein the queue identifier is a select queue identifier, (Examiner notes that the instant application does not contain an explicit definition for the term “select submission queue” and Examiner has interpreted a “select submission queue” to be a “queue that contains entries that are selected” and a “select queue identifier” is an identifier of a queue for an entry in the select submission queue.. Ramalingam Fig. 2 and paras [0027]-[0028] and [0056] that shows the entries in the Block Storage Controller queue that is an example of a submission queue that contain a submission queue id for each command entry (i.e. a select queue identifier) and the system selects items from the queue to create a sequential write stream request.)
and wherein the operations comprise: receiving a set of command requests from the host system, (Ramalingam [0002] discloses each processing node (host) has one or more submission queues to receive command requests from the processor nodes. Ramalingam Fig. 1 and para [0026] discloses the Computing System 100 may be a personal computer, a mainframe, a telephony device, a smart phone, etc. thus Computing System 100 may represent a host device.)
each individual command request in the set of command requests including an individual queue identifier, (Ramalingam Fig. 2 and para [0027] discloses that the Block Storage Controller 110 receives command requests from the submission queues at the nodes and places them in a common queue depicted in Fig. 2 of Ramalingam that shows each command request in the common submission queues is associated with a queued identifier (i.e. the Queue Entry Field 714b that identifies the submission queue id for the request.)
the individual command request being stored to an individual submission queue of the plurality of submission queues, the individual submission queue associated with the individual queue identifier. (Ramalingam Figs. 1 and 2 and paras [0002] and [0023]-[0029] discloses there are a plurality of nodes and there may be a submission queue per node, thus discloses an individual submission queue (per node) for the plurality of submission queues.
Regarding claim 13, Ramalingam teaches At least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processing device of a memory sub-system, cause the processing device to perform operations comprising: (Ramalingam [0141] teaches that the solution may be implemented as a computer program production maintained in a computer readable storage medium, where a processor may read and execute the code causing the processor to implement the solution.)
The remainder of claim 13 recites limitations described in claim 1 above, where a memory device is an example of a memory sub-system as the memory device of claim is within the solid state drive of Ramalingam, and thus is rejected based on the teaching and rationale of claim 1 above.
Regarding claim 14, Ramalingam and Navon teaches all of the limitations of claim 13 above.
The remainder of claim 14 recites limitations described in claim 2 above, and thus is rejected based on the teaching and rationale of claim 2 above.
Regarding claim 15, Ramalingam and Navon teaches all of the limitations of claim 13 above.
The remainder of claim 15 recites limitations described in claim 3 above, and thus is rejected based on the teaching and rationale of claim 3 above.
Regarding claim 16, Ramalingam and Navon teaches all of the limitations of claim 13 above.
The remainder of claim 16 recites limitations described in claim 4 above, and thus is rejected based on the teaching and rationale of claim 4 above.
Regarding claim 17, Ramalingam and Navon teaches all of the limitations of claim 13 above.
The remainder of claim 17 recites limitations described in claim 5 above, and thus is rejected based on the teaching and rationale of claim 5 above.
Regarding claim 18, Ramalingam and Navon teaches all of the limitations of claim 18 above.
The remainder of claim 14 recites limitations described in claim 7 above, and thus is rejected based on the teaching and rationale of claim 7 above.
Regarding claim 20, Ramalingam teaches A method comprising: (Ramalingam [0155] teaches the solution may be implemented as a method.)
retrieving, by a processing device of a memory sub-system and from a submission queue of the memory sub-system, a command request, (Ramalingam Fig. 2 and para [0027] discloses that the Block Storage Controller 110 receives command requests from the submission queues at the nodes and places them in a common queue depicted in Fig. 2 of Ramalingam. The Block Storage Controller is within the Solid State Drive 106, thus within a processing device.)
the submission queue being associated with a queue identifier; (Ramalingam Fig. 2 and paras [0027]-[0028] that discloses the completion queue on the storage controller contains entries from a plurality of submission queue id’s, thus is associated with one or more queue identifiers.)
storing, by the processing device, an entry for the command request in a command queue of the memory sub-system, the entry comprising a command queue sequence identifier, the queue identifier associated with the submission queue from which the command request is retrieved, … and a memory address of the command request, the memory address corresponding to a memory location on the memory sub-system; (Ramalingam Fig. 2 and paras [0027]-[0028] and [0056] that shows the entries in the Block Storage Controller queue contain a submission queue id associated with the submission queue from which the command request was retrieved and a logical block address for the command and the Solid State drive 106 (the processing device) maintains this in an ordered circular queue managed by head pointer, thus each index for each entry into the table is an example of a command queue sequence identifier.)
determining, by the processing device and in the command queue, a plurality of command requests of a common command type to be executed with respect to a sequence of memory addresses, (Ramalingam Figs. 7 and 8 and paras [0055]-[0084] most notable [0057] that discloses write stream management within the controller (i.e. within the Solid State Drive 106 that is the processing device) identifies write commands (a common command type) that have matching parameters such as 714b (the sequential queue id) and 714C (the address) where the address is identified as sequential for a plurality of commands to be executed.)
the determining being based on memory addresses of the plurality of command requests, queue identifiers of the plurality of command requests… ; (Ramalingam Fig. 2 and paras [0027]-[0028] and [0056]-0057] that shows the entries in the Block Storage Controller queue contain a submission queue id and a logical block address for the command and are used to identify commands that should be aggregated into a single sequential write stream request.)
and causing, by the processing device, execution of a preconditioned operation based on the plurality of command requests. (Ramalingam Figs. 7 and 8 and paras [0055]-[0084] that identifies a sequence of commands that are determined to be sequential within a single stream id and Fig. 3 and para [0044] discloses that these identified collection of commands are placed/written to a region assigned to the sequential write stream.)
However, Ramalingam does not explicitly teach a namespace, thus does not explicitly teach storing an entry in the command queue, the entry comprising a namespace identifier associated with the command request … and determining .. a common command type .. based on … and namespace identifiers of the plurality of command requests provided by respective entries stored in the command queue.
Navon, of a similar field of endeavor, further teaches storing an entry in the command queue, the entry comprising a namespace identifier associated with the command request (Navon [0127]-[0128] and [0131] teaches that an address space may be assigned to a namespace and command sequencies may be identified by a namespace identifier which may be used to identify matching patterns, where the pattern is a match if the requests are to the same namespace. Navon [0127] discloses the submission queues feeding a common submission queue may provide a namespace identifier when making requests. Thus the solution of Ramalingam in view of Navon would track the namespace in the table of Ramalingam Fig. 2 and use the namespace to determine if the commands had matching parameters to better identify related data that is more generally sequential that may be combined (per Ramalingam [0030].)
and determining .. a common command type .. based on … and namespace identifiers of the plurality of command requests provided by respective entries stored in the command queue. (Navon [0127]-[0128] and [0131] as detailed immediately above, where the solution of Ramalingam in view of Navon would track the namespace in the table of Ramalingam Fig. 2 and use the namespace to determine if the commands had matching parameters to better identify related data that is more generally sequential that may be combined (per Ramalingam [0030].)
Ramalingam and Navon are in a similar field of endeavor as both relate to scheduling requests managed in NVMe submission queues. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate aggregating reads including the reading of prefetch data (including data with a common namespace) as taught by Navon into the solution of Ramalingam that aggregates sequential data requests to improve the efficiency of processing the data to/from the storage device, thus combining prior art elements according to known methods to yield predictable results (improve the efficiencies of read requests as well as write requests).
Regarding claim 21, Ramalingam and Navon teaches all of the limitations of claim 13 above.
Navon further teaches wherein the determining of the plurality of command requests comprises filtering command requests in the command queue based on at least one queue identifier and at least one namespace identifier. (Navon [0131] teaches that when predicting the next read command to prefetch the system considers the source of the data and the namespace identifier. Thus the solution of Ramalingam that identifies the source of the data by a queue identifier would predict the next read command to prefetch using both the namespace identifier and the one namespace identifier stored within the command. See also Navon [0127]-[0128] and [0131] that teaches an address space may be assigned to a namespace and command sequencies may be identified by a namespace identifier which may be used to identify matching patterns.)
The motivation to combine Navon into the existing combination is the same as set forth in claim 13 above.
Regarding claim 22, Ramalingam and Navon teaches all of the limitations of claim 13 above.
Navon further teaches wherein the namespace identifiers of the plurality of command requests comprise a single namespace identifier. (Navon [0131] teaches that when predicting the next read command to prefetch the system considers the source of the data and the namespace identifier. See also Navon [0127]-[0128] and [0131] that teaches an address space may be assigned to a namespace and command sequencies may be identified by a namespace identifier which may be used to identify matching patterns. Thus the solution of Ramalingam that identifies the source of the data by a queue identifier would predict the next read command to prefetch using both the namespace identifier and the one namespace identifier stored within the command and would look for matching values (i.e. a single value common to multiple commands to combine).
The motivation to combine Navon into the existing combination is the same as set forth in claim 13 above.
Response to Remarks
Examiner thanks applicant for their claim amendments of 12/10/2025. They have been fully considered.
The Rejection of Claims Under § 102
Applicant argues on page 7 of their remarks that Ramalingam does not teach the newly amended limitations to claim 1.
Examiner agrees. And thus the 102 rejections to claims 1-4, 7, 12-16, and 18 has been withdrawn. However, as detailed above, these claims are now rejected under U.S.C. § 103 due to new citations to previously cited Navon.
The Rejection of Claims Under § 102
Applicant argues on page 8 of their remarks that Navon fails to teach or suggest the newly amended limitations as “Nothing in Navon discussed namespace identifiers being stored in command-queue entries”.
Examiner respectfully disagrees. Navon [0127] discloses a system that predicts the next prefetch read command to perform that may track commands from a host submission queue that includes queued commands with different namespace identifiers NS1, NS2, NS3 that would be beneficial to track commands as doing so would improve command prediction accuracy.
Applicants arguments with respect to 5, 6, 8, 10, 11, 13, 17, and 20 all rely upon perceived errors in the combination of Ramalingam and Navon which have been addressed in the claim rejections and remarks above.
New Claims
Examiner thanks applicant for their new claims 21 and 22. See the rejection above for a detailed response to these newly amended claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M. GIROUARD whose telephone number is (469)295-9131. The examiner can normally be reached M-F 9:30 - 7:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138