DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: reference number 2000 in Fig. 10. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4-6, and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (Pub. No.: US 20230137691 A1), hereinafter as Lai, in view of Yu et al. (Pub. No.: US 20220293568 A1), hereinafter as Yu.
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Image A: Lai’s Fig. 6, showcasing the various top and bottom surfaces of semiconductor chips.
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Image B: Lai’s Fig. 6, comparing the widths of the upper dielectric layer and upper semiconductor chip.
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Image C: closeup of Yu’s Fig. 4D, showcasing top and bottom surfaces of semiconductor chips.
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Image D: Lai’s Fig. 6, showcasing the various surfaces of upper dielectric layer.
With regards to claim 1, Lai teaches a semiconductor package, comprising: a lower semiconductor chip (see Lai Fig. 6, package substrate 200; Lai [0079] and [0102]: “Referring to FIG. 6, the fifth alternate embodiment structure illustrated may be formed in a similar manner according to the processes and techniques described with reference to FIGS. 1A-1L.”) comprising a top surface (see Image A) and a bottom surface (see Image A) that are opposite to each other (see Image A); an upper semiconductor chip (see Lai Fig. 6, hybrid interposer 601; Lai [0102]) on the top surface of the lower semiconductor chip (see Lai Fig. 6) and comprising a bottom surface (see Image A) and a top surface (see Image A) that are opposite to each other (see Image A); a dielectric layer (see Lai Fig. 6, underfill material portion 292; Lai [0081] and [0102]) between the top surface of the lower semiconductor chip and the bottom surface of the upper semiconductor chip (see Lai Fig. 6 and Image A); an upper dielectric layer (see Lai Fig. 6, underfill material portion 492; Lai [0068] and [0102]) on the top surface of the upper semiconductor chip (see Lai Fig. 6 and Image A); and a connection structure (see Lai Fig. 6, solder material portions 450 and package-side bonding pads 448; Lai [0077], [0074], and [0102]) that penetrates the dielectric layer (see Lai Fig. 6), the connection structure being connected to the lower semiconductor chip and the upper semiconductor chip (see Lai Fig. 6), wherein a width (see Image B) of the bottom surface of the upper semiconductor chip is greater than a width (see Image B) of the upper dielectric layer in a first direction (see Image B, x-direction), and wherein the first direction is parallel to the top surface of the lower semiconductor chip (see Image B).
Lai does not teach a lower dielectric layer between the dielectric layer and the bottom surface of the upper semiconductor chip.
Yu teaches a dielectric layer (see Yu Fig. 4D, bonding film 106; Yu [0040]) between a top surface (see Image C) of a lower semiconductor chip (see Yu Fig. 4D, first die 100; Yu [0027]) and a bottom surface (see Image C) of a upper semiconductor chip (see Yu Fig. 4D, second die 110; Yu [0027]); a lower dielectric layer (see Yu Fig. 4D, bonding film 116; Yu [0050]) between the dielectric layer and the bottom surface of the upper semiconductor chip (see Yu Fig. 4D); and a connection structure (see Yu Fig. 4D, bonding pads 108 and bonding pads 118; Yu [0040] and [0050]) that penetrates the dielectric layer and the lower dielectric layer (see Yu Fig. 4D), the connection structure being connected to the lower semiconductor chip and the upper semiconductor chip (see Yu Fig. 4D).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device of Lai with the dielectric layer and lower dielectric layer taught by Yu in order to bond the two chips together well and reduce the amount of air pockets. It would also be best to substitute the connection structure of Lai with the connection structure taught by Yu in order to keep the bonding process consistent with that of the dielectric layers being used.
With regards to claim 4, Lai and Yu teach the semiconductor package of claim 1, wherein the dielectric layer (see Yu Fig. 4D, bonding film 106) contacts the lower dielectric layer (see Yu Fig. 4D, bonding film 116).
With regards to claim 5, Lai and Yu teach the semiconductor package of claim 1, wherein the upper dielectric layer (see Lai Fig. 6, underfill material portion 492) has a bottom surface (see Image D) and a top surface (see Image D) that are opposite to each other (see Image D), wherein the bottom surface of the upper dielectric layer contacts the top surface (see Image A) of the upper semiconductor chip (see Lai Fig. 6, hybrid interposer 601), and wherein a lateral surface (see Image D) of the upper dielectric layer is rounded (see Lai Fig. 6 and Image D).
With regards to claim 6, Lai and Yu teach the semiconductor package of claim 5, wherein the width (see Image B) of the upper dielectric layer (see Lai Fig. 6, underfill material portion 492) is less than a width (the width of the lower dielectric layer in Yu is the same width as the bottom surface of the upper semiconductor chip. Because of this, when modifying the device of Lai with Yu, it would make sense to have the width of the lower dielectric layer match the width of the bottom surface of the upper semiconductor chip of Lai. See Image B for width comparison between the upper dielectric layer and the bottom surface of the upper semiconductor chip.) of the lower dielectric layer (see Yu Fig. 4D, bonding film 116) in the first direction (see Image B, x-direction).
With regards to claim 8, Lai and Yu teach the semiconductor package of claim 1, wherein the connection structure (see Yu Fig. 4D, bonding pads 108 and bonding pads 118) comprises: a first connection part (see Yu Fig. 4D, bonding pads 108) in the dielectric layer (see Yu Fig. 4D, bonding film 106); and a second connection part (see Yu Fig. 4D, bonding pads 118) in the lower dielectric layer (see Yu Fig. 4D, bonding film 116).
With regards to claim 9, Lai and Yu teach the semiconductor package of claim 8, wherein the first connection part (see Yu Fig. 4D, bonding pads 108) and the second connection part (see Yu Fig. 4D, bonding pads 118) comprise same material (see Yu [0040]: “In some embodiments, the bonding pads 108 may be made of copper or other suitable metal that is easy for forming hybrid bonding.”; and see Yu [0050]: “In some embodiments, the bonding pads 118 may be made of copper or other suitable metal that is easy for forming hybrid bonding.” Bonding pads 108 and 118 are both made of copper, so comprise a same material.).
With regards to claim 10, Lai and Yu teach the semiconductor package of claim 8, wherein the lower semiconductor chip (see Lai Fig. 6, package substrate 200) comprises: a lower circuit layer (see Lai Fig. 6, board-side surface laminar circuit (SLC) 240; Lai [0080] and [0102]); and a lower through via (see Lai Fig. 6, through-core via structures 214; Lai [0079] and [0102]) that penetrates the lower semiconductor chip (see Lai Fig. 6) and is connected to the lower circuit layer (see Lai Fig. 6), wherein the first connection part (see Yu Fig. 4D, bonding pads 108) is connected to the lower through via (see Lai Fig. 6).
With regards to claim 11, Lai and Yu teach the semiconductor package of claim 10, wherein the upper semiconductor chip (see Lai Fig. 6, hybrid interposer 601) comprises: an upper circuit layer (see Lai Fig. 6, organic structure 470; Lai [0061] and [0102]); and an upper through via (see Lai Fig. 6, through-substrate via (TSV) structures 475; Lai [0046] and [0102]) that penetrates the upper semiconductor chip (see Lai Fig. 6) and is connected to the upper circuit layer (see Lai Fig. 6), wherein the second connection part (see Yu Fig. 4D, bonding pads 118) is connected to the upper through via (see Lai Fig. 6).
Claims 2, 3, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Yu, in view of Fukazawa (Pub. No.: US 20060138629 A1).
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Image E: close up of Fukazawa Fig. 9A, showcasing differing widths of surfaces of upper semiconductor substrate.
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Image F: annotated version of Fukazawa Fig. 13.
With regards to claim 2, Lai and Yu teach the semiconductor package of claim 1, wherein the upper semiconductor chip (see Lai Fig. 6, hybrid interposer 601) includes: an upper circuit layer (see Lai Fig. 6, organic structure 470; Lai [0061] and [0102]) on the bottom surface (see Image A) of the upper semiconductor chip (see Lai Fig. 6); and an upper semiconductor substrate (see Lai Fig. 6, molding material layer 473; Lai [0046] and [0102]) on the top surface (see Image A) of the upper semiconductor chip (see Lai Fig. 6), wherein a top surface (see Image A) of the upper semiconductor substrate corresponds to the top surface of the upper semiconductor chip (see Image A), wherein a bottom surface (see Image A) of the upper semiconductor substrate is on the upper circuit layer (see Image A).
Lai and Yu do not teach a width of the top surface of the upper semiconductor substrate is less than a width of the bottom surface of the upper semiconductor substrate in the first direction.
Fukazawa teaches a width (see Image E) of a top surface (see Fukazawa Fig. 9A, rear surface 10B; Fukazawa [0096]) of an upper semiconductor substrate (see Fukazawa Fig. 9A, semiconductor chip 10; Fukazawa [0096]) is less than a width (see Image E) of a bottom surface (see Fukazawa Fig. 9A, active surface 10A; Fukazawa [0096]) of the upper semiconductor substrate in a first direction (see Image E, x-direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor chips of Lai and Yu with the rounded corners taught by Fukazawa in order to relieve stress concentration at the edges of the chips (see Fukazawa [0098]: “Therefore the curved sections 21 relieve stress concentration at the edges 23b of the rear surface 10B of the semiconductor chip 10.”).
With regards to claim 3, Lai, Yu, and Fukazawa teach the semiconductor package of claim 2, wherein a lateral surface (see Fukazawa Fig. 9A, side wall section 10C; Fukazawa [0098]) of the upper semiconductor substrate (see Fukazawa Fig. 9A, semiconductor chip 10) is rounded (see Fukazawa Fig. 9A, curved sections 21; Fukazawa [0098]).
With regards to claim 7, Lai and Yu teach the semiconductor package of claim 5.
Lai and Yu do not teach that a width of the upper semiconductor chip in the first direction decreases as a distance from the lower semiconductor chip along a direction perpendicular to the top surface of the lower semiconductor chip increases.
Fukazawa teaches that a width of an upper semiconductor chip (see Image F) in a first direction (see Image F, x-direction) decreases (because of the rounded corners of the semiconductor chip) as a distance from a lower semiconductor chip (see Image F) along a direction (see Image F, +Z direction) perpendicular to a top surface (see Image F) of the lower semiconductor chip increases (see Image F).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor chips of Lai and Yu with the rounded corners taught by Fukazawa in order to relieve stress concentration at the edges of the chips (see Fukazawa [0098]: “Therefore the curved sections 21 relieve stress concentration at the edges 23b of the rear surface 10B of the semiconductor chip 10.”).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (Patent No.: US 11362013 B2), hereinafter as Yeh, in view of Pendse (Pub. No.: US 20080136003 A1).
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Image G: close up of Yeh Fig. 15, showcasing top and bottom surfaces of semiconductor chips.
With regards to claim 12, Yeh teaches a semiconductor package, comprising: a lower semiconductor chip (see Yeh Fig. 15, thinned die 213; Yeh col. 9, ln. 59) comprising a top surface (see Image G) and a bottom surface (see Image G) that are opposite to each other (see Image G); a plurality of upper semiconductor chips (see Yeh Fig. 15, thinned dies 223, 233, and 243; Yeh col. 9, ln. 60) on the top surface of the lower semiconductor chip (see Yeh Fig. 15) and stacked in a direction perpendicular to the top surface of the lower semiconductor chip (see Yeh Fig. 15), the plurality of upper semiconductor chips comprising a first upper semiconductor chip (see Yeh Fig. 15, thinned die 223) and a second upper semiconductor chip (see Yeh Fig. 15, thinned die 233) adjacent to each other (see Yeh Fig. 15); a lower dielectric layer (see Yeh Fig. 19, die attach film 496; Yeh col. 12, ln. 37) between the first upper semiconductor chip and the second upper semiconductor chip (because Yeh is taking the same semiconductor chip and stacking it multiple times, the lower dielectric layer would be positioned between the first and second upper semiconductor chip as seen in Yeh Fig. 15 and 19.); an upper dielectric layer (see Yeh Fig. 19, insulating layer 498; Yeh col. 12, ln. 42) between the lower dielectric layer and the first upper semiconductor chip (because Yeh is taking the same semiconductor chip and stacking it multiple times, the upper dielectric layer would be positioned between the first upper semiconductor chip and the lower dielectric layer as seen in Yeh Fig. 15 and 19.); and a connection structure (see Yeh Fig. 19, vias 120/415 and contact pad 441; Yeh col. 12, ln. 8 and 17-18) that penetrates the upper dielectric layer and the lower dielectric layer (see Yeh Fig. 19), the connection structure being connected to the first upper semiconductor chip and the second upper semiconductor chip (see Yeh Fig. 19).
Yeh does not teach that a width of the upper dielectric layer is less than a width of the lower dielectric layer in a first direction, wherein the first direction is parallel to the top surface of the lower semiconductor chip.
Pendse teaches a dielectric layer (see Pendse Fig. 2, material 160, where it “comprises an encapsulating resin”; see Pendse [0034]) whose sidewalls are slanted (see Pendse Fig. 2).
By modifying the sidewalls of the upper dielectric layer of Yeh to be slanted as taught by Pendse, the combined device of Yeh and Pendse teaches that a width of the upper dielectric layer is less (because of the slanted walls taught by Pendse, the width of the upper dielectric layer would be less than the bottom surface of the semiconductor chips.) than a width (the width of the lower dielectric layer is the same as the bottom surface of the semiconductor chips as seen in Yeh Fig. 19.) of the lower dielectric layer in a first direction (see Image G), wherein the first direction is parallel to the top surface of the lower semiconductor chip (see Image G).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the upper dielectric layer of Yeh with the slanted sidewalls of Pendse in order to improve protection and reduce stress along the edges of the layer.
With regards to claim 13, Yeh and Pendse teach the semiconductor package of claim 12, wherein the lower dielectric layer (see Yeh Fig. 19, die attach film 496) contacts the upper dielectric layer (see Yeh Fig. 19, insulating layer 498).
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh and Pendse, in view of Fukazawa (Pub. No.: US 20060138629 A1).
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Image H: close up of Yeh Fig. 19, showcasing top and bottom surfaces of chip substrate.
With regards to claim 14, Yeh and Pendse teach the semiconductor package of claim 12, wherein each of the first upper semiconductor chip (see Yeh Fig. 15, thinned die 223) and the second upper semiconductor chip (see Yeh Fig. 15, thinned die 233) has a top surface (see Image G) and a bottom surface (see Image G) that are opposite to each other (see Image G), wherein the top surface of the first upper semiconductor chip faces the bottom surface of the second upper semiconductor chip (see Image G), wherein the lower dielectric layer (see Yeh Fig. 19, die attach film 496) and the upper dielectric layer (see Yeh Fig. 19, insulating layer 498) are between the top surface of the first upper semiconductor chip and the second upper semiconductor chip (see Yeh Fig. 19), and wherein each of the first upper semiconductor chip and the second upper semiconductor chip comprises: an upper semiconductor substrate (see Yeh Fig. 19, substrate 115; Yeh col. 3, ln. 36) on the top surface of a corresponding one of the first upper semiconductor chip and the second upper semiconductor chip (see Yeh Fig. 19); and an upper circuit layer (see Yeh Fig. 19, connector layer 495; Yeh col. 12, ln. 29) on the bottom surface of a corresponding one of the first upper semiconductor chip and the second upper semiconductor chip (see Yeh Fig. 19), a top surface (see Image H) of the upper semiconductor substrate corresponds to the top surface of a corresponding one of the first upper semiconductor chip and the second upper semiconductor chip (see Image H), a bottom surface (see Image H) of the upper semiconductor substrate is on the upper circuit layer (see Image H).
Yeh and Pendse do not teach a width of the top surface of the upper semiconductor substrate is less than a width of the bottom surface of the upper semiconductor substrate in the first direction.
Fukazawa teaches a width (see Image E) of a top surface (see Fukazawa Fig. 9A, rear surface 10B; Fukazawa [0096]) of an upper semiconductor substrate (see Fukazawa Fig. 9A, semiconductor chip 10; Fukazawa [0096]) is less than a width (see Image E) of a bottom surface (see Fukazawa Fig. 9A, active surface 10A; Fukazawa [0096]) of the upper semiconductor substrate in a first direction (see Image E, x-direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor chips of Yeh and Pendse with the rounded corners taught by Fukazawa in order to relieve stress concentration at the edges of the chips (see Fukazawa [0098]: “Therefore the curved sections 21 relieve stress concentration at the edges 23b of the rear surface 10B of the semiconductor chip 10.”).
With regards to claim 15, Yeh, Pendse, and Fukazawa teach the semiconductor package of claim 14, wherein a width of a top surface (because the upper dielectric layer has slanted sidewalls, the top surface of it would be less than the bottom surface of it.) of the upper dielectric layer (see Yeh Fig. 19, insulating layer 498) is less than the width of the top surface (the width of the bottom surface of the upper dielectric layer is the same as the top surface of the upper semiconductor substrate it is deposited on. So, the top surface of the upper dielectric layer is less than the top surface of the upper semiconductor substrate.) of the upper semiconductor substrate (see Yeh Fig. 19, substrate 115) in the first direction (see Image G, x-direction).
With regards to claim 16, Yeh, Pendse, and Fukazawa teach the semiconductor package of claim 14, wherein a width of a top surface (because the upper dielectric layer has slanted sidewalls, the top surface of it would be less than the bottom surface of it.) of the upper dielectric layer (see Yeh Fig. 19, insulating layer 498) is less than the width of the bottom surface (the width of the bottom surface of the upper dielectric layer is the same as the top surface of the upper semiconductor substrate it is deposited on. Because the top surface of the upper semiconductor substrate is less than the bottom surface of the upper semiconductor substrate, the top surface of the upper dielectric layer would also be less than the bottom surface of the upper semiconductor substrate.)of the upper semiconductor substrate (see Yeh Fig. 19, substrate 115) in the first direction (see Image G, x-direction).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (Pub. No.: US 20230137691 A1), hereinafter as Lai, in view of Takeuchi et al. (Pub. No.: US 20120080219 A1), hereinafter as Takeuchi.
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Image I: closeup of Takeuchi Fig. 8, showcasing bottom surface of upper semiconductor chip.
With regards to claim 17, Lai teaches a semiconductor package, comprising: a lower semiconductor chip (see Lai Fig. 6, package substrate 200; Lai [0079] and [0102]: “Referring to FIG. 6, the fifth alternate embodiment structure illustrated may be formed in a similar manner according to the processes and techniques described with reference to FIGS. 1A-1L.”) comprising a top surface (see Image A) and a bottom surface (see Image A) that are opposite to each other (see Image A); an upper semiconductor chip (see Lai Fig. 6, hybrid interposer 601; Lai [0102]) on the top surface of the lower semiconductor chip (see Lai Fig. 6) and having a bottom surface (see Image A) and a top surface (see Image A) that are opposite to each other (see Image A); a dielectric layer (see Lai Fig. 6, underfill material portion 292; Lai [0081] and [0102]) between the top surface of the lower semiconductor chip and the bottom surface of the upper semiconductor chip (see Lai Fig. 6); an upper dielectric layer (see Lai Fig. 6, underfill material portion 492; Lai [0068] and [0102]) on the top surface of the upper semiconductor chip (see Lai Fig. 6); and a connection structure (see Lai Fig. 6, solder material portions 450 and package-side bonding pads 448; Lai [0077], [0074], and [0102]) that penetrates the dielectric layer (see Lai Fig. 6), the connection structure being connected to the lower semiconductor chip and the upper semiconductor chip (see Lai Fig. 6), wherein a lateral surface (see Image D) of the upper dielectric layer is rounded (see Lai Fig. 6), wherein a width (see Image B) of the upper dielectric layer in a first direction (see Image B, x-direction) decreases (because the corners of the upper dielectric layer are rounded) as a distance from the lower semiconductor chip along a direction (see Image B, y-direction) perpendicular to the top surface of the lower semiconductor chip increases (see Image B), and wherein the first direction is parallel to the top surface of the lower semiconductor chip (see Image B).
Lai does not teach a lower dielectric layer between the dielectric layer and the bottom surface of the upper semiconductor chip; and that the connection structure penetrates the dielectric layer and the lower dielectric layer.
Takeuchi teaches a lower dielectric layer (see Takeuchi Fig. 8, underfill resin 50; Takeuchi [0022]) between a dielectric layer (see Takeuchi Fig. 8, adhesive 40; Takeuchi [0022]) and a bottom surface (see Image I) of an upper semiconductor chip (see Takeuchi Fig. 8, semiconductor chip 20; Takeuchi [0022]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device of Lai to have both a dielectric layer and a lower dielectric layer as taught by Takeuchi in order to reduce the amount of air trapped during manufacturing process (see Takeuchi [0054]: “If the entire upper surface of the circuit board 10 is covered with the adhesive 40, unevenness on the circuit board 10 is reduced compared with a configuration in which the upper surface of the circuit board 10 is partially covered with the adhesive 40. With this configuration, trapping of air during the supply of the uncured underfill resin 50 less often occurs. Thus formation of voids in the gap between the circuit board 10 and the semiconductor chip 20 can be further reduced.”).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lai and Takeuchi, in view of Fukazawa (Pub. No.: US 20060138629 A1).
With regards to claim 18, Lai and Takeuchi teach the semiconductor package of claim 17, wherein the upper semiconductor chip (see Lai Fig. 6, hybrid interposer 601) comprises: an upper circuit layer (see Lai Fig. 6, organic structure 470; Lai [0061] and [0102]) on the bottom surface (see Image A) of the upper semiconductor chip (see Lai Fig. 6); and an upper semiconductor substrate (see Lai Fig. 6, molding material layer 473; Lai [0046] and [0102]) on the top surface (see Image A) of the upper semiconductor chip (see Lai Fig. 6), wherein a top surface (see Image A) of the upper semiconductor substrate corresponds to the top surface of the upper semiconductor chip (see Lai Fig. 6), wherein a bottom surface (see Image A) of the upper semiconductor substrate is on the upper circuit layer (see Lai Fig. 6).
Lai and Takeuchi do not teach that a width of the top surface of the upper semiconductor substrate is less than a width of the bottom surface of the upper semiconductor substrate in the first direction.
Fukazawa teaches that a width (see Image E) of a top surface (see Fukazawa Fig. 9A, rear surface 10B; Fukazawa [0096]) of an upper semiconductor substrate (see Fukazawa Fig. 9A, semiconductor chip 10; Fukazawa [0096]) is less than a width (see Image E) of a bottom surface (see Fukazawa Fig. 9A, active surface 10A; Fukazawa [0096]) of the upper semiconductor substrate in a first direction (see Image E, x-direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor chips of Lai and Takeuchi with the rounded corners taught by Fukazawa in order to relieve stress concentration at the edges of the chips (see Fukazawa [0098]: “Therefore the curved sections 21 relieve stress concentration at the edges 23b of the rear surface 10B of the semiconductor chip 10.”).
With regards to claim 19, Lai, Takeuchi, and Fukazawa teach the semiconductor package of claim 18, wherein a lateral surface (see Image D) of the upper semiconductor substrate (see Lai Fig. 6, molding material layer 473) is rounded (see Fukazawa Fig. 9A, curved sections 21; Fukazawa [0098]), and wherein the width (see Image B) of the upper semiconductor substrate is greater than the width (see Image B) of the upper dielectric layer (see Lai Fig. 6, underfill material portion 492) in the first direction (see Image B, x-direction).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lai, Takeuchi, and Fukazawa, in view of Pendse (Pub. No.: US 20080136003 A1).
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Image J: closeup of Pendse Fig. 5, showcasing top and bottom surfaces of layers.
With regards to claim 20, Lai, Takeuchi, and Fukazawa teach the semiconductor package of claim 18, wherein a bottom surface (see Image D) of the upper dielectric layer (see Lai Fig. 6, underfill material portion 492) contacts the top surface (see Image A) of the upper semiconductor substrate (see Lai Fig. 6, molding material layer 473).
Lai, Takeuchi, and Fukazawa do not teach that a width of the bottom surface of the upper dielectric layer is equal to the width of the top surface of the upper semiconductor substrate in the first direction.
Pendse teaches that a width of a bottom surface (see Image J) of a dielectric layer (see Pendse Fig. 2, material 160, where it “comprises an encapsulating resin”; see Pendse [0034]) is equal to a width of a top surface (see Image J, where the bottom surface the dielectric layer is also the top surface of the semiconductor substrate.) of a semiconductor substrate (see Pendse Fig. 2, base substrate 130; Pendse [0031]) in a first direction (see Image J, x-direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the upper dielectric layer of Lai, Takeuchi, and Fukazawa with the bottom surface width taught by Pendse in order to fully insulate the two semiconductor chips from each other.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Seong et al. (Pub. No.: US 20250201794 A1)
Seong et al. (Pub. No.: US 20250096218 A1)
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/E.T.B./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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