Prosecution Insights
Last updated: April 19, 2026
Application No. 18/771,046

DEVICE ARRAY ANALYSIS METHOD AND ANALYSIS APPARATUS THEREFOR

Non-Final OA §102
Filed
Jul 12, 2024
Examiner
FOX, DANIELLE A
Art Unit
2884
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Dongguk University Industry-Academic Cooperation Foundation
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
96%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
590 granted / 711 resolved
+15.0% vs TC avg
Moderate +13% lift
Without
With
+13.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
29 currently pending
Career history
740
Total Applications
across all art units

Statute-Specific Performance

§101
2.9%
-37.1% vs TC avg
§103
39.6%
-0.4% vs TC avg
§102
41.4%
+1.4% vs TC avg
§112
10.4%
-29.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 711 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 6-9, 15-17, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0330909 (Koldiaev). PNG media_image1.png 218 483 media_image1.png Greyscale Regarding claim 1, Koldiaev disclose a device array analysis method comprising: manufacturing a device array including one or more devices (2020); supplying a first light signal (2012) to the device array (2020); obtaining an image (via 2048) by detecting a second light signal (2014) emitted from the device array (2020); and analyzing the image to determine whether the device array is normal or defective (Fig. 7-9, wherein defects 2402 are portrayed on map 2400). Regarding claim 2, Koldiaev disclose the device array analysis method of claim 1, further comprising removing interference between different second light signals emitted from the device array ([0050], [0114]). Regarding claim 3, Koldiaev disclose the device array analysis method of claim 1, wherein the analyzing of the image to determine whether the device array is normal or defective comprises calculating at least one of a threshold voltage of the one or more devices and a defect density of the device array, based on intensity of the second light signal of the image (Fig. 9). Regarding claim 4, Koldiaev disclose the device array analysis method of claim 1, wherein the obtaining of the image comprises obtaining an image of each of a plurality of devices of the device array, and/or obtaining an image of a device located at a specific position in the device array (Fig. 6-9). Regarding claim 6, Koldiaev disclose the device array analysis method of claim 1, wherein the obtaining of the image comprises: executing an algorithm for combining spot spectra of the device array; and/or obtaining an image for each region in the device array (Fig. 9). Regarding claim 7, Koldiaev disclose the device array analysis method of claim 1, wherein a frequency of the second light signal is twice a frequency of the first light signal ([0104], SHG signal). Regarding claim 8, Koldiaev disclose the device array analysis method of claim 1, wherein the one or more devices comprise at least one of a semiconductor device and a display device (2020). Regarding claim 9, Koldiaev disclose a device array analysis method comprising: manufacturing a device array including one or more devices (2020); supplying a first light signal (2012) to the device array (2020); obtaining an image (via 2048) by detecting a second light signal (2014) emitted from the device array (2020); and analyzing the image to determine whether the device array is normal or defective (Fig. 7-9, wherein defects 2402 are portrayed on map 2400); and when it is determined that the device array is defective, performing a subsequent process on the defective device array [0100], [0116], [0153], [0176]). Regarding claim 15, Koldiaev disclose a device array analysis apparatus comprising: a light source (2010) configured to generate and emit a first light signal (2012); a sampler (2020) configured to receive the first light signal (2012) and emit a second light signal (2014); a detector (2040) configured to detect and image the second light signal to form an image (via 2048, see Fig. 9); and an analyzer configured to analyze the image ([0125]-[0126]), wherein the image includes information about the second light signal emitted from a device array including one or more devices (2020). Regarding claim 16, Koldiaev disclose the device array analysis apparatus of claim 15, further comprising a beam shaper configured to shape the first light signal to have a constant intensity according to space (Fig. 6C). Regarding claim 17, Koldiaev disclose the device array analysis apparatus of claim 15, further comprising a first beam expander configured to adjust a diameter of the first light signal (Fig. 6C). Regarding claim 20, Koldiaev disclose the device array analysis apparatus of claim 15, further comprising an interference remover configured to remove interference between different second light signals emitted from the device array ([0050], [0114]). Allowable Subject Matter Claims 5, 10-14, and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 5, Koldiaev disclose the device array analysis method of claim 1, but fail to teach the details of wherein the determining of whether the device array is normal or defective comprises: when the device array includes only normal devices, proceeding to an end operation; and when the device array includes defective devices, modifying a manufacturing process condition of the device array. Regarding claim 10, Koldiaev disclose the device array analysis method of claim 9, but fail to teach the details of wherein the performing of the subsequent process on the defective device array comprises: searching for the defective device array; moving a stage; adjusting intensity of a third light signal supplied to the defective device array; and determining whether the defective device array is normal or defective. Claims 11-14 depend on claim 10. Regarding claim 18, Koldiaev disclose the device array analysis apparatus of claim 15, but fail to teach the details of further comprising a healer configured to heal the device array which is defective and make a third light signal be incident on the defective device array. Claim 19 depends on claim 18. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANI FOX whose telephone number is (571)272-3513. The examiner can normally be reached M-F: 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Makiya can be reached at 571-272-2273. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANI FOX/Primary Examiner, Art Unit 2884
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Prosecution Timeline

Jul 12, 2024
Application Filed
Jan 28, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
96%
With Interview (+13.3%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 711 resolved cases by this examiner. Grant probability derived from career allow rate.

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