DETAILED ACTION
This action is responsive to the following: the amendments and remarks made in amendment filed on June 25, 2026.
Claims 1-20 are pending. Claims 1, 13, and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed on June 25, 2026, have been entered. Claims 1-20 remain pending.
Claim Interpretation
Claim 3 contains the limitations “a first portion of dielectric material is configured to breakdown” and “a second portion of the dielectric material is configured to break down”. It is not clear from the claims or specification what is meant by a “portion” of the dielectric material. As best understood from the description in the specification these are not portions of dielectric material that are both associated with a single antifuse cell, but rather each portion is associated with a separate antifuse cell. Thus, this claim is interpreted to mean that when the first switching component is activated the dielectric material breaks down in the first cell and when the second switching component is activated the dielectric material breaks down in the second cell.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al (US 20180053767 A1).
Regarding Independent Claim 13, Cheng teaches an apparatus (Fig. 4: 400), comprising:
an antifuse (FIg. 2A: T2) comprising a channel (FIg. 2A: 150) extending in a vertical direction and a dielectric material (FIg. 2A: 180) disposed on at least one sidewall of the channel;
a digit line (Fig. 4: BL0) of a plurality of digit lines (Fig. 4: BL0, BL1) extending in a first horizontal direction, the digit line coupled with a terminal below the antifuse (FIg. 2A: T2); and
a word line (Fig. 4: WL0) of a plurality of word lines (Fig. 4: WL0, WL1) extending in a second horizontal direction perpendicular to the first horizontal direction and in contact (FIg. 2A: 190) with the dielectric material (FIg. 2A: 180) of the antifuse (FIg. 2A: T2).
Regarding Claim 14, Cheng teaches the limitations of Claim 13. Cheng further teaches a digit line decoder (Fig. 4: 420) coupled with the plurality of digit lines and configured to select the digit line as part of an access operation for the antifuse (Fig. 4: 400); and
a word line decoder (para 68 “While not specifically shown in FIG. 4, the memory system 400 would further comprise row decoder circuitry, word line driver circuitry, and other control circuity to control activation of the word lines (WL0, WL1, . . . ).”) coupled with the plurality of word lines and configured to select the word line as part of the access operation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-12 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20200027924 A1) in view of Cheng et al (US 20180053767 A1).
Regarding Independent Claim 1, Yang teaches an apparatus (Fig. 7: 700), comprising:
a first layer (Fig. 6: 602) comprising a switching component (Fig. 6: 112) and a first access line (Fig. 6: WL) extending in a first horizontal direction configured to activate the switching component (Fig. 6: 112); and
a second layer (Fig. 6: 218) above the first layer in a vertical direction, the second layer comprising:
a dielectric material (Fig. 6: 108a) disposed on at least one sidewall of the channel, the channel above a first terminal (Fig. 6: 204a) coupled with the switching component (Fig. 6: 112); and
a second access line (Fig. 6: BL1) extending in a second horizontal direction perpendicular to the first horizontal direction and coupled with the dielectric material (fig. 8: 108a).
Yang fails to teach an antifuse.
Cheng teaches an antifuse (FIg. 2A: T2) with a channel extending (FIg. 2A: 150) in the vertical direction and a dielectric material (FIg. 2A: 180) disposed on at least one sidewall of the channel (FIg. 2A: 150), and
Cheng further teaches that “Antifuse devices are implemented in various OTP (one-time programmable) applications, such as a one-time programmable read-only memory (PROM), and programmable logic devices (PLDs) to configure logic circuits and create customized integrated circuit designs, one-time programmable read-only memory (PROM), etc.” (para 2) Thus it would be obvious to combine the density of an RRAM cell taught in yang where a channel with variable resistance is disposed above the cell transistor element and replacing the RRAM elements with antifuses for the one time programmable applications outlined in Cheng.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Cheng to the teachings of Yang in the same or in a similar field of endeavor. The substituted and/or combined features would perform the same functions that they would perform separately, and the simple substitution of the RRAM material for the antifuse material would have yielded predictable results to produce a memory cell disposed in two layers where the first layer contains a switching component and the second layer contains an antifuse component. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding Claim 4, Yang and Cheng teach the limitations of Claim 1. Yang further teaches a third layer (Fig. 6: 212) between the first layer (Fig. 6: 602) and the second layer (Fig. 6: 218), the third layer comprising a conductive plate coupling a terminal below the antifuse (Fig. 6: 102; Cheng Fig 1A: T2) with the switching component (Fig. 6: 112).
Regarding Claim 5, Yang and Cheng teach the limitations of Claim 4. Cheng further teaches a plurality of second antifuses (Fig. 4: T2, Cell 2), each second antifuse (Fig. 4: T2, Cell 2) of the plurality of second antifuses comprising a respective channel (Fig 1A: T2, 150) above a second terminal (FIg. 2A: 130) coupled with the switching component (FIg. 2A: T1) via the conductive plate (combined with Yang Fig. 6: 212) and a respective dielectric material (FIg. 2A: 180, T2) disposed on at least one respective sidewall of the respective channel (FIg. 2A: 150, T2).
Regarding Claim 6, Yang and Cheng teach the limitations of Claim 5. Cheng further teaches wherein the second access line (Fig. 4: BL1) is coupled with the respective dielectric material (FIg. 2A: 180) of each of a first subset of the plurality of second antifuses (Fig. 4: CELL 2, T2) and
Yang teaches a third access line (Fig. 7: SL1) extending in the second horizontal direction is coupled with the respective dielectric material (Fig. 108a) of each of a second subset of the plurality of second antifuses (Fig. 7: 102 combined with Cheng FIg. 2A: T2).
Regarding Claim 7, Yang and Cheng teach the limitations of Claim 4. Yang further teaches wherein the third layer (Fig. 6: 212) further comprises a second conductive plate (Fig. 6: 212; Fig 7: 102, BL2n-1, BL2n) adjacent to the conductive plate (Fig. 6: 212; Fig 7: 102, BL1, BL2), the second conductive plate (Fig. 6: 212; Fig 7: 102, BL2n-1, BL2n) coupling a terminal of a second (Fig. 6: 212; Fig 7: 102, BL2n-1, BL2n) antifuse (Cheng 1A: T2) with a second switching component ( Fig 7: 112, BL2n-1, BL2n, WL1).
Regarding Claim 8, Yang and Cheng teach the limitations of Claim 7. a third antifuse between the antifuse and the second antifuse, the third antifuse isolated from the conductive plate and the second conductive plate.
(Yang teaches 2n BL in Fig. 7, therefore one could assume there are bitlines between BL1 and BL2 and BL2n-1 and BL2 attached to programmable cells, which when applying the teachings of Cheng to the teachings of Yang are antifuses. Therefore, a third antifuse isolated from the conductive plates of the first two antifuses is understood to be between them)
Regarding Claim 9, Yang and Cheng teach the limitations of Claim 1. Yang further teaches wherein the switching component (Fig. 6: 112) comprises a first terminal (Fig. 6 204b) coupled with a ground voltage source (Fig. 8B: 804, 0V, selectline) and a second terminal (Fig. 6 204a) coupled with the first terminal of the channel (Fig. 6: 212).
Regarding Claim 10, Yang and Cheng teach the limitations of Claim 1. Yang further teaches a first decoder (Fig. 7: 704) coupled with the first access line (Fig. 7: WL1) and configured to apply a first voltage (Fig. 8B: 804, 0.8~1.4V, wordline) to the first access line (Fig. 7: WL1) to activate the switching component (Fig. 6: 112); and
a second decoder (Fig. 7: 706) coupled with the second access line (Fig. 7: BL1) and configured to apply a second voltage (Fig. 7: bitline1, 2.8V~3.6V, 804) to the second access line (Fig. 7: BL1).
Regarding Claim 11, Yang and Cheng teach the limitations of Claim 10. Cheng further teaches wherein the dielectric material (FIg. 2A: 180) is configured to break down based at least in part on activating the switching component and applying the second voltage to the second access line (para 57 “. In this regard, formation of the conductive channel of the vertical antifuse device T2 is achieved, at least in part, by the dielectric breakdown of the gate dielectric material of the high-k metal gate stack structure 180 caused by the application of a high-voltage pulse to the metal gate electrode 200 of the vertical antifuse device T2”).
Regarding Claim 12, Yang and Cheng teach the limitations of Claim 1. Yang further teaches wherein the switching component (Fig. 6: 112) comprises a complimentary metal-oxide semiconductor (CMOS) transistor (para 25 “wherein the control device 112 comprises a MOSFET”) within a substrate (Fig. 6: 202).
Regarding Independent Claim 18, Yang teaches an apparatus (Fig. 7: 700), comprising:
a first access line (fig. 7: SL1) extending in a first horizontal direction;
a transistor (Fig. 6: 112);
a second access line (fig. 7: WL1) extending in a second horizontal direction perpendicular to the first horizontal direction and coupled with the channel region (Fig. 6: 204c, 204d) of the transistor;
a dielectric material (Fig. 5: 108a) above the second terminal of the transistor (Fig. 6: 204a); and
a conductive contact (Fig. 5: 502a) coupled with the dielectric material (Fig. 5: 108a).
Yang fails to teach a vertical transistor.
Cheng teaches a vertical transistor (FIg. 2A: T1) above a first terminal (FIg. 2A: 130) coupled with and above the first access line (Fig. 4: BL0) in a vertical direction, a channel region (FIg. 2A: 150) above the first terminal (FIg. 2A: 130) and a second terminal (FIg. 2A: 260) above the channel region (FIg. 2A: 150).
Vertical transistors are denser than planar MOSFETs thus denser layouts could be achieved by using a vertical transistor in place of a planar transistor would allow for a denser array of cells.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Cheng to the teachings of Yang to produce a memory cell with vertical transistor with a second terminal below dielectric material.
Regarding Claim 19, Yang and Cheng teach the limitations of Claim 18. Yang further teaches a third access line (Fig. 6: BL1) above the conductive contact (Fig. 6: 204b) and extending in the first horizontal direction, wherein the third access line (Fig. 6: BL1) is configured as a bit line for an array of memory cells above the vertical transistor.
Regarding Claim 20, Yang and Cheng teach the limitations of Claim 19. Yang further teaches wherein the dielectric material (Fig. 5: 108a) is configured to break down based at least in part on activating (Fig. 8B: 804, wordline, 0.8~1.4V) the vertical transistor using the second access line (Fig. 6: WL), applying a first voltage (Fig. 8B: 804, 0V, selectline) to the first access line (Fig. 1: SL), and applying a second voltage (Fig. 8B: 804, 2.8V~3.6V, Bitline 1) to the third access line (Fig. 6: BL1).
Allowable Subject Matter
Claims 2-3 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 would be allowable for teaching a semiconductor material extending from the channel of one antifuse to the channel of another antifuse. Cheng and Yang fail to teach such a material extending between programmable memory components. Therefore, this claim would be allowable if written in independent form.
Claim 3 would be allowable for being dependent on claim 2.
Claim 15 would be allowable for teaching applying voltages of the same magnitude but different voltages to access lines during the programming. Neither Cheng nor Yang teach applying voltages with different polarities. Therefore, this claim would be allowable if written in independent form.
Claims 16 and 17 would be allowable for being dependent on Claim 15.
Response to Arguments
Applicant's arguments filed June 25, 2026 have been fully considered but they are not persuasive.
For the rejection under 35 U.S.C. 103 of independent claims 1 applicant’s argument is directed solely the fact that there would be no motivation to replace RRAM with an antifuse.
Applicant’s first argument as to why this would be inappropriate is directed to use as an one-time programmable vs multi-time programmable memory. The number of time the array element would be used would be directed toward a method of operation or use and not the structure of the apparatus disclosed in the claims. As no mention is made of the number of times the cells are meant to be programmed in claim 1.
The examiner politely disagrees. RRAM and antifuses are both cells with well-known construction in the semiconductor memory art. Both RRAM and antifuses have memories that work by changing the resistive properties of layers of Dielectric materials.
Both of the cited references, Cheng and Yang, are within the semiconductor field of endeavor to include semiconductor memory and include specific layers to perform the desired functions. Cheng provides further support for the combination/ substitution in paragraph 0014: It is to be understood that the methods discussed herein for fabricating vertical FET device and vertical antifuse structures can be incorporated within semiconductor processing flows for fabricating other types of semiconductor devices and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc.
A cursory search also provided hundreds of sources where one-time programmable circuits were easily substituted with RRAM circuits to provide either a one-time programming or reprogramming capability. Just two examples will be listed here to exhibit the well-known substitution and/or combination of antifuses with RRAM in semiconductor memories:
Chung (U.S. Patent Application Publication 20200219574) paragraph 0230 teaches: “The programmable resistive element, such as 181 in FIG. 6(c01), can be a One-Time Programmable (OTP), Multiple-Time Programmable (MTP), embedded flash, or emerging memories, such as PCM, RRAM, or MRAM, etc.”
Hsu (U.S. Patent Application Publication 20210296360) paragraph 0084 teaches: “Also included in the array 800 is a memory storage layer 805. Depending on the type of memory and technology, the memory-storage layer 805 can be a charge-trapping layer or floating gates for NAND flash memory, variable resistive layer such as HfOx, TaOx, TiOx, PtOx, WOx, AlOx, CuOx, etc. for RRAM, ferroelectric layer for FRAM, magneto-resistive layers for MRAM, phase-change material such as chalcogenide for PCM, dielectric layer for anti-fuse OTP, or other suitable memory layer.”
Thus the substitution / combination of Cheng and Yang clearly meet the KSR rational because the substitution of the antifuse for the RRAM material would have yielded predictable results. The further addition of Chung and Hsu in this office action further buttress the KSR rational by explicitly showing that the antifuse and RRAM are routinely cited as interchangeable circuit devices in the semiconductor memory art.
Applicant’s next argument is directed to the structural aspects of Yang’s RRAM cells are fabricated using Back end of line (BEOL) of processes while Cheng’s are only fabricated by front end of line (FEOL) processes and that this would make the fabrication impossible. However, applicant seems to be making several inferences in the fabrication process to come to this conclusion. For instance, Yang refers to BEOL three times and only as descriptor of the metal stack not as a descriptor of the overall method of fabricating every component of the apparatus disclosed. It’s well understood by those of ordinary skill in the art that the metal stack is typically formed as part of the BEOL fabrication process and thus the use of BEOL as descriptor is limited to the metal stack and not every component of semiconductor device. There is no reason to assume other components of the device disclosed in Yang aren’t formed as part of the FEOL fabrication process. Further there is no reason to think that if a cell didn’t require metal components, that the BEOL parts of fabrication wouldn’t be omitted.
The final argument as to why the combination is improper is that the architecture of an RRAM device is incompatible with antifuse. However, nearly of applicant’s own limitations for an antifuse device map onto the architecture of Yang. Therefore, the argument is not persuasive as Yang discloses many of the same limitations as applicant.
For these reasons the arguments set forth with respect to claim 1 are not persuasive and the rejection under 35 U.S.C. 103 is maintained.
For the rejection under 35 U.S.C. 103 of independent claims 18 applicant’s argument is directed solely the fact that for “similar reasons” as claim 1 that the rejection was improper. However, the rationale to combine Yang and Cheng for claim 18 is substantially different for claim 18 than claim 1. Applicant’s argument is therefore unpersuasive with respect to claim 18 and the rejection of claim 18 under 35 U.S.C. 103 is maintained.
With respect to the rejection under 35 U.S.C. 102 of claim 13 applicant has asserted that Figures 1A/1B are not related to Figure 4, because Figure 4 is related to Figures 2A/2B. The examiner notes that Cheng et al. explain that Figures 1A/1B are similar to Figure 2A/2B except for the upper source drain regions 230 are formed on all fins 150 (see para. 61), and thus the reliance upon Figures 1A/1B in the rejection is not materially different that what Figure 4 requires from Figures 2A/2B. The examiner updated the rejection, to align with applicant's acknowledgment that Figures 2A/2B are for Figure 4.
Applicant's assertion that Cheng does not describe first and second access lines extending horizontally and perpendicular to each other is not persuasive. Patent documents are written for and presumed to be understood by persons skilled in the art. see S3 Inc. v. Nvidia Corp. 259 F.3d 1364 (Fed. Cir. 2001). Here, Cheng's illustration in Figure 4 is sufficient to demonstrate the access line (BLx and WLy) extend horizontally and perpendicular to each other, because persons skilled in the memory art would understand the bit lines are columns and word line are rows, typically arranging them perpendicular to each other unless stated otherwise in a disclosure.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/Donald HB Braswell/Primary Examiner, Art Unit 2825
