DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 11-13, 16-18, 21-25 and 27-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeng (US 2018/0068978) in view of Park (US 2014/0361428).
Regarding claim 1, Jeng discloses a module comprising:
a first wiring board (70, fig. 10);
a first component (50, fig. 10) that is an electrooptical component mounted on the first wiring board (para. 66);
a second wiring board (20, fig. 10) overlapping the first wiring board (see fig. 10);
a second component (66, fig. 10) that is an integrated circuit component mounted on the second wiring board (para. 39); and
a connecting member (36, fig. 10) disposed between the first wiring board and the second wiring board (see fig. 10), the connecting member being soldered to the first wiring board and the second wiring board (para. 31; wherein chips are interconnected through RDLs), the connecting member electrically connecting the first wiring board to the second wiring board (para. 31),
wherein the first wiring board (70, fig. 10) is located between the first component (50, fig. 10) and the second writing board (20, fig. 10) in a direction perpendicular to a principal surface of the first component (see fig. 10).
Jeng fails to disclose an air gap between chips.
Park discloses an air gap (260 in fig. 4) provided between the first component (220 in fig. 4) and the second component (230 in fig. 4 and para. 66, 68; wherein the air gap is used to exhaust heat).
When the invention was made (pre-AIA ) or before the effective filing date of the claimed invention (AIA ), it would have been obvious to one of ordinary skill in the art to include the teachings of Park in the device of Jeng. The motivation for doing so would have been to add an air gap between chips to dissipate heat from the chips (Park; para. 66, 68; further wherein air gaps are used conventionally to avoid having chips overheat, making the chipset more durable).
Regarding claim 2, Jeng discloses wherein the second wiring board (20, fig. 10) is provided between the first wiring board (70, fig. 10 and the second component (see 66 in fig. 10).
Regarding claim 3, Jeng discloses wherein the second component overlaps the first component in a direction perpendicular to a principal surface of the first component (see fig. 10).
Regarding claim 4, Jeng discloses further comprising a third component (30, fig. 10) mounted on the first wiring board (see fig. 3 and fig. 10), wherein the third component is provided between the first wiring board and the second wiring board (see fig. 3 and fig. 10).
Regarding claim 5, Jeng discloses wherein the third component overlaps the first component in a direction perpendicular to a principal surface of the first component (see fig. 10).
Regarding claim 6, Jeng discloses further comprising a fourth component (see smaller 30 in fig. 10) mounted on the second wiring board (see fig. 10), wherein the second wiring board is provided between the first wiring board and the fourth component (see fig. 10).
Regarding claim 7, Jeng discloses wherein the fourth component is a capacitor or an inductor (para. 30).
Regarding claim 11, Jeng discloses wherein the first wiring board includes a resin substrate (see organic insulative material in para. 28) and a first conductor layer, a second conductor layer, a third conductor layer, and a fourth conductor layer (para, 48; wherein redistribution layer 70 has several conductive layers 72, including e.g. four conductive layers) arranged at interval from each other in a thickness direction of the first wiring board (see fig. 4F and para. 48), the second conductor layer and the third conductor layer are disposed between the first conductor layer and the fourth conductor layer (see fig. 4F and para. 48), and a part of the third conductor layer overlaps the first component (50, fig. 10) in the direction perpendicular to the principal surface of the first component (see fig. 10 and para. 48).
Regarding claim 12, Jeng discloses further comprising a lid (90, fig. 10) fixed to the first wiring board (fig. 10), wherein the first component is disposed between the lid and the first wiring board in the direction perpendicular to the principal surface of the fist component (fig. 10), and wherein the second component is electrically connected to the first component via the connecting member (see the connection path between the first and second components in fig. 10).
Regarding claim 13, Jeng discloses wherein the third component is a memory (see SOC in para. 30, wherein a SOC includes a memory).
Regarding claim 14, Jeng discloses wherein the connecting member (36, fig. 10) includes a plurality of conductor portions (36C in fig. 10), a certain conductor portion among a plurality of conductor portions is soldered to the first wiring board with a first solder (C2 in fig. 10 and para. 31) and is soldered to the second wiring board with a second solder (C2 in fig. 10 and para. 31), and the first solder and the second solder are separate from each other (see fig. 10).
Regarding claim 16, Jeng discloses wherein the first component is electrically connected to the first wiring board by wire (51, fig. 10) bonding (para. 62, 35) to the fist component and the fist wiring board (see fig. 10 and para .35, 20), and the second component is soldered to the second wiring board (fig. 10 and para. 20).
Regarding claim 17, Jeng discloses wherein the second component supplies electric power to the first component (para. 39).
Regarding claim 18, Jeng discloses an apparatus (see semiconductor device in para. 2) comprising the module and a casing (90, fig. 10) accommodating the module.
Regarding claim 21, Jeng discloses wherein the first solder and the second solder are solder fillets (para. 30, 20; wherein conductive bumps are solder).
Regarding claim 22, Jeng discloses wherein the third component is a capacitor (para. 30).
Regarding claim 23, Jeng discloses wherein the third component is an integrated circuit component (para. 30).
Regarding claim 24, Jeng discloses wherein the third component stores data input to the first component (para. 30).
Regarding claim 25, Jeng discloses wherein the third component supplies power to the first component (para. 30).
Regarding claim 27, Jeng discloses Jeng discloses further comprising a fifth component (see right 30 in fig. 10) mounted on the second wiring board (20, fig. 10), wherein the fifth component is provided between the first wiring board and the second wiring board (see fig. 10).
Regarding claim 28, Jeng discloses wherein the fifth component is a memory, a processor, or a controller (para. 30).
Regarding claim 29, Jeng discloses further comprising a sixth component (see left 30 in fig. 10) mounted on the second wiring board (see fig. 10), wherein the sixth component is provided between the first wiring board and the second wiring board (see fig. 10), and the fifth component has a greater height than the sixth component in the direction perpendicular to the principal surface of the first component (see fig. 10).
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeng in view of Tsai (US 2022/0257732).
Regarding claim 8, Jeng fails to discloses a third wiring board.
Tsai discloses further comprising a third wiring board (33, fig. 3) soldered to the first wiring board or the second wiring (23, fig. 3) board (para. 78).
When the invention was made (pre-AIA ) or before the effective filing date of the claimed invention (AIA ), it would have been obvious to one of ordinary skill in the art to include the teachings of Tsai in the device of Jeng. The motivation for doing so would have been to connect three or more integrated circuits to three or more RDLs (para. 78) based on the dimensions of a chip. Wherein having more than two RDLs is known.
Regarding claim 9, Tsai discloses wherein the third wiring board is a flexible wiring board (para. 27; wherein the RDL is thin and is made up of wire traces and dielectric layers, resulting in the RDL being flexible).
Regarding claim 10, Tsai discloses wherein the second wiring board (23, fig. 3) is provided between the third wiring board (33, fig. 3) and the first wiring board (13, fig. 3).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeng in view of Cho (US 2021/0028217).
Regarding claim 19, Jeng fails to disclose a drive unit.
Cho discloses further comprising a drive unit that mechanically actuates the module in the casing (para. 39, 3; wherein the image sensor is driven in the camera).
When the invention was made (pre-AIA ) or before the effective filing date of the claimed invention (AIA ), it would have been obvious to one of ordinary skill in the art to include the teachings of Cho in the device of Jeng. The motivation for doing so would have been to have a usable camera made up of semiconductor packages (Cho; para. 3, 39). Ultimately creating greater usability for the user.
Regarding claim 20, Jeng discloses wherein the first component is an image sensor (para. 66, 36).
Jeng fails to discloses a display.
Cho discloses the apparatus further comprises a display module that displays an image picked up by the image sensor (para. 3).
The same rationale used to combine Cho with Zeng stated in claim 19 applies to claim 20.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeng in view of Horiuchi (US 2010/0065959).
Regarding claim 26, Jeng fails to disclose resin.
Horiuchi discloses wherein the connecting member has at least one of a part made of glass epoxy resin (40, fig. 4 and para. 68) and a part made of thermosetting resin (42, fig. 4 and para. 67).
When the invention was made (pre-AIA ) or before the effective filing date of the claimed invention (AIA ), it would have been obvious to one of ordinary skill in the art to include the teachings of Horiuchi in the device of Jeng. The motivation for doing so would have been to have insulating and protective materials surrounding the connecting device’s connections or vias for connections (Horiuchi; para. 67-68). Ultimately to reduce noise and connection interference.
Response to Arguments
Applicant’s arguments with respect to claims have been considered but are moot in view of new grounds of rejection. See new citations above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ROBIN J MISHLER/Primary Examiner, Art Unit 2628