DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsui et al. (US 2021/0305951), in view of Sasaki et al. (US 2020/0091874).
In regard to Claim 1:
Tsutsui discloses, in Figure 2, a power amplifier circuit comprising: a first transistor (Q1) on a semiconductor substrate (¶ 0021); a second transistor (Q50) that is on the semiconductor substrate (¶ 0021), that has a base (Q50 base) to which a first current (51) is supplied as a part of control currents (I cont), and that is configured to supply a bias current (Ief_pwr) based on the first current (51) to the first transistor (Q1); a third transistor (D52) that is on the semiconductor substrate (¶ 0021), that has a collector (D52 collector) to which a second current (D51 emitter current) is supplied as a part of the control currents (I cont), and that has an emitter (D52 emitter) configured to output a third current (D52 emitter current) based on the second current (D51 emitter current).
Tsutsui does not disclose a first metal part that is electrically connected to an emitter of the first transistor and that overlaps, in a plan view of the semiconductor substrate, a first layout region in which the first transistor is located; and a second metal part that is electrically connected to the emitter of the third transistor, wherein the third transistor overlaps the first metal part in the plan view.
Sasaki discloses, in Figure 7, a first metal part (52) that is electrically connected to an emitter of the first transistor (Q1 emitter) and that overlaps, in a plan view of the semiconductor substrate (50), a first layout region (42) in which the first transistor is located (Q1, ¶ 0074); and a second metal part (51) that is electrically connected to the emitter of the third transistor (Q3 emitter, ¶ 0066)), wherein the third transistor (Q3) overlaps the first metal part in the plan view (¶ 0073).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the metal parts and substrate taught by Sasaki with the amplifier taught by Tsutsui, since the temperature rise of the second transistor can be suppressed, and reduction of thermal stability in operation of the radio frequency power amplifier can be suppressed (Sasaki ¶ 0009).
In regard to Claim 4:
Sasaki further discloses, in Figure 7, the power amplifier circuit according to Claim 1, wherein a first wire electrically connecting the emitter of the third transistor (Q3) to the second metal part intersects a second wire electrically connected to a base of the first transistor (Q1, ¶ 0066).
In regard to Claim 6:
Tsutsui discloses, in Figure 2, the power amplifier circuit according to Claim 1, further comprising: a fifth transistor (D51) that is on the semiconductor substrate (¶ 0021), that has a collector and a base that are electrically connected to each other (D51 base and collector are connected together) and to which a fifth current (D51 collector current) is supplied as a part of the control currents (I cont), and that has an emitter (D51 emitter) configured to output the second current (D51 emitter current), wherein the collector and a base of the third transistor are electrically connected to each other (D52 base and collector are connected together).
Allowable Subject Matter
Claims 2-3 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to Claim 2:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
a fourth transistor that is on the semiconductor substrate, that has a collector to which the second current is supplied as a part of the control currents, that is connected in parallel with the third transistor, and that has an emitter configured to output a fourth current based on the second current, wherein the emitter of the fourth transistor is electrically connected to the second metal part.
Claims 7 and 8 are allowed.
In regard to Claim 7:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
a fourth transistor that is on the semiconductor substrate, that has a collector to which the second current is supplied, that is connected in parallel with the third transistor, and that has an emitter configured to output a fourth current based on the second current;
However, Tsutsui discloses, in Figure 2, a power amplifier circuit comprising: a first transistor (Q1) on a semiconductor substrate (¶ 0021); a second transistor (Q50) that is on the semiconductor substrate (¶ 0021), that has a base (Q50 base) to which a first current (51) is supplied as a part of control currents (I cont), and that is configured to supply a bias current (Ief_pwr) based on the first current (51) to the first transistor (Q1); a third transistor (D52) that is on the semiconductor substrate (¶ 0021), that has a collector (D52 collector) to which a second current (D51 emitter current) is supplied as a part of the control currents (I cont), and that has an emitter (D52 emitter) configured to output a third current (D52 emitter current) based on the second current (D51 emitter current).
Sasaki discloses, in Figure 7, a first metal part (52) that is electrically connected to an emitter of the first transistor (Q1 emitter) and that overlaps, in a plan view of the semiconductor substrate (50), a first layout region (42) in which the first transistor is located (Q1, ¶ 0074), wherein the emitter of the third transistor (Q3) is electrically connected to the first metal part (¶ 0073).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ishihara et al. (US 2019/0181816) discloses a power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
Hamano (US 2022/0293537) discloses a semiconductor device includes a gate electrode, first and second transistors arranged in a first direction, first and second drain wirings each connected to a corresponding drain region of the first and second transistors, first output wiring extending in a second direction orthogonal to the first direction and having one end connected to a portion adjacent to the second transistor of the first drain wiring, second output wiring extending in the second direction and having one end connected to a portion adjacent to the first transistor of the second drain wiring, third output wiring extending in the first direction and connected to the other end of the first output wiring and the other end of the second output wiring, and fourth output wiring connecting a center portion of the third output wiring to an output terminal.
Sasaki (US 2017/0170789) discloses a power amplifier circuit includes a first amplifier transistor and a bias circuit. The first amplifier transistor amplifies a first signal and outputs a second signal. The bias circuit supplies a bias voltage or a bias current to the first amplifier transistor. The first amplifier transistor includes plural unit transistors disposed in a substantially rectangular region. The bias circuit includes first and second bias transistors and first and second voltage supply circuits. The first and second bias transistors respectively supply first and second bias voltages or first and second bias currents to the bases of unit transistors of first and second groups.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
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