DETAILED ACTIONNotice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 - 7, 14 - 20 and 22 - 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ashida et al. (10,976,205, hereinafter Ashida). Regarding claim 1, Ashida discloses a method and apparatus comprising a force sensor chip 1 made of a cubic semiconductor single crystal (See Fig. 2), a measurement circuit 14 (See Fig. 7A), and a strain body 3 configured to undergo a body deformation in response to an external mechanical force applied to the strain body, wherein the strain body is mechanically coupled to the force sensor chip in such a way as to couple the external mechanical force to the force sensor chip to strain the force sensor chip mainly along a primary strain direction, wherein the force sensor chip comprises a first pair of piezo-resistive devices 15 integrated in the force sensor chip, wherein the first pair of piezo-resistive devices are arranged such that first current paths through the first pair of piezo-resistive devices are not parallel or anti-parallel to each other, and wherein the first pair of piezo-resistive devices are configured to respond differently to a strain along the primary strain direction, wherein the measurement circuit is configured to measure the external mechanical force based on one or more currents flowing through the first pair of piezo-resistive devices, and wherein each piezo-resistive device of the first pair of piezo-resistive devices has holes as majority carriers, and a 110 crystal direction of the force sensor chip is aligned within +/-35 to a line that is parallel to the primary strain direction (See Col. 3, lines 24 – 61 and Col. 4, lines 12 – 55). Regarding claim 2, the measurement circuit 14 is integrated in the force sensor chip 1 (See Fig. 7A). Regarding claim 3, a die attach layer 2 is configured to mechanically couple the force sensor chip to the strain body (See Col. 3, lines 51 - 62).
Regarding claim 4, either the <100> crystal directions or the <110> crystal directions of the force sensor chip are parallel or antiparallel to chip edges of the force sensor chip (See Fig. 7A).
Regarding claim 5, the first pair of piezo-resistive devices, which have holes as majority carriers, are p-doped devices (See Col. 4, lines 12 – 66).
Regarding claim 6, the first pair of piezo-resistive devices are piezo-resistors (See Col. 3, lines 58 – 62).
Regarding claim 7, the first pair of piezo-resistive devices 15 includes a first p-doped piezo-resistor configured to conduct a current in a 110 crystal direction of the force sensor chip, and a second p-doped piezo-resistor configured to conduct the current in a -110 crystal direction of the force sensor chip (See Col. 4, lines 12 – 66). Regarding claim 14, a second pair of piezo-resistive devices 15 is integrated in the force sensor chip, wherein the second pair of piezo-resistive devices are arranged such that second current paths through the second pair of piezo-resistive devices are not parallel or anti-parallel to each other, and wherein the second pair of piezo-resistive devices respond differently to the strain along the primary strain direction, the first pair of piezo-resistive devices and the second pair of piezo-resistive devices are coupled in a Wheatstone bridge configuration, wherein the first pair of piezo-resistive devices are a first pair of orthogonal lateral piezo-resistors, and wherein the second pair of piezo-resistive devices are a second pair of orthogonal lateral piezo-resistors (See Fig. 7A, See Col. 4, lines 2 - 12).
Regarding claim 15, the strain body 3 has a length dimension and a width dimension, and wherein the primary strain direction extends along the length dimension (See Fig. 1).
Regarding claim 16, the width dimension and the length dimension define a lateral chip plane of the force sensor chip, and wherein the first current paths are aligned with the lateral chip plane (See Fig. 1).
Regarding claim 17, the strain body is mechanically coupled to the force sensor chip in such a way that the body deformation causes a largest principal strain component of the force sensor chip to occur along the primary strain direction (See Fig. 2).
Regarding claim 18, the first current paths are parallel to a {100} plane of the force sensor chip (See Fig. 7A).
Regarding claim 19, the force sensor chip 1 is made of a cubic semiconductor single crystal; and the strain body 3 is configured to undergo a body deformation in response to an external mechanical force applied to the strain body, wherein the strain body is mechanically coupled to the force sensor chip in such a way as to couple the external mechanical force to the force sensor chip to strain the force sensor chip mainly along a primary strain direction, wherein the force sensor chip comprises a first pair of piezo-resistive devices 15 integrated in the force sensor chip, wherein the first pair of piezo-resistive devices are arranged such that first current paths through the first pair of piezo-resistive devices are not parallel or anti-parallel to each other, and wherein the first pair of piezo-resistive devices respond differently to a strain along the primary strain direction; a second pair of piezo-resistive devices 15 integrated in the force sensor chip, wherein the second pair of piezo-resistive devices are arranged such that second current paths through the second pair of piezo-resistive devices are not parallel or anti-parallel to each other, and wherein the second pair of piezo-resistive devices respond differently to the strain along the primary strain direction; and a measurement circuit 14 configured to measure the external mechanical force based on at least one of one or more first currents flowing through the first pair of piezo-resistive devices, or one or more second currents flowing through the second pair of piezo-resistive devices, wherein each piezo-resistive device of the first pair of piezo-resistive devices has holes as majority carriers, and each piezo-resistive device of the second pair of piezo-resistive devices has electrons as the majority carriers (See Col. 3, lines 24 – 61 and Col. 4, lines 12 – 55). Regarding claim 20, a <5,12,0> crystal direction of the force sensor chip is aligned within +/-35 to a line that is parallel to the primary strain direction (See Fig. 7A).
Regarding claim 22, the cubic semiconductor single crystal is configured to undergo a chip deformation based on an external mechanical force applied to a deformable member to which the force sensor chip is configured to be mechanically coupled in such a way as to couple the external mechanical force to the cubic semiconductor single crystal to strain the cubic semiconductor single crystal mainly along a primary strain direction; a first pair of piezo-resistive devices 15 are integrated in the cubic semiconductor single crystal, wherein the first pair of piezo-resistive devices are arranged such that first current paths through the first pair of piezo-resistive devices are not parallel or anti-parallel to each other, and wherein the first pair of piezo-resistive devices respond differently to an in-plane mechanical strain caused by a chip deformation of the cubic semiconductor single crystal; and a measurement circuit 14 is configured to measure the external mechanical force based on one or more currents flowing through the first pair of piezo-resistive devices, wherein each piezo-resistive device of the first pair of piezo-resistive devices has holes as majority carriers, and a <110> crystal direction of the cubic semiconductor single crystal is configured to be aligned within +/-35 to a line that is parallel to the primary strain direction (See Col. 3, lines 24 – 61 and Col. 4, lines 12 – 55). Regarding claim 23, a cubic semiconductor single crystal is configured to undergo a chip deformation based on an external mechanical force applied to a deformable member to which the force sensor chip is configured to be mechanically coupled in such a way as to couple the external mechanical force to the cubic semiconductor single crystal to strain the cubic semiconductor single crystal mainly along a primary strain direction; a first pair of piezo-resistive devices 15 are integrated in the cubic semiconductor single crystal, wherein the first pair of piezo-resistive devices are arranged such that first current paths through the first pair of piezo-resistive devices are not parallel or anti-parallel to each other, and wherein the first pair of piezo-resistive devices respond differently to an in-plane mechanical strain caused by the chip deformation; a second pair of piezo-resistive devices 15 are integrated in the cubic semiconductor single crystal, wherein the second pair of piezo-resistive devices are arranged such that second current paths through the second pair of piezo-resistive devices are not parallel or anti-parallel to each other, and wherein the second pair of piezo-resistive devices respond differently to the in-plane mechanical strain caused by a chip deformation of the cubic semiconductor single crystal; and a measurement circuit 14 is configured to measure the external mechanical force based on one or more first currents flowing through the first pair of piezo-resistive devices, and based on one or more second currents flowing through the second pair of piezo-resistive devices, wherein each piezo-resistive device of the first pair of piezo-resistive devices has holes as majority carriers, and wherein each piezo-resistive device of the second pair of piezo-resistive devices has electrons as the majority carriers (See Col. 3, lines 24 – 61 and Col. 4, lines 12 – 55). Regarding claim 24, a <5,12,0> crystal direction of the cubic semiconductor single crystal is configured to be aligned within +/-35 to a line that is parallel to the primary strain direction (See Fig. 7A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 – 11 are rejected under 35 U.S.C. 103 as being unpatentable over Ashida in view of Broce (3,609,252). Regarding claim 8, Ashida discloses a method and apparatus comprising a force sensor chip 1 made of a cubic semiconductor single crystal (See Fig. 2), a measurement circuit 14 (See Fig. 7A), and a strain body 3 configured to undergo a body deformation in response to an external mechanical force applied to the strain body, wherein the strain body is mechanically coupled to the force sensor chip in such a way as to couple the external mechanical force to the force sensor chip to strain the force sensor chip mainly along a primary strain direction, wherein the force sensor chip comprises a first pair of piezo-resistive devices 15 integrated in the force sensor chip, wherein the first pair of piezo-resistive devices are arranged such that first current paths through the first pair of piezo-resistive devices are not parallel or anti-parallel to each other, and wherein the first pair of piezo-resistive devices are configured to respond differently to a strain along the primary strain direction, wherein the measurement circuit is configured to measure the external mechanical force based on one or more currents flowing through the first pair of piezo-resistive devices, and wherein each piezo-resistive device of the first pair of piezo-resistive devices has holes as majority carriers, and a 110 crystal direction of the force sensor chip is aligned within +/-35 to a line that is parallel to the primary strain direction (See Col. 3, lines 24 – 61 and Col. 4, lines 12 – 55). Ashida fails to disclose that the first pair of piezo-resistive devices form a voltage divider configured to generate an electric potential at a node coupled between the first pair of piezo-resistive devices, and the measurement circuit is configured to measure the external mechanical force based on the electric potential. However, Broce discloses a method and apparatus comprising piezoresistive devices that form a voltage divider (See Fig. 12) configured to generate an electric potential at a node coupled between the first pair of piezo-resistive devices, and a measurement circuit that is configured to measure the external mechanical force based on the electric potential (See Col. 6, lines 63 – 75). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify Ashida according to the teachings of Broce for the purpose of, advantageously providing an improved device since this type of device permits the isolated coupling and mixing of an electrical signal with signals generated by stresses on the device (See Broce, Col. 1, lines 58 – 63).
Regarding claim 9, Ashida fails to disclose that the first pair of piezo-resistive devices are transistors. However, in Broce, the first pair of piezo-resistive devices are transistors (See Fig. 9, See Col. 8, lines 40 – 75 and Col. 9, lines 1 – 24). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify Ashida according to the teachings of Broce for the purpose of, advantageously providing an improved device since this type of device permits the isolated coupling and mixing of an electrical signal with signals generated by stresses on the device (See Broce, Col. 1, lines 58 – 63).
Regarding claim 10, Ashida fails to disclose that the first pair of piezo-resistive devices includes a first p-transistor configured to conduct a first current in a first <110> crystal direction of the force sensor chip, and a second p-transistor configured to conduct a second current in a direction orthogonal to the first <110> crystal direction of the force sensor chip, or wherein the first pair of piezo-resistive devices includes a first n-transistor configured to conduct the first current in a first <100> crystal direction of the force sensor chip, and a second n-transistor configured to conduct the second current in a direction orthogonal to the first <100> crystal direction of the force sensor chip. However, in Broce, the first pair of piezo-resistive devices includes a first p-transistor configured to conduct a first current in a first <110> crystal direction of the force sensor chip, and a second p-transistor configured to conduct a second current in a direction orthogonal to the first <110> crystal direction of the force sensor chip (See Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify Ashida according to the teachings of Broce for the purpose of, advantageously providing an improved device since this type of device permits the isolated coupling and mixing of an electrical signal with signals generated by stresses on the device (See Broce, Col. 1, lines 58 – 63).
Regarding claim 11, Ashida fails to disclose that the first pair of piezo-resistive devices includes a first p-transistor configured to conduct a first current, and a second p-transistor configured to conduct a second current, and wherein the measurement circuit is configured to determine the external mechanical force based on a ratio of the first current and the second current or based on a difference between the first current and the second current. However, in Broce, the first pair of piezo-resistive devices are transistors configured to conduct currents, wherein the measurement circuit is configured to determine the external mechanical force based on a ratio of the first current and the second current or based on a difference between the first current and the second current (See Fig. 9, See Col. 8, lines 40 – 75 and Col. 9, lines 1 – 24). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify Ashida according to the teachings of Broce for the purpose of, advantageously providing an improved device since this type of device permits the isolated coupling and mixing of an electrical signal with signals generated by stresses on the device (See Broce, Col. 1, lines 58 – 63).8. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ashida and Broce, as applied to claim 1 above, and further in view of Roewer et al. (2022/0404217, hereinafter Roewer). Regarding claim 12, Ashida and Broce fail to disclose that the first pair of piezo-resistive devices form a current mirror or a differential input pair. However, Roewer discloses an apparatus comprising a current mirror 18 that is formed from piezoresistive devices T1, T2 (See Pg. 2, Para. 0022 and Pg. 4, Para. 0034). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify Ashida and Broce according to the teachings of Roewer for the purpose of, advantageously providing an improved device since this type of device is space-saving, cost-efficient and temperature stable (See Roewer, Pg. 1, Para. 0005).9. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ashida in view of CN115265861. Regarding claim 13, Ashida fails to disclose a temperature-dependent power supply coupled to the first pair of piezo-resistive devices, wherein the temperature-dependent power supply is configured to provide a supply voltage or a supply current based on an ambient temperature such that a measure of the external mechanical force is compensated for the ambient temperature. However, CN115265861 discloses an apparatus comprising a temperature-dependent power supply 120 coupled to a first pair of piezo-resistive devices 130, wherein the temperature-dependent power supply is configured to provide a supply voltage or a supply current based on an ambient temperature such that a measure of the external mechanical force is compensated for the ambient temperature (See Fig. 1, See Pg. 6, Paras. 3 and 4 and Pg. 7, Paras. 1 and 2). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify Ashida and according to the teachings of CN115265861 for the purpose of, advantageously providing an improved device since this type of device improves the accuracy of pressure detection (See the Abstract of CN115265861).
11. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Ashida in view of Haroun et al. (11,653,568, hereinafter Haroun). Regarding claim 21, in Ashida, the force sensor chip 1 is made of a cubic semiconductor single crystal; and the strain body 3 is configured to undergo a body deformation in response to an external mechanical force applied to the strain body, wherein the strain body is mechanically coupled to the force sensor chip in such a way as to couple the external mechanical force to the force sensor chip to strain the force sensor chip mainly along a primary strain direction, wherein the force sensor chip comprises a first pair of piezo-resistive devices 15 integrated in the force sensor chip, wherein the first pair of piezo-resistive devices are arranged such that first current paths through the first pair of piezo-resistive devices are not parallel or anti-parallel to each other, and wherein the first pair of piezo-resistive devices respond differently to a strain along the primary strain direction; a second pair of piezo-resistive devices 15 integrated in the force sensor chip, wherein the second pair of piezo-resistive devices are arranged such that second current paths through the second pair of piezo-resistive devices are not parallel or anti-parallel to each other, and wherein the second pair of piezo-resistive devices respond differently to the strain along the primary strain direction; and a measurement circuit 14 configured to measure the external mechanical force based on at least one of one or more first currents flowing through the first pair of piezo-resistive devices, or one or more second currents flowing through the second pair of piezo-resistive devices, wherein each piezo-resistive device of the first pair of piezo-resistive devices has holes as majority carriers, and each piezo-resistive device of the second pair of piezo-resistive devices has electrons as the majority carriers (See Col. 3, lines 24 – 61 and Col. 4, lines 12 – 55). Ashida fails to disclose a device to extract a value of the strain along the primary strain direction based on combining information derived from the one or more first currents flowing through the first pair of piezo-resistive devices and information derived from the one or more second currents flowing through the second pair of piezo-resistive devices.
However, Haroun discloses an apparatus comprising an extraction device for extracting a value of a strain along a primary strain direction based on combining information derived from one or more first currents flowing through piezoresistive devices 108, 112, 116 (See Fig. 1A, See Col. 7, lines 9 – 43).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify Ashida and according to the teachings of Haroun for the purpose of, advantageously providing an improved device since this type of device does not require a bulky system having separated components (See Haroun, Col. 1, lines 35 – 44).
Conclusion
12. The prior art made of record and not relied upon is considered pertinent
to applicant's disclosure. 13. Shekhawat et al. (7,759,924) disclose a cascaded mosfet embedded multi-input microcantilever. Lal et al. (6,479,920) disclose direct charge radioisotope activation and power generation. Boll et al. (3,609,593) disclose a vibratory reed device. Schott et al. (EP2490036) disclose a stress sensor for measuring mechanical stresses in a semiconductor chip and stress compensated hall sensor.14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OCTAVIA HOLLINGTON whose telephone number is (571)272-2176. The examiner can normally be reached Monday-Friday 9am-5pm.
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/OCTAVIA HOLLINGTON/Primary Examiner, Art Unit 2855 5/30/26
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