DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to applicant’s communication filed February 16, 2026 in response to PTO Office Action dated November 17, 2025. The applicant’s remarks and amendment to the specification and/or claims were considered with the results that follow.
Claims 1-20 have been presented for examination in this application. In response to the last Office Action, claims 1, 3-5, 8, 10-12, and 15-17 have been amended.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suzuki et al. (US# 2019/0294358).
Regarding claim 1, Suzuki et al. teaches a storage system (3) comprising: a plurality of non-volatile storage devices [Fig. 1, at least NAND flash (5); or individual pages/blocks in NAND]; and a storage controller (4) comprising a processing device (12), operatively coupled to the plurality of non-volatile storage devices, configured to: receive, (by way of data) from a non-volatile storage device of the plurality of non-volatile storage devices, an indication [bit error rate, 0096, lines 1-11] that data stored at the non-volatile storage device needs to be refreshed, wherein the data was stored at the non-volatile storage device as part of a data segment [0129, lines 1-8]; identify other data from the data segment stored at one or more of the plurality of non-volatile storage devices (this may be same device) [pages and sub-blocks moved 0129, liens 1-8]; and perform a garbage collection operation to store the data and the other data at a different set of blocks of the non-volatile plurality of storage devices [blocks moved, 0129, lines 1-8].
Regarding claim 2, Suzuki et al. teaches wherein the data and the other data comprise live data from the data segment [live not clearly described and interpreted as data to be refreshed [0129, lines 1-8].
Regarding claim 3, Suzuki et al. teaches wherein the plurality of non-volatile storage devices comprises a plurality of managed flash storage devices [NAND comprises at least plurality of storage device blocks managed by controller; see also 0046] and wherein the indication is generated by logic of the non-volatile storage device and transmitted from the non-volatile storage device to the storage controller [0084, wherein SSD logic for reading influences read disturb stress which results in BER of the block, which is sent to the controller 0096, lines 1-11].
Regarding claim 4, Suzuki et al. teaches wherein the plurality of non-volatile storage devices comprises a heterogeneous mix of at least two different types of storage devices [0036].
Regarding claim 5, Suzuki et al. teaches wherein to perform the garbage collection operation, the processing device is further configured to: allocate the different set of blocks of at least two different types of storage devices for storing the data and the other data based on a similarity of corresponding characteristics (P/E FLASH cycles) of the different set of blocks [ (of the FLASH and DRAM group) for the data movement and storage; 0129, lines 1-8], or for different types nonvolatile memories [0036].
Regarding claim 6, Suzuki et al. teaches wherein the corresponding characteristics correspond to a number of program/erase cycles performed on the different set of blocks [0050 & 0100].
Regarding claim 7, Suzuki et al. teaches wherein the data and the other data are stored at the plurality of storage devices using quad-level cell (QLC) mode [0047, lines 6-9].
Claims 8 and 15 are rejected as containing subject matter similar to that of claim 1, and are rejected for the same reasons as claim 1.
Claims 9 and 16 are rejected as containing subject matter similar to that of claim 2, and are rejected for the same reasons as claim 2.
Claims 10 and 17 are rejected as containing subject matter similar to that of claim 3, and are rejected for the same reasons as claim 3.
Claims 11 and 18 are rejected as containing subject matter similar to that of claim 4, and are rejected for the same reasons as claim 4.
Claims 12 and 19 are rejected as containing subject matter similar to that of claim 5, and are rejected for the same reasons as claim 5.
Claims 13 and 20 are rejected as containing subject matter similar to that of claim 6, and are rejected for the same reasons as claim 6.
Claim 14 is rejected as containing subject matter similar to that of claim 7, and is rejected for the same reasons as claim 7.
Response to Arguments
Applicant's arguments filed July 30, 2025 have been fully considered but they are not persuasive.
Regarding Applicant’s Argument on page 6 of the response directed towards the claimed indication and read count table, the Examiner respectfully disagrees. The aforementioned Bit Error Rate (BER) is not stored in the read count table, but is obtained from data read from the NAND pages.
Regarding Applicant’s Argument on page 7 of the response directed towards the types of non-volatile storage devices, the Examiner respectfully disagrees. Suzuki et al. teaches that NAND is used but other nonvolatile semiconductor memories may be used.
Regarding Applicant’s Argument on page 7 of the response directed towards the corresponding characteristics, the Examiner respectfully disagrees. The phrase “corresponding characteristics” was not defined in the claim, and “similarity-based allocation” as argued by Applicant was not claimed. The types of nonvolatile semiconductor devices of [0036] contain many similarities, including at least refreshing and bit error rates.
Regarding Applicant’s Argument on pages 8-9 of the response directed towards the indication, the Examiner respectfully disagrees. Suzuki et al. teaches read disturb stress within the ssd leading to BER of the blocks, which are read and loaded to the controller.
Therefore, the prior art disclosed supra teaches the claimed subject matter and the prior art rejections are maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Brian R. Peugh whose telephone number is (571) 272-4199. The examiner can normally be reached on Monday-Friday from 7:30am to 3:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Rocio Del Mar Perez-Velez, phone number 571-270-5935, can be reached. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is 571-272-2100.
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/BRIAN R PEUGH/ Primary Examiner, Art Unit 2133