Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is taken in response to Applicant’s Amendment and Remarks filed on September 4, 2025 regarding Application No. 18/771609.
Claims 1-20 are pending for consideration.
Response to Remarks and Amendments
Applicants’ amendments and remarks have been fully and carefully considered, with the Examiner’s response set forth below.
Applicant’s arguments with respect to the independent claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 11-14, 16-17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ellis (US 9,582,211) in view of Anazawa (US 2020/0293198 A1).
Regarding claim 1, Ellis teaches an apparatus, comprising:
a memory device [Data Storage System 100, FIG. 1]; and a controller coupled with the memory device [Storage Device 120, FIG. 1] and configured to cause the apparatus to:
receive a respective command [computer system 110 sends one or more host commands (e.g., read commands and/or write commands) on control line 111 to storage device 120 (c4 L45-65)] to process respective data for each memory array of a set of memory arrays of a memory system [NVM 140-1 … 140-n, FIG.1], each memory array associated with a channel of a set of channels of the memory system [storage device 120 includes M memory channels, each of which has an NVM controller 130 and a set of NVM devices 140 or 142 coupled to the NVM controller 130 (c5 L1-15)];
determine a respective timing delay to process the respective data over each respective channel of the set of channels of the memory system [By generating wait enable signals 306 such that the respective wait periods (e.g., wait periods 320 and 324) are partially non-overlapping, command queues of the different memory channels are deferred in a staggered manner and resumed in a staggered manner. (c10 L60-c11 L5)] based at least in part on a respective current value associated with each respective channel [the wait period and duty cycle of a corresponding memory channel are set in accordance with the power thresholds that have been exceeded by power measurement 311, as determined by power threshold comparison module 312. For example, if there are two or more predefined power thresholds ( e.g., power threshold A=3200 milliWatts, and power threshold 8=3600 milliWatts), and only the lower power threshold A is exceeded by power measurement 311 (e.g., power measurement 311 is 3225 milliWatts), the wait periods and duty cycles of the wait enable signals for each memory channel are smaller than they would be if both power thresholds A and B are exceeded by power measurement 311. (c11 L60 – c12 L15) … Examples of the subsystem for which power is monitored are described above. Power monitor 310 is optionally implemented using one or more current sensors, current-to-voltage converters, diodes, and/or other passive or active components to measure electrical characteristics of storage device 120 and its components. (c9 L10-L40)]; and
process the respective data for each respective memory array and over each respective channel based at least in part on the respective timing delay associated with each respective channel [command execution module 216, which dispatches commands from one or more command queues (e.g., command queue 212) to the NVM devices 140 in memory channel i for execution; command deferral module 214 65 determines when to suspend and when to resume operation of command execution module 216; (c7 L60-67)].
Ellis, however, does not explicitly teach wherein the respective data being for each memory array of the set of memory arrays of the memory system.
Anazawa, in analogous art, teaches the respective data being for each memory array of the set of memory arrays of the memory system [¶0056, “The processor 11 transmits a read command to all the NAND controllers 16 corresponding to each of the NAND memories NM specified in step S101…”; and ¶0068, “In the example illustrated in FIG. 5, data designated by the read request are stored in the NAND memories NM0-0, NM1-1, and NMn-0. The read command for reading the data from the NAND memory NM0-0 is represented as ‘R1’, …”].
That is Anazawa describes a memory system with multiple NAND memory arrays (see FIG. 1, [0026]); wherein the controller can issue parallel read commands for multiple NAND memories (see [0020], [0055]-[0075]); and wherein each command is directed to a particular memory array and channel (see [0056]-[0058]). Anazawa finally discloses that the commands are managed per-channel and per-memory (see queue buffers, [0039], [0056]-[0058]). Hence Anazawa’s controller issues respective commands to respective memory arrays—each command is for data stored in a particular array; wherein the read operations retrieve the data stored in each memory array addressed by the command ([0056]: “The processor 11 transmits a read command to all the NAND controllers 16 corresponding to each of the NAND memories NM specified…”); and the data retrieved is the data stored in each memory array, not a shared/duplicated data item.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to use the data storage technique as disclosed in Anazawa in the system of Ellis. The combination would have been obvious because a person of ordinary skill in the art would know to use the known technique of Anazawa to improve the similar device of Ellis in the same way.
Regarding claim 2, Ellis/Anazawa teach the apparatus of claim 1, wherein determining the respective timing delay is based at least in part on a threshold quantity of channels of the set of channels of the memory system processing the respective data during a same time.
On the one hand, Ellis discloses a non-volatile memory controller that staggers or defers command execution across multiple memory channels to reduce power consumption and avoid power spikes. Ellis monitors power consumption by the memory system or subsystem, and defers command execution per channel during a “wait period” if a power threshold is exceeded. Power is measured and used as the basis for deferral (see Abstract; Figs. 1, 3A, 5A–5D; and corresponding disclosure for these figures). Therefore, Ellis at least teaches determining timing delays based on current values associated with channels. Moreover, Ellis’s “wait period” (timing delay) for each channel is managed such that not all channels are active at once, thereby reducing the number of channels processing data during the same time ([c15 L50-c16 L5], [c13 L30-50], [c16 L25-50], [c11 L5-20], Fig. 3B; and corresponding disclosure). The system can be configured so that only a threshold number of channels are active in parallel ([c11 L19-40]: “wait period for each memory channel…has a duration based at least in part on a priority of the corresponding memory channel,” and [c16 L25-40]: “duty cycle corresponding to a priority,” which is used to limit channel concurrency). And Ellis further discloses “if there are two or more predefined power thresholds ( e.g., power threshold A=3200 milliWatts, and power threshold 8=3600 milliWatts), and only the lower power threshold A is exceeded by power measurement 311 (e.g., power measurement 311 is 3225 milliWatts), the wait periods and duty cycles of the wait enable signals for each memory channel are smaller than they would be if both power thresholds A and B are exceeded by power measurement 311” (c12 L1-15).
On the other hand, Anazawa discloses a memory controller that manages parallel operations across multiple memory channels and arrays ([0020]-[0026], [0055]-[0079]). Anazawa further teaches that the controller may adjust the transfer rates and timing of operations per channel in order to align completion times and avoid excessive simultaneous activity ([0061]-[0075], Figs. 5–7). This effectively show how Anazawa limits the number of channels that are simultaneously processing data, i.e., operates with a threshold quantity of concurrent channels. Finally, Anazawa teaches that transfer rate and timing can be adjusted to avoid performance degradation and power issues due to excessive parallelism ([0078]-[0092]).
Therefore, it would have been obvious to one of ordinary skill in the art to combine the channel concurrency management and parallelism threshold techniques of Anazawa with the power-based (current-based) staggered wait logic of Ellis. Both references address the need to avoid excessive simultaneous channel activity to manage power and performance. Combining Anazawa’s explicit teaching of limiting the number of channels processing data at the same time with Ellis’s staggered delay and power monitoring would yield an apparatus where the timing delay for each channel is determined based, at least in part, on a threshold quantity of channels processing data simultaneously. This would have predictably improved power efficiency and system reliability.
Regarding claim 3, Ellis teaches the apparatus of claim 1, wherein, to process the respective data for each respective memory array and over each respective channel, the controller is configured to cause the apparatus to:
process the respective data for a first memory array and over a first channel in response to a first timing delay associated with the first channel [command execution module 216, which dispatches commands from one or more command queues (e.g., command queue 212) to the NVM devices 140 in memory channel i for execution; command deferral module 214 65 determines when to suspend and when to resume operation of command execution module 216; (c7 L60-67)]; and
process the respective data for a second memory array and over a second channel based at least in part on processing the respective data for the first memory array and in response to a second timing delay associated with the second channel, wherein the first timing delay is different than the second timing delay [the start time for memory channel 1 is different from the start time for memory channels 2, 3 and 4. (c11 L5-20)].
Regarding claim 4, Ellis teaches the apparatus of claim 1, wherein, to process the respective data for each respective memory array and over each respective channel, the controller is configured to cause the apparatus to:
process the respective data for a first memory array and over a first channel in response to the respective timing delay associated with the first channel [command execution module 216, which dispatches commands from one or more command queues (e.g., command queue 212) to the NVM devices 140 in memory channel i for execution; command deferral module 214 65 determines when to suspend and when to resume operation of command execution module 216; (c7 L60-67)]; and
process the respective data for a second memory array and over a second channel in response to the respective timing delay associated with the second channel, wherein the respective timing delay associated with the first channel and the respective timing delay associated with the second channel is the same [In some other embodiments, two or more memory channels may have the same start time for resuming execution of commands, while at least one other memory channel has a different start time for resuming execution (c11 L5-20)].
Regarding claim 11, Ellis teaches the apparatus of claim 1, wherein, to receive the respective command to process respective data for each memory array of the set of memory arrays of the memory system, the controller is configured to cause the apparatus to: receive the respective command to write the respective data to each memory array of the set of memory arrays of the memory system [in some implementations, computer system 110 sends one or more host commands (e.g., read commands and/or write commands) (c4 L45-65)].
Regarding claim 12, Ellis teaches the apparatus of claim 11, wherein, to process the respective data for each respective memory array and over each respective channel, the controller is configured to cause the apparatus to: write the respective data to each respective memory array [in some implementations, computer system 110 sends one or more host commands (e.g., read commands and/or write commands) (c4 L45-65)].
Regarding claim 13, Ellis teaches the apparatus of claim 1, wherein, to receive the respective command to process respective data for each memory array of the set of memory arrays of the memory system, the controller is configured to cause the apparatus to: receive the respective command to read the respective data from each memory array of the set of memory arrays of the memory system [in some implementations, computer system 110 sends one or more host commands (e.g., read commands and/or write commands) (c4 L45-65)].
Regarding claim 14, Ellis teaches the apparatus of claim 13, wherein, to process the respective data for each respective memory array and over each respective channel, the controller is configured to cause the apparatus to: read the respective data from each respective memory array [in some implementations, computer system 110 sends one or more host commands (e.g., read commands and/or write commands) (c4 L45-65)].
Regarding claim 16, Ellis teaches the apparatus of claim 1, wherein the set of memory arrays comprises a set of not-and (NAND) arrays, a set of dynamic random-access memory (DRAM) arrays, or any combination thereof, and the set of channels comprises a set of open not-and (NAND) flash interface working group (ONFI) channels, a set of DRAM channels, a set of compute express link (CXL) channels, or any combination thereof [storage device 120 includes a single NVM device while in other implementations storage device 120 includes a plurality of NVM devices. In some implementations, NVM devices 140, 142 include NAND-type flash memory or NOR-type flash memory. Further, in some implementations, NVM controller 130 is a solid-state drive (SSD) controller. However, one or more other types of storage media may be included in accordance with aspects of a wide variety of implementations. (c4 L20-45)].
Regarding claim 17, Ellis teaches the apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: detect one or more of a voltage, a current, or any combination thereof, wherein determining the respective timing delay is based at least in part on one or more of the voltage, the current, or any combination thereof [In some embodiments, power monitor 310 obtains a power measurement (e.g., power measurement 311) corresponding to power consumption by storage device 120, or a subsystem of storage device 120. Examples of the subsystem for which power is monitored are described above. Power monitor 310 is optionally implemented using one or more current sensors, current-to-voltage converters, diodes, and/or other passive or active components to measure electrical characteristics of storage device 120 and its components. (c9 L10-40)].
Regarding claim 19 and 20; these claim(s) limitations are significantly similar to those of claim(s) 1; and, thus, are rejected on the same grounds.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ellis in view of Anazawa (US 2020/0293198 A1); and further in view of Sethuraman (US 20200396625).
Regarding claim 5, Ellis explicitly teach all the claim limitations except for the apparatus of claim 1, wherein the respective timing delay comprises a preconfigured time duration and each channel of the set of channels of the memory system is associated with a quantity of timing delays.
Sethuraman, in analogous art teaches wherein the respective timing delay comprises a preconfigured time duration and each channel of the set of channels of the memory system is associated with a quantity of timing delays [the IoT devices 101, 103, 105 may use the channel metrics to stagger its Tx by waiting until better channel conditions become available or until the expiration of a preconfigured delay period. (¶0022)].
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to use a preconfigured time delay as disclosed in Sethuraman. The combination would have been obvious because a person of ordinary skill in the art would want to further reduce the power consumption when staggering commands (¶0001).
Regarding claim 6, Ellis teaches the apparatus of claim 5, wherein the preconfigured time duration is based at least in part on a response time of a power management integrated circuit of the memory system [FIG. 3A is a block diagram illustrating an implementation of a power usage monitor and staggered wait logic 124, in accordance with some embodiments (c8 L60-c9 L15)].
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ellis in view of Anazawa (US 2020/0293198 A1).
Regarding claim 9, Ellis explicitly teach all the claim limitations except for the apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: receive a configuration indicating a threshold quantity of channels of the set of channels of the memory system to be active during a duration, wherein determining the respective timing delay is based at least in part on the configuration.
On the one hand, Ellis discloses that the computer readable storage medium of memory 206 further stores a configuration module for configuring NVM controller 130-I;k wherein in some embodiments, upon power up and upon reset, the configuration module automatically sets the values of one or more configuration parameters of NVM controller 130-i in accordance with the components of memory channel i (e.g., the type of non-volatile memory components in memory data storage system 100, which includes storage device 120 [c8 L1-25].
On the other hand Elllis discloses that for example, if there are two or more predefined power thresholds (e.g., power threshold A=3200 milliWatts, and power threshold 8=3600 milliWatts), and only the lower power threshold A is exceeded by power measurement 311 (e.g., power measurement 311 is 3225 milliWatts), the wait periods and duty cycles of the wait enable signals for each memory channel are smaller than they would be if both power thresholds A and B are exceeded by power measurement 311 [c12 L1-15].
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to further include disclosed thresholds as configurable parameters. The combination would have been obvious because a person of ordinary skill in the art would understand that is standard for computer systems to have configurable parameters such as thresholds.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ellis in view of Anazawa (US 2020/0293198 A1); and further in view of Tiku (US 20240393945).
Regarding claim 10, Ellis explicitly teach all the claim limitations except for the apparatus of claim 1, wherein, to receive the respective command to process respective data for each memory array of the set of memory arrays of the memory system, the controller is configured to cause the apparatus to:
receive the respective command to transfer data from a first memory array of the set of memory arrays of the memory system to a second memory array of the set of memory arrays of the memory system.
Tiku, in analogous art, teaches wherein, to receive the respective command to process respective data for each memory array of the set of memory arrays of the memory system, the controller is configured to cause the apparatus to:
receive the respective command to transfer data from a first memory array of the set of memory arrays of the memory system to a second memory array of the set of memory arrays of the memory system [(¶0016) a memory controller may receive a command from the host to move the data from a first memory array to a second memory array of the main memory].
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to move date between arrays as disclosed in Tiku. The combination would have been obvious because a person of ordinary skill in the art would want to provide persistent data (¶0020 in Tiku).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ellis in view of Shin (US 20180011635).
Regarding claim 18, Ellis explicitly teach all the claim limitations except for the apparatus of claim 1, wherein the respective command comprises an external transfer command, and the respective data comprises a page.
Shin, in analogous art, teaches wherein the respective command comprises an external transfer command, and the respective data comprises a page [The decoded external command inputted to the second command queue 123 may include tags, commands, and an address indicating a page of the memory array 110. (¶0066)].
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to transfer external commands of data comprising pages as disclosed in Shin. The combination would have been obvious because a person of ordinary skill in the art would know to combine prior art elements according to known methods to yield predictable results.
Allowable Subject Matter
Claims 7, 8 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/Ramon A. Mercado/Supervisory Patent Examiner, Art Unit 3658
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