DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-15 are presented for examination in this application. The application filing date on 07/12/2024. Claims 1 and 12 are independent.
Examiner notes
(A). Examiner interpreted “and/or” as “or” which have been recited in independent claims 1, and 12 as well other dependent claims.
(B). Drawings submitted on 07/12/2024 comply with the provisions of 37 CFR 1.121(d), (C). IDS submitted on 09/19/2024 have been fully considered by the Examiner.
(C). Limitations have been provided with the Bold fonts in order to distinguish from the cited part of the reference (Italic).
(D). Examiner has cited particular columns, line numbers, references, or figures in references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 VI and 2123.
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111 (c).
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in European patent application no. EP23185063.7 on 07/12/2023. Examiner further acknowledged that receiving electronics copy of European patent application. Accordingly, the foreign priority filing date is being considered by the examiner.
Claim Objections
Claims 1-15 are objected to because of the following informalities:
Claim 1:
Line 2, first occurrence of an acronym “FPGA” should be written as --field programmable gate array (FPGA)--.
Line 4, replace both “it” with –the FPGA program code to be generated--, respectively.
Line 4-5, “the framework” lacks proper antecedent basis.
Line 6, “the result” lacks proper antecedent basis.
Line 8-9, “the initialization program code” lacks proper antecedent basis.
Claim 3:
Line 2-3, “the running of the initialized FPGA program code” lacks proper antecedent basis.
Claim 7:
Line 1, “the controlled FPGA” lacks proper antecedent basis.
Claim 9:
• Line 2, first occurrence of an acronym, “VHDL” must be spelled out as --Very High Speed Integrated Circuit Hardware Description Language (VHDL)--.
Claim 12:
Line 2, first occurrence of an acronym “FPGA” should be written as --field programmable gate array (FPGA)--.
Line 7, “the result” lacks proper antecedent basis.
Claim 13:
Line 2, before “further”, delete “a”.
Claim 14:
Line 3, first occurrence of an acronym “API” should be written as --Application Programming Interface (API)--.
Claim 15:
Line 5, “the transferred bit position” lacks proper antecedent basis.
Claims 2, 4-6, 8, and 10-11 are dependent claims of objected claims; therefor they inherit the same issues as in the base claims.
Appropriate correction is required.
CONTINGENT LIMITATIONS
Claim 13 (method claims) interpreted based on Ex parte Schulhauser. See MPEP 2111.04 ll.
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A nor B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B.
The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.
See Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016) for an analysis of contingent claim limitations in the context of both method claims and system claims. In Schulhauser, both method claims and system claims recited the same contingent step. When analyzing the claimed method as a whole, the PTAB determined that giving the claim its broadest reasonable interpretation, "[i]f the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed" (quotation omitted). Schulhauser at 10. When analyzing the claimed system as a whole, the PTAB determined that "[t]he broadest reasonable interpretation of a system claim having structure that performs a function, which only needs to occur if a condition precedent is met, still requires structure for performing the function should the condition occur." Schulhauser at 14. Therefore "[t]he Examiner did not need to present evidence of the obviousness of the [ ] method steps of claim 1 that are not required to be performed under a broadest reasonable interpretation of the claim (e.g., instances in which the electrocardiac signal data is not within the threshold electrocardiac criteria such that the condition precedent for the determining step and the remaining steps of claim 1 has not been met);" however to render the claimed system obvious, the prior art must teach the structure that performs the function of the contingent step along with the other recited claim limitations. Schulhauser at 9, 14.Noting that no claim may be read apart from and independent of the supporting disclosure on which it is based, the court found that the claim was internally inconsistent based on the description, definitions and examples set forth in the specification relating to the appearance of the surface after treatment, and therefore indefinite. Id. (Cohn, 438 F.2d at 993).
Claim Rejections - 35 U.S.C. 112
The following is a quotation of the second paragraph of 35 U.S.C. 112:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
Claim 3, it is not clear whether “a build and / or initialization” in line 2 of claim 3 is the same as “a build and / or initialization step” of line 8 of claim 1 or not. For the purposes of examination, “a build and / or initialization step” of line 2 of claim 3 will be interpreted as --the build and / or initialization step--.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-2 and 8 are rejected under 35 U.S.C. 103 as being obvious over Kassas et al. (US 20080263343 A1, hereinafter Kassas) in view of Sanchez et al. US 20040210855 A1, hereinafter Sanchez) and Zhou et al. (CN 111123083 B, hereinafter Zhou).
As to claim 1, Kassas discloses a computer system to run several build and / or initialization steps controlled by a computer for an FPGA-based application, wherein the computer system being set up to generate an FPGA program code as part of build steps (par. 0105, FIGS. 3 and 4A/4B illustrate exemplary graphical programs (block diagrams), also referred to as virtual instruments (VIs), and a front panel (GUI), according to one embodiment. More specifically, the graphical programs implement a PID controller application that utilizes a PHE, e.g., a field programmable gate array (FPGA), where FIG. 3 illustrates a typical user-created program or VI that may run on the PHE, e.g., an FPGA target program, and that is executable to pass multiple channels of data to host program executing on a controller coupled to the PHE …),
Kansas does not explicitly disclose the following limitations but,
Sanchez discloses to check by reading the writable memory before a build and / or initialization step and / or before the initialization program code has been run as to whether at least one previous build and / or initialization step has been completed without errors (par. 0025, … system and parameter consistency checks can include, matching data bus widths of peripherals and system components, determining interrupt conflicts, determining memory map conflicts, determining memory size and usage, determining device counts, determining availability of FPGA resources and determining maximum operating frequency. Further, par. 0026, he system analyzer 120 can be configured to propagate default values, global values and/or previously defined values through the system model. … Further, par. 0027, … By tracking memory usage, the system analyzer 120 can have the capability to determine whether the code space assigned in the memory map is too large for the physical memory. System analyzer 120 can also be configured to track physical resource requirements for example, slice counts for IP blocks, and width and height of specifications of IP blocks. A GUI can provide a visual display of a resulting or representative floor plan to aid with tracking and management of physical resources).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include initialization build steps, as disclosed by Sanchez, for the purpose for customization of the software of an FPGA-based SoC includes the steps of selecting a system component used for customizing the FPGA-based (see abstract of Sanchez).
Zhou discloses to transfer it to an FPGA, and wherein the computer system is further set up to store and / or control the results of the build and / or initialization steps centrally in a writable memory (page 6, … downloading the test bit
stream code to the to-be-tested FPGA chip to the circuit board be-detected circuit board the to-be-circuit board is used for transmitting the output signal generated by the operation of the FPGA chip be tested based on the test bit stream code and the clock signal to the PC machine; the PC machine is further used for analyzing the output signal of the FPGA chip be tested to finish the test. More specifically, the invention claims a test system for FPGA PLL IP core, the FPGA to be tested is chip on the circuit board to be tested, the circuit board to be tested on the input signal and the output signal of the FPGA chip to the test point, so as to apply excitation to the FPGA chip observe the output signal. The power supply provides core and I/O power for the circuit board to be tested. The signal source provides input clock signal for the circuit board to be tested. the logic analyzer samples the output signal of the PLL in the tested FPGA chip the side circuit board and stores it as the file for analysis. the PC machine is the control center of the test verification platform, the finished work comprises: (1) downloading the test bit stream code to the FPGA chip be tested on the circuit board to be tested; (2) controlling the output voltage of the power supply, current limiting current, recording power output voltage value and output current value; (3) controlling the waveform of the signal output by the signal source, frequency and duty ratio; (4) controlling the logic analyzer to sample the output signal on the circuit board to be tested, and storing the sampled signal in the file),
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include a computer system to run several build and / or initialization steps controlled by a computer for an FPGA-based application wherein the computer system being set up to generate an FPGA program code as part of build steps, as disclosed by Zhou, for the purpose of transmitting the output signal generated by the operation of the FPGA chip be tested based on the test bit stream code and the clock signal to the PC machine; the PC machine is further used for analyzing the output signal of the FPGA chip be tested to finish the test. (see abstract of Zhou).
As to claim 2, Kassas discloses the computer system wherein the writable memory is a Block RAM of the FPGA (par. 0106, … the new configuration may be stored in the appropriate memory locations (block RAM) on the FPGA target …).
As to claim 8, Kansas discloses the computer system wherein the computer system is designed to control a (par. 0031, FIG. 4A illustrates a typical user-implemented supervisory control loop program targeted for execution on a controller, and configured to provide configuration data to the multi-channel FPGA program of FIG. 3, and to monitor inputs and outputs to the FPGA target program. Further, par. 0032, FIG. 4B illustrates a typical graphical user interface (GUI) for the user-implemented supervisory control loop program of FIG. 4A; Further, par. 0106, … Thus, the processing loop may serve as a supervisory control loop that provides configuration data to the multi-channel (e.g., n channels) PHE function and monitoring of inputs and outputs of the processing function as required …).
Claim 3 is rejected under 35 U.S.C. 103 as being obvious over Kassas et al., Sanchez et al. and Zhou et al. as applied to the claim 1 and further in view of Wang et al. Wang et al. (CN 108595269 A, hereinafter Wang).
As to claim 3, Kansas as modified by Sanchez and Zhou does not explicitly disclose the following limitations but,
Wang discloses, the computer system according wherein the computer system is set up to perform (page 10, … , firstly the data read into a memory of the FPGA from the memory of CPU through DMA method, the data written to the DRAM at the same time carrying out exclusive-or calculation, After the data to be written and XOR calculating the check data are written in the FPGA memory, write control module processes all the data hard disk and check hard disk sends write command frame, when state returned by all hard disk are displayed without error, to inform the RAID controller drives the RAID command completed successfully,, … ).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include the computer system according wherein the computer system is set up to perform a build and / or initialization step and / or the running of the initialized FPGA program code only if the previous build and / or initialization step has been completed without errors , as disclosed by Wang, for the purpose of checking data are read out and returned by all hard disk state is displayed without error in the executing process (see page 11 of Wang).
Claims 4 is rejected under 35 U.S.C. 103 as being obvious over Kassas et al. , Sanchez et al. and Zhou et al. as applied to claim 1 in the above and further in view of Gould et al. (US 20190236749 A1, hereinafter Gould).
As to claim 4, Kassas as modified by Sanchez and Zhou does not explicitly disclose the following limitations but,
Gould discloses the computer system wherein the computer system is set up to grant write access to the writable memory under predefined conditions (par. 0054, … the write allocation pointer can allow each thread to determine where to write its data, and each thread, upon determining the write allocation pointer, can advance the write allocation pointer to a next memory location for writing data. … ).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include the computer system wherein the computer system is set up to grant write access to the writable memory under predefined conditions, as disclosed by Gould, for the purpose of performing atomic/Interlocked Operation Hardware in order to avoid race conditions that would otherwise occur with multi-threaded programming (see paragraph 0054 of Gould).
Claim 5 is rejected under 35 U.S.C. 103 as being obvious over Kassas et al., Sanchez et al. and Zhou et al. as applied to claim 1 in the above and further in view of Liu et al. (CN US 20230325507 A1, hereinafter Liu).
As to claim 5, Kansas as modified by Sanchez and Zhou does not explicitly disclose the following limitations but,
Liu discloses the computer system wherein the computer system is set up to prevent write access to predetermined bit areas on the writable memory (par. 0010, Code for certain applications (e.g. applications that are essential to the functioning of a device including the host system and memory system, such as an operating system) may be stored in a write-protected area of the memory system, where the host system may be prevented from altering code for applications that is stored in the write-protected area of the memory system. That is, application code that is stored in the write-protected area may be read-only for the host system or other applications …).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include the computer system wherein the computer system is set up to prevent write access to predetermined bit areas on the writable memory, as disclosed by Liu, for the purpose of write-protected area may be read-only for the host system or other applications. (see par. 0010 of Liu).
Claim 6 is rejected under 35 U.S.C. 103 as being obvious over Kassas et al., Sanchez et al. and Zhou et al. as applied to claim 1 in the above and further in view of Pandey et al. (US 10020067 B2, hereinafter Pandey).
As to claim 6, Kansas as modified by Sanchez and Zhou does not explicitly disclose the following limitations but,
Pandey discloses the computer system wherein the computer system is configured to (col. 2, ll. 37-43, OTP controller 106 is configured to send and receive data to and from OTP memory 108, and to send data from OTP memory to processor 102 and other components (not shown) in system 100 or external to system 100. The information stored in OTP memory 108 is not erasable [i.e. change] and can be programmed only once. When the data is programmed, error correction techniques such as ECC).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include the computer system wherein the computer system is configured to change each bit only once, as disclosed by Pandey, for the purpose of ECC bits or the redundant data can be provided from OTP memory 108 to OTP control. (see col. 2, ll. 55-57 of Pandey).
Claim 7 is rejected under 35 U.S.C. 103 as being obvious over Kassas et al. , Sanchez et al. and Zhou et al. as applied to claim 1 in the above and further in view of Luo et al. (US 20180024194 A1, hereinafter Luo).
As to claim 7, Kansas as modified by Sanchez and Zhou does not explicitly disclose the following limitations but,
Luo discloses the computer system (par. 0006, … thereby enabling fast configuration of the FPGA chip for testing of its functional and performance parameters without needing to power-off. This entails a solution capable of real-time, … ).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include the computer system the FPGA-based application is part of a real-time capable system, as disclosed by Luo, for the purpose of fast, repeatable configuration and functional and performance testing. Further, it allows not only rapid download of multiple configuration code streams but also higher configuration speed and lower implementation costs. (see paragraph 0006 of Lou).
Claim 9 is rejected under 35 U.S.C. 103 as being obvious over Kassas et al. , Sanchez et al. and Zhou et al. as applied to claim 1 in the above and further in view of Palermo et al. (US 20230421253 A1, hereinafter Palermo).
As to claim 9, Kansas as modified by Sanchez and Zhou does not explicitly disclose the following limitations but,
Palermo discloses the computer system wherein the computer is set up to perform one or more of the following build and / or initialization steps:
(par. 0062, … the PDC can be initialized by being instantiated on hardware (e.g., configure an FPGA to implement the PDC), software (e.g., configure an application, a virtual machine, a container ...).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system Palermo disclosed by Kassas to include creation of an FPGA application container, as disclosed by, for the purpose of creation of an FPGA application container. (see paragraph 0065 of Palermo).
Claim 10 is rejected under 35 U.S.C. 103 as being obvious over Kassas et al., Sanchez et al. and Zhou et al. as applied to claim 1 in the above and in view of Smith et al. (US 8219772 B2, hereinafter Smith).
As to claim 10, Kansas as modified by Sanchez and Zhou does not explicitly disclose the following limitations but,
Smith discloses the computer system wherein the computer system is set up to perform an integrity check on the writable memory after a write access (par. Abstract, A method and system of controlling access to a programmable memory including: allowing code to be written to the programmable memory in a first access mode; preventing execution of the code stored in the programmable memory in the first access mode; verifying the integrity of the code stored in the programmable memory… ).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include the computer system wherein the computer system is set up to perform an integrity check on the writable memory after a write access, as disclosed by Smith, for the purpose of if the integrity of the code stored in the programmable memory is verified, setting a second access mode, wherein in the second access mode, further code is prevented from being written to the programmable memory, and execution of the code stored in the programmable memory is allowed. (see abstract of Smith).
Claim 11 is rejected under 35 U.S.C. 103 as being obvious over Kassas et al., Sanchez et al. and Zhou et al. and Smith et al. as applied to claim 11 in the above and further in view of Rabbani et al. (US 20210365592 A1, hereinafter Rabbani).
As to claim 11, Kansas as modified by Sanchez, Zhou and Bernat does not explicitly disclose the following limitations but,
Rabbani discloses the computer system wherein the computer system is set up to perform an integrity check on the writable memory via a checksum (par. 0015, … writing them to the device's memory, and of reading out the checksum and sending it back to the verifier. Configurable hardware devices like FPGAs …).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include the computer system wherein the computer system is set up to perform an integrity check on the writable memory via a checksum, as disclosed by Rabbani, for the purpose of verifying and determining if the prover is operating in the intended state file. (see paragraph 0010 of Rabbani)
.
Claim 12 is rejection under 35 U.S.C. 103 as being obvious over Kassas et al., Sanchez et al. and Zhou et al., Luo et al and Wang et al.
As to claim 12, Kassas discloses a method for error-free execution of multiple build and / or initialization steps controlled by a computer for an FPGA-based application, the method comprising:
generating an FPGA program code as part of build steps (par. 0105, FIGS. 3 and 4A/4B illustrate exemplary graphical programs (block diagrams), also referred to as virtual instruments (VIs), and a front panel (GUI), according to one embodiment. More specifically, the graphical programs implement a PID controller application that utilizes a PHE, e.g., a field programmable gate array (FPGA), where FIG. 3 illustrates a typical user-created program or VI that may run on the PHE, e.g., an FPGA target program, …);
Kansas does not explicitly disclose the following limitations but,
Sanchez discloses running initialization steps in preparation for an execution of the FPGA program code (par. 0008, … a method of generating a chip support package for a customized FPGA-based SoC can comprise the step of monitoring during initialization of the customized FPGA-based SoC for at least one system component and associated parameters among a plurality of system components used for customizing the customized FPGA-based SoC and the step of creating a software interface based on the system components and associated parameters monitored));
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include running initialization steps in preparation for an execution of the FPGA program code, as disclosed by Sanchez, for the purpose for customization of the software of an FPGA-based SoC includes the steps of selecting a system component used for customizing the FPGA-based (see abstract of Sanchez).
Zhou discloses transferring the generated FPGA program code to an FPGA) to transfer it to an FPGA, and wherein the computer system is further set up to store and / or control the results of the build and / or initialization steps centrally in a writable memory (page 6, … downloading the test bit
stream code to the to-be-tested FPGA chip to the circuit board be-detected circuit board the to-be-circuit board is used for transmitting the output signal generated by the operation of the FPGA chip be tested based on the test bit stream code and the clock signal to the PC machine; the PC machine is further used for analyzing the output signal of the FPGA chip be tested to finish the test. More specifically, the invention claims a test system for FPGA PLL IP core, the FPGA to be tested is chip on the circuit board to be tested, the circuit board to be tested on the input signal and the output signal of the FPGA chip to the test point, so as to apply excitation to the FPGA chip observe the output signal. The power supply provides core and I/O power for the circuit board to be tested. The signal source provides input clock signal for the circuit board to be tested. the logic analyzer samples the output signal of the PLL in the tested FPGA chip the side circuit board and stores it as the file for analysis. the PC machine is the control center of the test verification platform, the finished work comprises: (1) downloading the test bit stream code to the FPGA chip be tested on the circuit board to be tested; (2) controlling the output voltage of the power supply, current limiting current, recording power output voltage value and output current value; (3) controlling the waveform of the signal output by the signal source, frequency and duty ratio; (4) controlling the logic analyzer to sample the output signal on the circuit board to be tested, and storing the sampled signal in thefile),
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include a computer system to run several build and / or initialization steps controlled by a computer for an FPGA-based application wherein the computer system being set up to generate an FPGA program code as part of build steps, as disclosed by Zhou, for the purpose of transmitting the output signal generated by the operation of the FPGA chip be tested based on the test bit stream code and the clock signal to the PC machine; the PC machine is further used for analyzing the output signal of the FPGA chip be tested to finish the test. (see abstract of Zhou).
Luo discloses storing and controlling the results of the build and / or initialization steps in a central writable memory (par. 0049-0050, … The ATE test module 60 is adapted to provide a signal indicative of a request for configuring the chip under test and control the test and configuration board to generate a test signal. In addition, the ATE test module 60 applies a test signal source file to the FPGA under test 63 and determines and analyzes the test results output therefrom … . Further, par. 0050, …The flash memories [i.e. writable] are adapted to store repeatedly reconfigured configuration code streams needed for testing of the FPGA chip. High-coverage FPGA testing requires a large number of configuration code streams for testing various FPGA functions. These configuration code streams are stored in different areas in the flash memories. The flash memories are advantageous in that they can be combined into an array for storing a plurality of configuration code streams);
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include checking, in a writable memory, as to whether at least one previous build and / or initialization step has been completed without errors, as disclosed by Luo, for the purpose of controlling test algorithm developed based on ATE, reading a configuration code stream consisting of corresponding configuration codes by a master FPGA from the mass memories. (see paragraph 0009 of Lou).
Wang discloses checking, in a writable memory, as to whether at least one previous build and / or initialization step has been completed without errors (page 10, … , firstly the data read into a memory of the FPGA from the memory of CPU through DMA method, the data written to the DRAM at the same time carrying out exclusive-or calculation, After the data to be written and XOR calculating the check data are written in the FPGA memory, write control module processes all the data hard disk and check hard disk sends write command frame, when state returned by all hard disk are displayed without error, to inform the RAID controller drives the RAID command completed successfully,, … ).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include checking, in a writable memory, as to whether at least one previous build and / or initialization step has been completed without errors, as disclosed by Wang, for the purpose of checking data are read out and returned by all hard disk state is displayed without error in the executing process (see page 11 of Wang).
Claim 13 is rejection under 35 U.S.C. 103 as being obvious over Kassas et al., Sanchez et al., Zhou et al.. Luo et al. and Want et al. as applied to claim 12 above and further in view of Wang et al. (CN 108595269 A, hereinafter Wang).
As to claim 13, Kassas et al. as modified by Sanchez, Zhou et al. and Luo does not explicitly disclose the following but,
Wang discloses the method further comprising the step of:
performing a further build and / or initialization step and / or running the initialized FPGA program code only if the previous build and / or initialization step has been completed without errors (page 10, … , firstly the data read into a memory of the FPGA from the memory of CPU through DMA method, the data written to the DRAM at the same time carrying out exclusive-or calculation, After the data to be written and XOR calculating the check data are written in the FPGA memory, write control module processes all the data hard disk and check hard disk sends write command frame, when state returned by all hard disk are displayed without error, to inform the RAID controller drives the RAID command completed successfully,, … ).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include performing initialization step, as disclosed by Wang, for the purpose of checking data are read out and returned by all hard disk state is displayed without error in the executing process (see page 11 of Wang).
Claim 14 is rejected under 35 U.S.C. 103 as being obvious over Kassas et al., Sanchez et al., Zhou et al., Luo et al. and Wang as applied to claim 12 in the above and further in view of Gould et al. (US 20190236749 A1, hereinafter Gould).
As to claim 14, Kassas as modified by Kassas et al. as modified by Sanchez et al., Zhou et al. and Luo does not explicitly disclose the following limitations but,
Gould discloses the method further comprising the step of:
assigning bit positions in the writable memory to an initialization management component via an API query (par. 0027, in one implementation, computer device 10 includes a CPU 34, which may be one or more processors, or CPU processor core(s) 38, that are specially-configured or programmed to control [i.e. management] operation of computer device 10 according to the described examples. For instance, a user may provide an input to computer device 10 to cause CPU 34 to execute one or more of software application(s) 46, GPU driver 48, graphics application programming interface (API) 52, an optional CPU-side FIFO queue manager 74 …. Further, par. 0042, … the pointers 216, 218, 220, 222 may be constructed to have a number of high order bits that can indicate an identifier of the memory page, which may be an index into an array of memory page addresses 212 allocated [i.e. assigned] for the FIFO queue. …).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include assigning bit positions in the writable memory to an initialization management component via an API query, as disclosed by Gould, for the purpose of indexing into an array of memory page addresses allocated / assigned. (see paragraph 0042 of Gould).
Claim 15 is rejected under 35 U.S.C. 103 as being obvious over Kassas et al., Sanchez et al., Zhou et al., Luo et al., Wang and Gould et al. as applied to claim 14 in the above and further in view of Ohtsubo et al. (US 20090304345 A1, hereinafter Ohtsubo) and Dosaka et al. (US 20070058407 A1, hereinafter Dosaka).
As to claim 15, Kassas as modified Kassas et al. as modified by Sanchez et al. and Zhou et al. and Luo does not explicitly disclose the following limitations but,
Ohtsubo discloses the method wherein the initialization management component performs the following steps:
discloses assigning a free bit position for connected hardware and / or software components (par. 0199, … a start of the next block allocated [i.e. assigned] in the free block bit map is acquired from the file system, and set as the search start position (step S10006));
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include assigning a free bit position for connected hardware and / or software components, as disclosed by Ohtsubo, for the purpose of registering in the free block bit map to search for a largest frame size. (see paragraph 0205 of Ohtsubo).
Dosaka discloses (par. 0009, an arrangement in which the bit/search line is selectively connected to a storage node of a memory cell in accordance with a write enable signal, in order to realize a write mask, by selectively writing data to each of the memory cells. According to Reference 1, a parallel memory array of CAM cells storing data in parallel and allowing a search of parallel data, and a serial bit array orthogonal to the parallel memory array are arranged, and data are transmitted to the parallel memory array in accordance with the data stored in the serial bit array, so that selective parallel writing to bits at specific positions of the parallel data word becomes possible).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Kassas to include storing a reference for the bit position in a writable memory, as disclosed by Dosaka, for the purpose of arrangement in which the bit/search line is selectively connected to a storage node of a memory cell in accordance with a write enable signal, in order to realize a write mask, by selectively writing data to each of the memory. (see paragraph 0009 of Dosaka).
Conclusion
Prior arts made of record are considered pertinent to applicant's disclosure. See MPEP § 707.05 (C) For Examples:
I. Zhang et al. (US-10521618-B1) discloses: “ FIG. 2 illustrates example configurations of an OTP memory module and security module generally at 200. The illustrated OTP memory module 132 and security module 134 may represent intellectual property (IP) cores, IP macros, IP blocks, or any other suitable unit of circuitry (e.g., logic, cells, chip layout/nets). Alternately or additionally, each or both of the OTP memory module 132 and security module 134 may be implemented as part of a system-on-chip (SoC), application-specific standard part (ASSP), digital signal processor (DSP), programmable SoC (PSoC), or field-programmable gate array (FPGA)..” (please see col. 5, ll.10-20).
II. Hwang et al. (US 20050183045 A1) discloses: “The invention provides an interface that can facilitate integration of user specific proprietary cores and commercially available cores during customization of an FPGA-based SoC. A selected hardware or software system component used for customizing the FPGA-based SoC can be configured using parameters that can be automatically propagated and used to configure peer system components. During configuration of the peer system components, other parameters used to configure those peer system components can also be propagated and used to configure other system components during customization of the FPGA-based SoC.” (please see [xxx]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammad Kabir whose telephone number is (571)270-13411. The examiner can normally be reached on M-F, 8:00 am - 5:00 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sam Sough can be reached on (571) 272-6799. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Mohammad Kabir/
Examiner, Art Unit 2192
/S. Sough/SPE, Art Unit 2192
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