Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 9-11, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20190265888 A1) in view of Huang et al. (US 2018/0373584 A1).
Regarding claim 1: Yang discloses an apparatus (non-volatile storage system 100) comprising: one or more control circuits (controllers 102, FIGs. 1 and 2A) configured to connect to a three-dimensional NAND memory structure (non-volatile memory 104 can be NAND flash memory cells in a three dimensional configuration, par. 51, FIG. 2A, the NAND memory structure organized into pages (page in memory of memory cells, par. 23) of NAND memory cells (NAND flash memory cells, par. 51), the one or more control circuits configured to: track multi-level cell (MLC) (memory comprises MLC memory, par. 23) programming speed (tracking read speed via parallelism, par. 53) of candidate pages (applies to pages, par. 62) in the three-dimensional memory structure (semiconductor memory elements may be arranged in three dimensional memory structure, par. 78), the candidate pages being candidates for single-level cell (SLC) (programming pages of an SLC block, par. 69) programming without program verify (pages used for programming without verify 1000 and 1060, FIG. 10); determine whether individual candidate pages are eligible (YES/NO determination of 1050 of FIG. 10) for single-level cell (SLC) programming (1005 of FIG. 10) without program verify (1060 of FIG. 10); and program (1035 of FIG. 10) the candidate pages based on the determination.
Yang does not disclose the determination being based on the MLC programming speed.
Huang does disclose a device for programming non-volatile memory (200) where an MLC programming operation (FIG. 3) has a step of determining the speed of the programming (determination 314, FIG. 3).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the determination for programming Yang (1050, FIG 10) with the determination of checking the programming speed of the MLC pages to have the system determine the appropriate programming with or without verify to save time due to the faster operation when verify operation is skipped (Yang par. 66) (Yang par. 66).
Regarding claim 2: Yang discloses a non-volatile storage system (100), wherein programming the candidate pages based on the determination includes the one or more control circuits: programming the candidate pages (1005 of FIG. 10) to a single bit per memory cell without program verify (1060 of FIG. 10) or to a single bit per memory bit with program verify (1070 of FIG. 10) based on a determination.
Yang does not disclose the programming basing the determination on the MLC programming speed meeting or failing to meet a speed criterion.
Huang does disclose a device for programming non-volatile memory (200) where an MLC programming operation that is checked for meeting a speed criterion (314 of FIG. 3 verifies a number of programming pulses to MLC is less than a limit, par. 33) and failing to meet a speed criterion (314 of FIG. 3 verifies a number of programming pulses to MLC is equal or greater than a limit, par. 33).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the determination for programming Yang (1050, FIG 10) with the determination of checking the programming speed of the MLC pages to have the system determine the appropriate programming with or without verify to save time due to the faster operation when verify operation is skipped (Yang par. 66).
Regarding claim 3: Yang discloses a non-volatile storage system (100), wherein: based on a determination, programs candidate pages that with (1070, FIG. 10) or without (1060, FIG. 10) a program verify.
Yang does not disclose tracking multi-level cell (MLC) programming speed of the candidate pages includes tracking which candidate pages complete MLC programming within a pre-determined number of program pulses and which candidate pages complete MLC programming in more than the pre-determined number of program pulses.
Huang does disclose a device for programming non-volatile memory (200), wherein: tracking multi-level cell (MLC) programming speed of the candidate pages includes tracking which candidate pages complete MLC programming within a pre-determined number of program pulses (block 314 of FIG. 3 verifies a number of programming pulses to MLC is less than a limit, par. 33) and which candidate pages complete MLC programming in more than the pre-determined number of program pulses (block 314 of FIG. 3 verifies a number of programming pulses to MLC is equal or greater than a limit, par. 33).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the determination for programming Yang (1050, FIG 10) with the determination of checking the programming speed via program pulses of the MLC pages to have the system determine the appropriate programming with or without verify to save time due to the faster operation when verify operation is skipped (Yang par. 66).
Regarding claim 9: Yang discloses a non-volatile storage system (100), wherein the NAND memory structure is further organized into blocks (blocks of memory, par. 69, FIG. 1), each block comprises a plurality of the candidate pages (pages contained within blocks in memory, par. 40), each block comprises a plurality of NAND strings (NAND memory array composed of multiple strings of memory, par. 77) and plurality of word lines (memory elements of memory array having word lines, par. 80) associated with the NAND strings in the block, each candidate page comprises a group of memory cells connected to the same word line (page comprises memory cells of a set of word lines, par. 62), more than one of the candidate pages is connected to the same word line (pages of a block sharing the word line of the memory, par. 40).
Regarding claim 10: Yang discloses a method for operating NAND memory (NAND memory device, par. 43), the method comprising: Programming (1005 of FIG. 10, par. 41) a block of NAND memory cells (blocks of memory comprised of NAND flash memory cells, par. 51, FIG, 2A) to multiple bits per memory cell group by group (multiple-level cells MLC, par. 41), each candidate group being a candidate for programming to a single bit per cell without verify (1060 of FIG. 10); and programming the block of the NAND memory cells to a single bit per memory cell group by group (SLC programming 1005 of FIG. 10, par. 41), including: applying one or more program pulses followed by a program verify (program-verify after the program pulse, par. 69, 1070 of FIG. 10); and applying a single program pulse without any program verify (1060 of FIG. 10).
Yang does not disclose a method of tracking which candidate groups take more than a pre-determined number of program pulses to complete programming; and applying one or more program pulses followed by a program verify for each of the one or more program pulses for those candidate groups that took more than the pre-determined number of program pulses to complete programming to multiple bits per memory cell; and applying a single program pulse without any program verify for those candidate groups that completed programming to multiple bits per cell within the pre-determined number of program pulses.
Huang does disclose a method for programming non-volatile memory (200), including tracking which candidate groups take more than a pre-determined number of program pulses to complete programming (block 314 of FIG. 3 verifies a number of programming pulses to MLC is equal or greater than a limit, par. 33), and a determination of proceeding a program operation followed with a program verify for each of the one or more program pulses for those candidate groups that took more than the pre-determined number of program pulses to complete programming to multiple bits per memory cell (block 314 of FIG. 3 verifies a number of programming pulses to MLC is equal or greater than a limit, par. 33); and a determination of proceeding a program operation followed without a program verify for those candidate groups that completed programming to multiple bits per cell within the pre-determined number of program pulses (block 314 of FIG. 3 verifies a number of programming pulses to MLC is less than a limit, par. 33).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the determination for programming Yang (1050, FIG 10) with the determination of checking the programming speed via program pulses of the MLC pages to have the system determine the appropriate programming with or without verify to save time due to the faster operation when verify operation is skipped (Yang par. 66).
Regarding claim 11: Yang discloses a method for operating NAND memory (NAND memory device, par. 43), wherein programming the block of the NAND memory cells to a single bit per memory cell group by group further includes: applying one or more program pulses followed by a program verify (program-verify after program pulse 1030 of FIG. 10) for each of the one or more program pulses for any groups that are not candidates for programming to a single bit per cell without verify (determination 1020 of FIG. 10 as not candidate).
Regarding claim 16: Yang discloses a non-volatile memory system (non-volatile storage system 100), comprising: a plurality of three-dimensional blocks (non-volatile memory 104 comprises blocks of NAND flash memory cells in a three dimensional configuration, par. 51, FIG. 2A) comprising NAND strings and word line associated with the NAND strings (NAND memory array composed of multiple strings of memory and connected word lines, pars. 77 and 80); and one or more control circuits (controllers 102, FIGs. 1 and 2A) in communication with the plurality of three-dimensional blocks, (controllers 102 connected to memory 104, FIG. 1 and 2A) the one or more control circuits configured to: maintain a pool of hybrid blocks (blocks of memory comprised of NAND flash memory cells, par. 51, FIG, 2A) that are eligible for multi-level cell (MLC) programming and single-level cell (SLC) programming (memory cells can be programmable as SLC or MLC, par. 41); select a hybrid block from the pool for SLC programming (begins SLC programming and checks block, 1005 of FIG. 10); and based on a speed criterion of programming speed, program candidates to a single bit per memory cell with program verify (1070 of FIG. 10) or program candidates to a single bit per memory cell without program verify (1060 of FIG. 10).
Yang does not disclose tracking MLC programming speed for candidates selection for SLC programming; and a speed criterion for determination of the candidate to be programmed to SLC with or without verify.
Huang does disclose a device for programming non-volatile memory (200), comprising: track MLC programming speed (speed determined by number of programming pulses within a limit, 314 of FIG. 3); and has a determination for a speed criterion of programming speed to program candidates who completed MLC programming slower than a criterion (block 314 of FIG. 3 verifies a number of programming pulses to MLC is equal or greater than a limit, par. 33) and a speed criterion of programming speed who completed MLC programming at least as fast as the criterion (block 314 of FIG. 3 verifies a number of programming pulses to MLC is less than a limit, par. 33).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the determination for programming Yang (1050, FIG 10) with the determination of checking the programming speed via program pulses of the MLC pages to have the system determine the appropriate programming with or without verify to save time due to the faster operation when verify operation is skipped (Yang par. 66).
Regarding claim 17: Yang discloses a non-volatile memory system (non-volatile storage system 100), wherein: based on a predetermined criterion, program candidate pages (SLC programming 1005, FIG. 10) to single bit per memory cell with program verify (1070, FIG. 10) or without program verify (1060, FIG. 10).
Yang does not disclose the criterion comprises a pre-determined number of program loops.
Huang does disclose a device for programming non-volatile memory (200), comprising: a criterion comprises a pre-determined number of program loops ((speed determined by number of programming pulses within a limit similar to number of program pulses per loop, 314 of FIG. 3); and a determination for a speed criterion of programming speed to program candidates who completed MLC programming slower than a criterion (block 314 of FIG. 3 verifies a number of programming pulses to MLC is equal or greater than a limit, par. 33) and a speed criterion of programming speed who completed MLC programming at least as fast as the criterion (block 314 of FIG. 3 verifies a number of programming pulses to MLC is less than a limit, par. 33).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the determination for programming Yang (1050, FIG 10) with the determination of checking the programming speed via program pulses of the MLC pages to have the system determine the appropriate programming with or without verify to save time due to the faster operation when verify operation is skipped (Yang par. 66).
Allowable Subject Matter
Claims 4-8, 12-15, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having a determination of a threshold number or candidate pages/groups for eligibility of SLC programming as in claims 4, 14, and 18; maintain a dynamic list of the candidate pages that identifies a first set of the candidate pages that are slower than an MLC programming speed criterion to program to multiple bits per memory cell and a second set of the candidate pages that are at least as fast as the MLC programming speed criterion to program to the multiple bits per memory cell as in claims 6, 12, and 20; and moving blocks having at least one candidate group that completed MLC programming in more than the pre-determined number of program loops from the pool of hybrid blocks to a pool of MLC blocks that are eligible for MLC programming but are not eligible for SLC programming as in claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827