DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 23 January, 2026 has been entered.
Response to Amendment
Claims 1-20 remain pending in the application. Examiner acknowledges amendments to the claims which have necessitated further search and consideration. Upon review, the amended claims have been rejected under 35 USC § 103.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 11-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (U.S. Patent No. 9,946,462), hereinafter referred to as Li, in view of Yen et al (U.S. Patent Pub. No. 2020/0151108), hereinafter referred to as Yen, Kodama (U.S. Patent Pub. No. 2018/0276114), and Armangau et al (U.S. Patent Pub. No. 2020/0349082), hereinafter referred to as Armangau.
In regard to claim 1, Li teaches an apparatus, comprising: a controller associated with a memory device (Li Fig. 1, controller 106 associated with memory 102), wherein the controller is configured to cause the apparatus to: transfer, from a non-volatile memory to a local memory (Column 2, lines 52-57 apparatus of Fig. 1 includes memory 102 which may be non-volatile that stores mapping entries 110; Column 4, lines 41-52 updating a mapping table includes transferring compression unit to buffer 105 in CDC 104 which may be implemented within controller, see Fig. 8), regions of an address mapping (Column 3, lines 19-23 compression units are mapping table regions) that are associated with a first amount of data received from a host system (Column 14, lines 62-65 a controller can select mapping to update based on data being stored to flash memory; Fig. 8 shows apparatus connected to host device; Column 17, lines 54-62 disclose communication between host and storage apparatus; storing new data functionally requires receiving data at the apparatus from host); update the regions of the address mapping with physical address information for the first amount of data (Column 4, lines 53-56) based at least in part on a changelog that indicates physical addresses associated with the first amount of data (Column 14, lines 62-65 mapping entry may be updated based on changes to physical address mapping, functionally requires recording some changelog of physical address; Column 15, lines 8-13 physical die address may be updated e.g. after being recorded as a change); compress the regions of the address mapping in the local memory based at least in part on updating the regions (Fig. 4 steps 414 to 424), and wherein a bit value is modified based at least in part on the regions being compressed by a threshold factor (Column 9, lines 30-38 disclose modifying a metadata indicator (e.g. some bit value) based on successful compression i.e. a threshold compression ratio of at least greater than 1).
Li does not teach modifying a bit value to indicate that transfer of the regions to the non-volatile memory is to be delayed until after at least one of the regions has been updated again, however Yen Paragraph 0090 teaches preventing writing updates to L2P mapping data is until the updated data count value (see Fig. 9C) is at a threshold e.g. the data count is a bit value modified to indicate transfer should be delayed until it reaches a certain value. When combined with the disclosure of Lin after compression has already occurred, the claimed limitation is achieved. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Yen in order to prevent poor efficiency in mapping table updates (Yen Paragraph 0090, lines 18-22).
The previously cited references do not teach an embodiment including a controller with local memory for mapping data or modifying a bit value associated with regions based on a threshold compression ratio. However, Kodama ¶ 0021-0022 disclose that mapping data is stored in DRAM 5 shown in Fig. 1 and ¶ 0028 discloses that the DRAM is connected to an internal bus along with internal components of the memory controller i.e. the DRAM is local, achieving the limitations of a memory controller with local memory for L2P mapping if the controller is used with the disclosures of Li and Yen. This localized DRAM allows for the disclosure of Kodama to store firmware for operation as well as mapping data in a single memory (see ¶ 0033 where firmware is loaded onto DRAM and L2P mapping is also updated on DRAM), which would inevitably reduce complexity and cost by eliminating an additional component (as the disclosure of Li Fig. 1 already includes a memory in the controller, but not explicitly for L2P storage, as well as other memories separately connected). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine this aspect of Kodama with previously cited references in order to gain the expected advantage of a reduced cost and complexity of implementing the disclosure by reducing the required number of memory modules. Additionally, Kodama ¶ 0053 and ¶ 0060 disclose different modes of operation for compressed L2P data (see ¶ 0052) based on whether a compression threshold is reached, wherein the threshold is measured using a ratio (e.g. factor). If the determination capability of Kodama's disclosure is combined with the bit value of Yen which delays transfers, the claimed limitation is achieved. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Kodama in order to ensure compression thresholds are reached to maximize storage efficiency and improve efficiency of nonvolatile memory (¶ 0014).
The previously cited references do not teach specific checkpoint procedures for flushing data to and from volatile memory, however Armangau ¶ 0035 teaches keeping mapping data from being flushed after a first cache processing cycle until another processing cycle is performed (via setting a flag or indicator), achieving the claimed limitation as well as accurately capturing an inventive concept of the instant application. A person of ordinary skill could easily incorporate this with the update counter and compression threshold of previous references to achieve the claimed embodiment wherein compressed mapping data is held between volatile memory flushes. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Armangau to enable mapping structures to be populated more fully, promoting efficient cache utilization (¶ 0005, lines 20-22).
As for claim 2, the previously cited references teach the apparatus of claim 1. Additionally, Li discloses canceling operation if there are no mappings to update (Column 11, lines 43-45; i.e. threshold quantity of one), and compressing regions based on there being at least one to update (Fig. 4, steps 414-426), achieving the claimed limitation.
As for claim 3, the previously cited references teach the apparatus of claim 1, and the combination of Li and Yen is capable of updating multiple mapping regions when necessary (Yen Paragraph 0090, multiple logical unit mappings are updated), achieving the claimed limitation.
As for claim 4, the previously cited references teach the apparatus of claim 3. Additionally, Li Fig. 4 shows transferring regions back (step 422) to the compressed mapping table (which may be non-volatile; Column 2, lines 52-57) only after updating a selected mapping (step 414), achieving the claimed limitation.
As for claim 5, the previously cited references teach the apparatus of claim 3. Additionally, Li Fig. 4 shows transferring regions back (step 422) to the compressed mapping table (which may be non-volatile; Column 2, lines 52-57) only after decompressing them in the decompression circuit (step 414; included in controller in Fig. 8; stores entries in buffer 105), achieving the claimed limitation.
As for claim 6, the previously cited references teach the apparatus of claim 3. Additionally, Li Fig. 6 shows decompressing a region to be modified (step 604, step 610) and updating the region based on it being decompressed (steps 614-616), achieving the claimed limitation.
As for claim 11, the previously cited references teach the apparatus of claim 1. Additionally, Li discloses a flag indicating regions of an address mapping are compressed (Column 9, lines 30-38 disclose modifying a metadata indicator (e.g. some bit value) based on successful compression), achieving the claimed limitation.
As for claim 12, Li teaches a non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor (Column 2, lines 43-47). Applicant is directed to the rejection of claim 1 above for remaining limitations, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 13, the previously cited references teach the medium of claim 12. Applicant is directed to the rejection of claim 2 above for remaining limitations, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 14, the previously cited references teach the medium of claim 12. Applicant is directed to the rejection of claim 3 above for remaining limitations, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 15, the previously cited references teach the medium of claim 14. Applicant is directed to the rejection of claim 4 above for remaining limitations, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 16, the previously cited references teach the medium of claim 14. Applicant is directed to the rejection of claim 5 above for remaining limitations, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 17, the previously cited references teach the medium of claim 14. Applicant is directed to the rejection of claim 6 above for remaining limitations, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 20, Applicant is directed to the rejection of claim 1 above, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
Claims 7-10 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Li, Yen, Kodama, Armangau, and Cariello et al (U.S. Patent Pub. No. 2022/0188237), hereinafter referred to as Cariello.
In regard to claim 7, the previously cited references teach the apparatus of claim 3. They do not teach the remaining limitations of claim 7. However, Cariello teaches storing mapping regions in volatile memory associated with a controller (Paragraph 0060), and transferring additional regions associated with some data (Paragraphs 0062-0063), after which regions may be transferred back to non-volatile memory (Paragraph 0069, lines 5-7; Fig. 3 PVT flush may occur after retrieving additional mappings and before continuing update operations), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Cariello in order to update mappings continuously and increase unmap command performance (Cariello Paragraph 0011, lines 1-3).
As for claim 8, the previously cited references teach the apparatus of claim 7. Additionally, Cariello teaches storing mapping regions in volatile memory associated with a controller (Paragraph 0060), and transferring additional regions associated with some data only if the memory device has enough space (e.g. satisfying a condition; Paragraphs 0062-0063), achieving the claimed limitation.
As for claim 9, the previously cited references teach the apparatus of claim 1. They do not teach the remaining limitations of claim 9. However, Cariello teaches storing mapping regions in volatile memory associated with a controller (Paragraph 0060), and transferring regions associated with some data only if the memory device has enough space (e.g. satisfying a threshold amount of data; Paragraphs 0062-0063), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Cariello in order to update mappings continuously and increase unmap command performance (Cariello Paragraph 0011, lines 1-3).
As for claim 10, the previously cited references teach the apparatus of claim 1. They do not teach the remaining limitations of claim 10. However, Cariello teaches transferring regions associated with some data only if a mapping change log is full (e.g. change log satisfying a threshold size; Fig. 3 step 315-345), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Cariello in order to update mappings continuously and increase unmap command performance (Cariello Paragraph 0011, lines 1-3).
As for claim 18, the previously cited references teach the medium of claim 14. Applicant is directed to the rejection of claim 7 above for remaining limitations, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 19, the previously cited references teach the medium of claim 18. Applicant is directed to the rejection of claim 8 above for remaining limitations, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
Response to Arguments
Applicant’s arguments (see page 8 of response filed 23 January, 2026) with respect to the rejections of amended claims 1-20 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further search and consideration, a new ground of rejection is made in view of Armangau. Armangau teaches a data mapping update procedure including keeping certain map data in volatile memory between cache processing cycles (e.g. checkpoint procedures), as addressed in the amended rejection of claim 1. These features may be readily combined with previously cited references to achieve the limitations of the amended claims. Additionally, previously cited reference Kodama was found to teach the newly added limitation of a required compression factor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Friday 8:30AM-5PM EST.
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/ZAKARIA MOHAMMED BELKHAYAT/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139