DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is in response to communications filed 07/12/2024.
Claims 1-22 are pending.
Claims 1-22 are rejected.
Priority
Applicant’s priority claim to provisional US Application 63/513,447 filed 07/13/2023 is herein acknowledged.
Information Disclosure Statement
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statements dated 03/20/2025, 09/08/2025, and 02/24/2026 are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), copies of the PTOL-1449s initialed and dated by the examiner is attached to the instant office action.
Drawings
The applicant’s drawings submitted on 07/12/2024 are acceptable for examination purposes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 18 recites “determine a fourth indicator of a group of the first set of groups indicator” where claim 17, from which claim 18 depends, already recites “receive a first indicator of a group of the first set of group indicator”. It is unclear whether antecedent basis is to be established between the recitations of the “group of the first set of group indicator” and whether the same group is to be referenced or different groups are being identified. For the purposes of the current action, it is interpreted that the same group is being referenced. Furthermore, the Examiner notes the inconsistency in the phrasing between the “first set of group indicator” as recited in claim 17 and the ”first set of groups indicator” recited in claim 18. Appropriate correction is required. Any additional consistency changes should be made across all claims where applicable.
Claim 22 recites “wherein the IC includes multiple instances of the decoder circuit … execute in parallel multiple processes that use the decoder circuit to determine …” It is unclear whether “the multiple instances” of the decoder circuit are used for executing in parallel the multiple processes or if one decoder circuit is capable of multiple parallel processes. For the current action, it is interpreted that the one decoder circuit is capable of parallel processing.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7, 9-14, 16-18, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Renno (US 2008/0276051).
Regarding claim 1, Renno teaches a circuit device comprising: a memory having a set of memory ranges; and a processor device coupled to the memory (Figure 1, microcontroller 103 and memory 107), wherein: the processor device includes a set of access protection registers (APRs) associated with a set of groups ([0024] In some implementations, attributes of different portions of memory 108 can be applied to configurable regions or sub-regions of fixed or variable size that can be configurable through the memory protection unit 102. In particular, for example, the memory protection unit 102 can include registers 110, which can be configured to specify a location for each memory region or sub-region within a device's overall memory map.); each APR of the set of APRs is configured to store: a respective permission for a respective memory range of the set of memory ranges; and a respective permission for each group of the set of groups ([0026] Other registers can store memory protection attributes that are applied to the various regions and sub-regions. For example, one or more registers can store values that specify whether particular regions or sub-regions are accessible for read, write or execution access (e.g., accessibility parameters).); and the processor device is configured to: receive an instruction from the memory that is associated with a target address; and determine a permission associated with the instruction based on: a first APR of the set of APRs that is associated with the target address of the instruction; and the respective permission, stored by the first APR, for a first group of the set of groups that is associated with the instruction ([0029] In some implementations, the memory protection unit 102 can be employed each time a memory access attempt or request is made (e.g., by the execution unit 104 executing program instructions). For example, if the execution unit 104 executes a read instruction directed to a specific address in instruction memory 114, the memory protection unit 102 can identify a configured region and sub-region (e.g., a region or sub-region within the memory map that is characterized by values in the registers 110) that includes the specific address. The memory protection unit 102 can then determine which set of memory protection attributes (e.g., memory protection attributes 130 or 132) are to be applied to the relevant region and sub-region. Based on the appropriate set of memory protection attributes, the memory protection unit 102 can determine whether to allow or inhibit the memory access.). Herein Renno teaches a memory protection configuration wherein a memory controller comprises circuitry for managing memory region and sub-region access. Herein the region and sub-region classifications are determined as analogous to the recited set of memory ranges and set of groups as claimed as both sets of terms refer to organized portions of memory. Furthermore, Renno teaches maintaining a plurality of registers storing memory protection attributes which control access to the memory portions thereof which may be referenced in response to receiving memory access request to the respective specific address included in the region and sub-region. In this manner, Renno discloses the claim limitations as currently recited.
Regarding claim 7, Renno further teaches the circuit device of claim 1, wherein: each APR of the set of APRs is configured to store read/write (R/W) permissions for each group of the set of groups; and the processor device is configured to determine whether to permit an access of the target address based on the R/W permissions stored by the first APR of the set of APRs that is associated with the target address ([0023] In some implementations, the memory protection unit 102 can be used to control the above-described operations. For example, the memory protection unit 102 can employ memory protection attributes to determine whether program instructions from a particular portion of memory 108 can be executed, or whether data can be read from or written to other portions of memory 108. In addition to controlling read, write or execute-access to portions of memory 108, the memory protection unit 102 can be employed to control whether data or instructions in various portions of memory 108 are bufferable or cacheable. [0040] The protection regions can be of different sizes. In the implementation shown in FIG. 3, the size of each region is characterized by a corresponding address register. In particular, for example, the size of region 312 can be specified by size bits 326 in address register 324. Similarly, the size of region 302 can be specified by size bits 328 in address register 322. In some implementations, memory regions can be defined to cover the entire memory map 200. In other implementations, memory regions may be defined that only cover a portion of the memory map 200.). Herein Renno explicitly identifies maintaining read and write permissions for respective portions of memory based on address. Additionally, further attributes including caching are discussed.
Regarding claim 9, Renno teaches an integrated circuit (IC) comprising: a first memory having a set of address ranges and configured to store an instruction that requests a memory access to a memory location (Figure 1, microcontroller 103 and memory 107. Paragraph [0007] In some implementations, an embedded device includes, within a single device package, an execution unit configurable to execute program instructions; one or more memories that are configurable to store data and program instructions to be executed by the execution unit; and a memory protection unit that is configurable to receive a signal from the execution unit requesting access to a specific location in the one or more memories); a second memory including multiple access protection registers (APRs), each APR associated with and storing memory access and execution permissions information for a different one of the address ranges, different subsets of the APRs associated with different groups of a set of groups, wherein the permissions information is specified with respect to the groups of the set of groups ([0024] In some implementations, attributes of different portions of memory 108 can be applied to configurable regions or sub-regions of fixed or variable size that can be configurable through the memory protection unit 102. In particular, for example, the memory protection unit 102 can include registers 110, which can be configured to specify a location for each memory region or sub-region within a device's overall memory map.); a data access filter (Figure 6, Region Hit Check 604 and Privilege Check 616); and a processor configured to provide a first information that indicates the memory location to the second memory, and to provide a second information corresponding to the instruction to the data access filter; wherein the second memory is configured to, responsive to the first information, provide corresponding permissions information to the data access filter; and wherein the data access filter is configured to, responsive to the permissions information and the second information, determine whether to permit the memory access requested by the instruction to complete ([0029] In some implementations, the memory protection unit 102 can be employed each time a memory access attempt or request is made (e.g., by the execution unit 104 executing program instructions). For example, if the execution unit 104 executes a read instruction directed to a specific address in instruction memory 114, the memory protection unit 102 can identify a configured region and sub-region (e.g., a region or sub-region within the memory map that is characterized by values in the registers 110) that includes the specific address. The memory protection unit 102 can then determine which set of memory protection attributes (e.g., memory protection attributes 130 or 132) are to be applied to the relevant region and sub-region. Based on the appropriate set of memory protection attributes, the memory protection unit 102 can determine whether to allow or inhibit the memory access.). Herein Renno teaches a memory protection configuration wherein a memory controller comprises circuitry for managing memory region and sub-region access. Herein the region and sub-region classifications are determined as analogous to the recited set of memory ranges and set of groups as claimed as both sets of terms refer to organized portions of memory. Furthermore, Renno teaches maintaining a plurality of registers storing memory protection attributes which control access to the memory portions thereof which may be referenced in response to receiving memory access request to the respective specific address included in the region and sub-region. Renno discloses performing steps for checking memory region permissions which is determined as analogous to the data access filter as claimed. The memory and execution units are disclosed as being embodied in a single device package. In this manner, Renno discloses the claim limitations as currently recited.
Regarding claim 10, Renno further teaches the IC of claim 9, wherein the second information includes an indication of a source group of the set of groups corresponding to the instruction and a read/write access type of the memory access ([0023] In some implementations, the memory protection unit 102 can be used to control the above-described operations. For example, the memory protection unit 102 can employ memory protection attributes to determine whether program instructions from a particular portion of memory 108 can be executed, or whether data can be read from or written to other portions of memory 108. In addition to controlling read, write or execute-access to portions of memory 108, the memory protection unit 102 can be employed to control whether data or instructions in various portions of memory 108 are bufferable or cacheable.). Herein Renno teaches based on the requesting instruction identified privilege level, determined as analogous to the indication of the source group, the instruction may be permitted or denied access to the requested memory address.
Regarding claim 11, Renno further teaches the IC of claim 9, wherein the corresponding permissions information indicates which memory access permissions instructions fetched from memory ranges associated with each of the groups of the set of groups has with respect to a first address range ([0024] In some implementations, attributes of different portions of memory 108 can be applied to configurable regions or sub-regions of fixed or variable size that can be configurable through the memory protection unit 102. In particular, for example, the memory protection unit 102 can include registers 110, which can be configured to specify a location for each memory region or sub-region within a device's overall memory map. In some implementations, each region has a start address and size, based on values in a corresponding configuration register. In other implementations, each region has a start address and an ending address, which can be configured through a corresponding register or registers. In some implementations, each region has its own dedicated register or registers that characterize the region within the overall memory map. [0029] In some implementations, the memory protection unit 102 can be employed each time a memory access attempt or request is made (e.g., by the execution unit 104 executing program instructions). For example, if the execution unit 104 executes a read instruction directed to a specific address in instruction memory 114, the memory protection unit 102 can identify a configured region and sub-region (e.g., a region or sub-region within the memory map that is characterized by values in the registers 110) that includes the specific address. The memory protection unit 102 can then determine which set of memory protection attributes (e.g., memory protection attributes 130 or 132) are to be applied to the relevant region and sub-region.). Herein Renno teaches the respective region defined permissions based on the targeted address. Each register stores corresponding protection attributes to control access to the memory region.
Regarding claim 12, Renno further teaches the IC of claim 9, wherein the processor includes a third memory; and wherein the data access filter is configured to send a message to the processor responsive to the determine action; and wherein the processor is configured to, as a hardware process responsive to the message, block a data from being stored in one or more of the first memory or the third memory (Figure 7, [0067] The privilege check module 616 can then determine (box 722) whether the attempted access is allowed by the implemented memory protection policy. If so, the memory access can be allowed (box 724). If the attempted access is not allowed by the implemented memory protection policy, the memory access can be blocked or inhibited, and the memory protection unit may additionally generate an exception (box 726).). Herein Renno teaches as part of the processing flow, determining whether to allow a memory request access to a targeted address and if determined to not be allowed, the request is blocked. The plurality of memories as depicted in Figure 1 in system 100 including elements memory system 108 and registers 110 and system memory 107 are determined to be the respective first, second, and third memories as claimed. As noted in the rejection of claim 9, memory protection unit 102 performs the processing steps to determine whether to allow the request based on the memory region protection attributes stored in the respective region registers.
Regarding claim 13, Renno further teaches the IC of claim 9, wherein the processor is configured to control the instruction to be fetched from the first memory; wherein the first memory is configured to provide a source address from which the instruction is fetched to the second memory; wherein the second memory is configured to determine a source APR responsive to the source address; and wherein the second memory is configured to determine whether the instruction is executable code responsive to the source APR ([0023] In some implementations, the memory protection unit 102 can be used to control the above-described operations. For example, the memory protection unit 102 can employ memory protection attributes to determine whether program instructions from a particular portion of memory 108 can be executed, or whether data can be read from or written to other portions of memory 108. [0029] In some implementations, the memory protection unit 102 can be employed each time a memory access attempt or request is made (e.g., by the execution unit 104 executing program instructions). For example, if the execution unit 104 executes a read instruction directed to a specific address in instruction memory 114, the memory protection unit 102 can identify a configured region and sub-region (e.g., a region or sub-region within the memory map that is characterized by values in the registers 110) that includes the specific address. The memory protection unit 102 can then determine which set of memory protection attributes (e.g., memory protection attributes 130 or 132) are to be applied to the relevant region and sub-region. Based on the appropriate set of memory protection attributes, the memory protection unit 102 can determine whether to allow or inhibit the memory access.). Herein Renno teaches the instructions are determined by the memory protection unit 102 whether they are capable of being executed using the memory region protection attributes stored in respective registers.
Regarding claim 14, Renno further teaches the IC of claim 9, wherein the processor is configured to control the instruction to be fetched from the first memory; wherein the first memory is configured to provide a source address from which the instruction is fetched to the second memory; wherein the second memory is configured to determine a source APR and a source group of the set of groups associated with the source APR responsive to the source address; and wherein the second memory is configured to provide an identifier of the source group of the set of groups to the processor ([0023] In some implementations, the memory protection unit 102 can be used to control the above-described operations. For example, the memory protection unit 102 can employ memory protection attributes to determine whether program instructions from a particular portion of memory 108 can be executed, or whether data can be read from or written to other portions of memory 108. [0029] For example, if the execution unit 104 executes a read instruction directed to a specific address in instruction memory 114, the memory protection unit 102 can identify a configured region and sub-region (e.g., a region or sub-region within the memory map that is characterized by values in the registers 110) that includes the specific address. The memory protection unit 102 can then determine which set of memory protection attributes (e.g., memory protection attributes 130 or 132) are to be applied to the relevant region and sub-region. Based on the appropriate set of memory protection attributes, the memory protection unit 102 can determine whether to allow or inhibit the memory access.). Herein Renno teaches based on the corresponding region from the instruction is executed, associated protection region registers are accessed to provide the appropriate protection attributes relevant to the instruction in order to determine whether to enable access.
Regarding claim 16, Renno further teaches the IC of claim 9, wherein the address ranges correspond to a memory map of the first memory ([0024] In particular, for example, the memory protection unit 102 can include registers 110, which can be configured to specify a location for each memory region or sub-region within a device's overall memory map.). Herein Renno teaches the configuration of the memory regions as being respective of the overall device memory map.
Regarding claim 17, Renno teaches an integrated circuit (IC) comprising: a first memory having a set of address ranges (Figure 1, microcontroller 103 and memory 107. Paragraph [0007]); a second memory including access protection registers (APRs), each of the APRs configured to store an association with a respective address range, and configured to store an indicator of an associated group of a first set of groups ([0024] In some implementations, attributes of different portions of memory 108 can be applied to configurable regions or sub-regions of fixed or variable size that can be configurable through the memory protection unit 102. In particular, for example, the memory protection unit 102 can include registers 110, which can be configured to specify a location for each memory region or sub-region within a device's overall memory map.); a third memory configured to store an association between subsets of the first set of groups and a corresponding group of a second set of groups ([0025] Each region can further include sub-regions. In some implementations, a fixed number of sub-regions (e.g., three, four, eight, sixteen or some other number) are evenly distributed within a region, based on the size of the region and the number of sub-regions. In other implementations, a fixed number of sub-regions may be distributed in a different manner. In particular, for example, each region may include some sub-regions of a first size and other sub-regions of a second size. In still other implementations, the number and distribution of sub-regions within a region can also be configurable through values in corresponding registers.); a fourth memory configured to store an association between subsets of the second set of groups and a corresponding group of a third set of groups ([0027] Each set of memory protection attributes 130 or 132 can include attributes that specify accessibility parameters for each region and sub-region, attributes that specify bufferability parameters for each region and sub-region, and attributes that specify cacheability parameters for each region and sub-region. In some implementations, other memory attributes can be included in each set. [0028] In particular, in some implementations, the memory protection unit includes one selection register for each region of memory, and each selection register includes a field for each sub-region within the region. Each field can store a value that uniquely identifies one of the alternative sets of memory protection attributes. [0040] Configurable protection regions and [0059] Overlapping regions); a processor including an instruction pipeline, the instruction pipeline including multiple stages and a fifth memory; and a decoder circuit configured to receive a first indicator of a group of the first set of group indicator from the second memory, determine a second indicator of a group of the second set of groups using the third memory and the first indicator, determine a third indicator of a group of the third set of groups using the fourth memory and the second indicator, and provide the first indicator, the second indicator, and the third indicator to the fifth memory ([0029] In some implementations, the memory protection unit 102 can be employed each time a memory access attempt or request is made (e.g., by the execution unit 104 executing program instructions). For example, if the execution unit 104 executes a read instruction directed to a specific address in instruction memory 114, the memory protection unit 102 can identify a configured region and sub-region (e.g., a region or sub-region within the memory map that is characterized by values in the registers 110) that includes the specific address. The memory protection unit 102 can then determine which set of memory protection attributes (e.g., memory protection attributes 130 or 132) are to be applied to the relevant region and sub-region. Based on the appropriate set of memory protection attributes, the memory protection unit 102 can determine whether to allow or inhibit the memory access. And Figure 7 and corresponding disclosure). Herein Renno teaches a memory protection configuration wherein a memory controller comprises circuitry for managing memory region and sub-region access. As depicted in Figure 7, the controller performs a processing flow with multiple steps for receiving a memory access request and determining respective permissions of the access and whether to allow access. Paragraph [0053] further references the circuitry decoding the memory request to determine parameters. Herein the region and sub-region classifications are determined as analogous to the recited set of memory ranges and set of groups as claimed as both sets of terms refer to organized portions of memory. Furthermore, Renno teaches maintaining a plurality of registers storing memory protection attributes which control access to the memory portions thereof which may be referenced in response to receiving memory access request to the respective specific address included in the region and sub-region. The memory and execution units are disclosed as being embodied in a single device. The combination of elements which are referenced for processing the request including the plurality of regions, sub-regions, and corresponding attributes as determined by the memory controller and components embodied therein is determined to teach the recited elements of the first, second, third, fourth, and fifth memories and utilization thereof. These memories are respective to memory system 108, registers 110, memory system 107 as corresponding to the first memory to system 108, second, third, and fourth memories to registers 110, and the fifth memory to memory system 107. In this manner, Renno discloses the claim limitations as currently recited.
Regarding claim 18, Renno further teaches the IC of claim 17, wherein the processor is configured to control an instruction to be fetched from the first memory and to control a memory address from which the instruction is fetched to be provided to the second memory; and wherein the second memory is configured to determine a fourth indicator of a group of the first set of groups indicator responsive to the memory address, and to provide the fourth indicator to the third memory ([0028] Implementations that include multiple alternative sets of memory protection attributes can include a mechanism for specifying which of the multiple alternative sets of memory protection attributes are to be applied to specific regions or sub-regions. For example, as is described with reference to FIGS. 3, 4 and 6, some implementations include a selection register (or a selection field within a register) for each sub-region of memory, which specifies which of the alternative sets of memory protection attributes are to be applied to the corresponding sub-region. In particular, in some implementations, the memory protection unit includes one selection register for each region of memory, and each selection register includes a field for each sub-region within the region. Each field can store a value that uniquely identifies one of the alternative sets of memory protection attributes.). Herein Renno teaches in addition to the protection registers storing protection attributes including read/write access, each memory region may also be associated with alternative memory protection attributes stored in other registers corresponding to the region which may be accessed and the attributes therein applied to determining whether to enable the request or not. As best understood of the limitation, the alternative region attributes are determined as analogous as representing a fourth indicator of a group of the first set of group indicators as associated with the requested memory address which is then provided to the third memory.
Regarding claim 21, Renno further teaches the IC of claim 17, wherein each of the APRs is configured to store execution permissions information for the associated memory range, and is configured to store memory access rights to the associated memory range of the APR for each of the groups of the first set of groups ([0018] In some implementations, a device can include a memory protection unit that facilitates protection of individual portions of corresponding memory. Some memory protection units can support the configuration of various regions and sub-regions within an overall memory map, where each region or sub-region can have its own memory protection attributes (e.g., attributes that determine whether memory in the corresponding region or sub-region is cacheable, bufferable or accessible for one or more of reading, writing or executing). [0026] Other registers can store memory protection attributes that are applied to the various regions and sub-regions. For example, one or more registers can store values that specify whether particular regions or sub-regions are accessible for read, write or execution access (e.g., accessibility parameters).). Herein Renno teaches the respective memory protection registers store execution and access permissions.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3, 5-6, 19-20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Renno in view of McCarthy et al. (US 2013/0326193).
Regarding claim 2, Renno does not explicitly disclose the circuit device of claim 1, wherein: the set of groups is a first set of groups; the first set of groups are associated with a second set of groups; each group of the second set of groups is associated with a respective stack; and the processor device is configured to determine whether to permit a stack transition based on the second set of groups and on an instruction handshake. Regarding this limitation, McCarthy discloses in Paragraphs [0038] and [0042] “[0038] The peripheral address range indicator specifies a smallest address of a peripheral that user code may access, in an embodiment... Either way, the peripheral address range indicator defines a group of peripherals that is accessible only to supervisor code, and a group of peripherals that is accessible to both supervisor and user code. [0041] The core may then determine whether or not to allow the next instruction to be fetched and/or whether a state change that may be necessitated by the fetch is allowed. As mentioned previously, when the next instruction fetch address (e.g., an address based on the value in IFAR 117) is not within a memory region associated with the current privilege state, the core may be configured to allow a state change to occur and the next computer instruction to be fetched only when a transition from the current privilege state to the different privilege state is allowed. [0042] In an embodiment, when the current privilege state is the supervisor state, and the next instruction fetch address is within the user code memory region 218, the core may allow a "normal" transition from the supervisor state to the user state (and may allow the next instruction to be fetched) only in response to a "legal supervisor-to-user state transition event." ...” Herein McCarthy discloses the organization of performing a stack transition based on determination of whether a fetched instruction is permitted for execution. Specifically, the processing circuitry is involved in determining whether the next fetched instruction is executed in the current state or a transition is required. This determination is interpreted as analogous to the instruction handshake as claimed. The groups as discussed by McCarthy are analogous to the memory regions and sub-regions as disclosed by Renno wherein each region has corresponding protection attributes for access. McCarthy similarly allocates memory portions to corresponding portions of execution code wherein stacks are established which are provided with access protections. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the stack transition operations as disclosed by McCarthy with the memory implementation scheme as disclosed by Renno for providing protected memory regions with secure access (McCarthy [0025]). Renno and McCarthy are analogous art because they are from the same field of endeavor of managing protected memory region allocations.
Regarding claim 3, Renno and McCarthy in combination further disclose the circuit device of claim 2, wherein: the second set of groups is associated with a third set of groups; the processor device includes a permissions register configured to store a permission associated with the third set of groups; and the processor device is configured to determine whether to permit an operation based on the permission associated with the third set of groups stored in the permission register (McCarthy [0038] The peripheral address range indicator specifies a smallest address of a peripheral that user code may access, in an embodiment. Alternatively, the peripheral address range indicator may specify the largest address of a peripheral that only supervisor code may access. Alternatively, multiple peripheral address range indicators may be used to identify addresses of multiple groups of peripherals that may be accessible to user code, supervisor code, or both. Either way, the peripheral address range indicator defines a group of peripherals that is accessible only to supervisor code, and a group of peripherals that is accessible to both supervisor and user code.). Herein the range of address indicators which permit access by both supervisor and user code is determined to be analogous to the third set of groups which permit operation by either the supervisor or user code. Renno similarly discloses in Paragraph [0059] that address ranges may be provided to overlapping regions and therefore subject to protection attributes from either region.
Regarding claim 5, Renno and McCarthy in combination further disclose the circuit device of claim 3, wherein: each group of the first set of groups is associated with a LINK; each group of the second set of groups is associated with a STACK; and each group of the third set of groups is associated with a ZONE (Renno [0025] Each region can further include sub-regions. In some implementations, a fixed number of sub-regions (e.g., three, four, eight, sixteen or some other number) are evenly distributed within a region, based on the size of the region and the number of sub-regions. In other implementations, a fixed number of sub-regions may be distributed in a different manner. In particular, for example, each region may include some sub-regions of a first size and other sub-regions of a second size. In still other implementations, the number and distribution of sub-regions within a region can also be configurable through values in corresponding registers. And McCarthy [0035] and [0046]). Herein Renno and McCarthy disclose configuration of permissions across a plurality of regions further divided into sub-regions. McCarthy additionally discloses allocation of regions to code stacks. Under broadest reasonable interpretation of the claim language in view of the originally filed Specification, the regions and sub-regions as disclosed by Renno and McCarthy are determined to be analogous to the LINK, STACK, and ZONE designations as claimed. The permissions registers are groupings of various portions of memory which respective permissions are applied. It would be obvious to one of ordinary skill in the art to organize the regions into specified groupings based on the applicable permissions to be set for authorizing access into the respective region.
Regarding claim 6, Renno does not explicitly disclose the circuit device of claim 1, wherein: the instruction is a first instruction; each APR of the set of APRs is configured to store an executable indicator that indicates whether data stored in the respective memory range is executable; and the processor device is configured to determine whether to execute a second instruction based on the executable indicator stored by a second APR of the set of APRs associated with a memory range from which the second instruction is fetched. Regarding this limitation, McCarthy discloses in Paragraphs [0032-33] “[0032] The code memory regions (separated by one or more partitions) are defined using at least one "instruction address range indicator," in an embodiment. The address range indicator(s) define one or more first memory regions allocated for storing computer instructions associated with the supervisor state ("supervisor code"), and define one or more second memory regions allocated for storing computer instructions associated with the user state ("user code"). [0033] The instruction address range indicator specifies the base address for storage of user code within the code memory (e.g., within flash memory 160 or code memory 210), in an embodiment. Alternatively, the instruction address range indicator may specify the highest address (upper boundary) for storage of supervisor code within the code memory. Either way, the instruction address range indicator defines a boundary, in memory, between the supervisor code region and the user code region.” Herein McCarthy discloses maintaining address range indicators of memory regions indicating respective region allocation to particular execution instances. The system utilizes the indicators to determine whether the corresponding address belongs to the current execution state. The system thereby controls what code or instructions are allowed to execute. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the memory protected regions when performing code execution in order to prevent disallowed address access (McCarthy [0035]).
Regarding claim 19, Renno does not explicitly disclose the IC of claim 17, wherein the fifth memory is configured to store for each instruction in each stage of the instruction pipeline, a respective indicator of a group of the first set of groups, a respective indicator of a group of the second set of groups, and a respective indicator of a group of the third set of groups. Regarding this limitation, McCarthy discloses in Paragraph [0040] “In an embodiment, in conjunction with execution protection, an instruction address range indicator is stored in the user code BAR 212 (e.g., during system initialization or at other times), and the instruction address range indicator defines a partition 214 between a first memory region 216 allocated for storing supervisor code (a "supervisor code memory region"), and a second memory region 218 allocated for storing user code (a "user code memory region"). During system operation, the core (e.g., core 110) compares the address of each next instruction to be fetched (e.g., an address based on the value in IFAR 117) with the instruction address range indicator. When the comparison indicates that the address of the next instruction to be fetched falls within the first memory region 216, the core determines that the next instruction to be fetched is supervisor code. Conversely, when the comparison indicates that the address of the next instruction to be fetched falls within the second memory region 218, the core determines that the next instruction to be fetched is user code.” Herein McCarthy discloses as part of the processing flow, the core executing the access instruction manages address range indicators as part of the determination process of whether to allow or prevent instruction execution. As best understood of the limitation as claimed, the core, as depicted in Figure 1 as core 110, comprises processing accesses to memory as part of an instruction flow which includes both RAM 164 and FLASH 160. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to maintain a working set of information for an instruction execution in order to properly determine whether the instruction has appropriate access to the targeted address (McCarthy [0015]).
Regarding claim 20, Renno and McCarthy in combination further disclose the IC of claim 19, wherein the processor is configured to: compare the respective indicator of a group of the second set of groups corresponding to a first stage of the instruction pipeline to the respective indicator of a group of the second set of groups corresponding to a second stage of the instruction pipeline; and determine whether to execute an instruction in the second stage responsive to the compare action (Renno [0023] and McCarthy [0015]). Herein Renno and McCarthy disclose maintaining region and sub-region protection attributes for controlling access to targeted addresses. In view of the rejection of claim 19, from which claim 20 depends, the working memory as would be stored as part of the processing flow for accessing a target address, may be stored in RAM and used to verify whether permissions have been compared from the first and second set of groups for accessing the region accordingly.
Regarding claim 22, Renno does not explicitly disclose the IC of claim 17, wherein the IC includes multiple instances of the decoder circuit; and wherein the processor is configured to execute in parallel multiple processes that use the decoder circuit to determine one or more of a group of the second set of groups indicator or a group of the third set of groups indicator. Regarding this limitation, McCarthy discloses in Paragraphs [0047-48] “[0047] For example, although the flowchart depicts steps of updating the IFAR (block 306), fetching and decoding an instruction (block 314), and executing an instruction (block 318) in a sequential manner, it should be understood that, once a first instruction begins progressing through the instruction pipeline, certain of these processes may be performed in parallel in conjunction with executing a sequence of instructions. Those skilled in the art would understand how to implement the concepts inherent in the flowchart of FIG. 3 in a system that includes a pipelined architecture. [0048] As each instruction proceeds through the execution pipeline, the addresses in the IFAR and PC register are updated, and the next instruction is fetched, decoded, and executed.” Herein McCarthy discloses the capability of the system for processing instructions in the instruction pipeline in parallel. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide multiple instances of decoder circuitry such that processes may be performed in parallel including determining group indicators of the second or third set.
Claims 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Renno in view of McCarthy and further in view of Schulz et al. (US 2016/0283402).
Regarding claim 4, Renno and McCarthy do not explicitly disclose the circuit device of claim 3, wherein the operation includes at least one of a firmware update operation or a debug operation. Regarding this limitation, Schulz discloses in Paragraphs [0100] and [0102] “[0100] Trusted task A has permission to access authentication keys or other cryptographic keys in a secure ROM memory region 1112. Trusted task A also has permission to access a working memory space 1114, and region protection registers 1116 that define permissions to other memory spaces. The other memory spaces are memory regions that hold code for task D (1120) and OS 1140, along with the working spaces 1124, 1144 for those tasks. These permissions support the ability of trusted task A to provide software update and DRTM services to the OS and to task D. [0102] The permissions in registers 1116 (RPR #4) may be matched to procedures for typically invoking the OS, e.g., using context switches and/or interrupts. The permissions in registers 1146 may be matched to procedures for installing and/or updating software by the OS.” Herein Schulz discloses that permission registers are used to authorize software install or update procedures. The registers enable trusted software access to particular memory regions. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the memory protected regions when performing system changes in order to prevent inadvertent data changes (Schulz [0104]). Renno, McCarthy, and Schulz are analogous art because they are from the same field of endeavor of managing protected memory region allocations.
Regarding claim 8, Renno and McCarthy do not explicitly disclose the circuit device of claim 1, wherein the processor device is configured to allow a subset of the associations between the set of APRs and the respective memory ranges, and a subset of the associations between the set of APRs and the set of groups, to be changed responsive to execution of programmable instructions corresponding to a first group of the set of groups that is designated as a root-of-trust group, and not to allow the associations to be changed responsive to programmable instructions corresponding to other groups of the set of groups. Regarding these limitations, Schulz discloses in Paragraphs [0087-88] “[0087] Block diagram 900 in FIG. 9 illustrates an example in which the regulations presented in section 730 of FIG. 7 may be used to support dynamic root of trust (DRTM) examinations by trusted task A. In block diagram 900, a trusted task A (910) has been given access to root signatures or hashes or other confirming information for trust management in a secure ROM memory region 912. Trusted task A 910 also has been given access to a working memory space 914, and to region protection registers 916 that define permissions to other memory spaces. Those other memory spaces are memory regions that hold code for two other software elements, trusted task B (920) and trusted task C (930), along with the working spaces 922, 932 for those two trusted tasks. [0088] The confirmation may be supported by root information obtained from secure memory region 912. This confirmation may be performed before trusted tasks B or C are allowed to execute on a processor. In this context, trusted tasks B and C can be considered as measured trusted tasks. DRTM trusted task A may be provided with meta-data or other descriptive information about trusted tasks B and C, describing the permissions to be granted to those trusted tasks and the contents of each memory region to be allocated. DRTM trusted task A may furthermore implement a measurement facility and policy, describing which of the provided components of trusted tasks B and C to measure and how the measurements should be made.” Herein Schulz discloses trusted task A as being granted access to root signatures via dynamic root of trust. Trusted task A, analogous to the first group designated as a root of trust group, is therefore given authority over managed trusted tasks and is capable of authorizing execution thereof including any configuration changes. Specifically, the managed tasks must be confirmed using root information. Trusted task A additionally is permitted access to region protection registers. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the memory protected region access by executing instructions designated with root of trust when performing system changes in order to prevent inadvertent data changes (Schulz [0085]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Renno in view of Schulz.
Regarding claim 15, Renno does not explicitly disclose the IC of claim 9, wherein the processor is configured to allow the associations between the APRs and the memory ranges, and between the APRs and the groups of the set of groups, to be changed responsive to execution of programmable instructions corresponding to a group of the set of groups that is designated by hardware as a root-of-trust group of the set of groups, and not to allow the associations to be changed responsive to programmable instructions corresponding to other groups of the set of groups. Regarding these limitations, Schulz discloses in Paragraphs [0087-88] “[0087] Block diagram 900 in FIG. 9 illustrates an example in which the regulations presented in section 730 of FIG. 7 may be used to support dynamic root of trust (DRTM) examinations by trusted task A. In block diagram 900, a trusted task A (910) has been given access to root signatures or hashes or other confirming information for trust management in a secure ROM memory region 912. Trusted task A 910 also has been given access to a working memory space 914, and to region protection registers 916 that define permissions to other memory spaces. Those other memory spaces are memory regions that hold code for two other software elements, trusted task B (920) and trusted task C (930), along with the working spaces 922, 932 for those two trusted tasks. [0088] The confirmation may be supported by root information obtained from secure memory region 912. This confirmation may be performed before trusted tasks B or C are allowed to execute on a processor. In this context, trusted tasks B and C can be considered as measured trusted tasks. DRTM trusted task A may be provided with meta-data or other descriptive information about trusted tasks B and C, describing the permissions to be granted to those trusted tasks and the contents of each memory region to be allocated. DRTM trusted task A may furthermore implement a measurement facility and policy, describing which of the provided components of trusted tasks B and C to measure and how the measurements should be made.” Herein Schulz discloses trusted task A as being granted access to root signatures via dynamic root of trust. Trusted task A, analogous to the first group designated as a root of trust group, is therefore given authority over managed trusted tasks and is capable of authorizing execution thereof including any configuration changes. Specifically, the managed tasks must be confirmed using root information. Trusted task A additionally is permitted access to region protection registers. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the memory protected region access by executing instructions designated with root of trust when performing system changes in order to prevent inadvertent data changes (Schulz [0085]). Renno and Schulz are analogous art because they are from the same field of endeavor of managing protected memory region allocations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ono et al. (US 2007/0250675) – Paragraphs [0031-39] wherein protection register groups are discussed.
Shankar (US 2024/0330471) – Abstract wherein memory protection registers are discussed.
Cheng et al. (US 2024/0354427) – Abstract wherein data register protection groups are discussed.
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/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/ Supervisory Patent Examiner, Art Unit 2135
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