DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 2-3 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II (Claim 2) and Group III (Claim 3), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/17/2026. It should be noted that, claims 6-10 will be treated as cancelled when this application is in condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US PGPub No. 20170337008-A1) in view of Mundra et al. (US PGPub No.20200304464-A1), Mendes et al. (US Pub No. 20210357125-A1), and Renno et al. (US Pat No. 8051263-B2).
With respect to claim 1, Mochizuki teaches a circuit device comprising: (¶0027-0028: Figure 1 shows a semiconductor device 1, as the program is executed by the CPU 10, access to the hardware IPs 22 and 23 and shared memory 21 occurs. The semiconductor device 1 may include a memory controller, an internal memory, an input/output interface circuit. ) a memory having a set of memory ranges and configured to store instructions; a set of access protection registers (APRs) associated with a set of groups, (¶0033-0034: Figure 2 shows a block diagram of the hardware IP 22.As shown in Figure 2, the hardware IP 22 includes an information processing unit 31, a group of registers (hereinafter referred to as a “register group”) 32, a memory access command generation unit 33, and a memory protection unit 34. The information processing 31 performs a specific process according to an operation instruction provided from CPU 10. The register group 32 includes a plurality of registers. Further, access permission range address values provided from the CPU are stored in two of the plurality of register. Further, the access permission range address values include an access permission start address indicating a start address of an access permission range and an access permission last address indicating a last address of the access permission range. );
wherein each APR of the set of APRs is configured to store: a respective permission for a respective memory range of the set of memory ranges; and (¶0034: In the example shown in Figure 2, a processing instruction provided from the CPU 10 is stored in one of the plurality of registers. Further, data to be processed by the information processing unit 31, operation parameters used for the data process, and the like are also stored in registers included in the register group 32. Note that each of the hardware IPs 22 and 23 can specify an access permission range by using registers that store an access permission start address and an access permission area size, instead of using the registers storing the access permission start address and the access permission last address.);
Mochizuki does not disclose:
a first respective permission for each group of the set of groups;
Mochizuki does disclose a set memory of ranges and a set of address protection registers associated with a group, but Mochizuki does not disclose a set of groups, rather a singular group. However, Mundra teaches a first respective permission for each group of the set of groups; (¶0051-0052: Figure 4 shows a firewall module 400, consisting of two sub-modules, a Memory Mapped Register block (MMR blk) 404 and one or more Firewall Blocks (FW blk) 401 through 4nn connected to said MMR blk. multiple regions (up to 24), where each region is defined by an address range to be checked with the associated access permissions. The firewall module does concurrent checks of the incoming transactions with all enabled regions.) Further Figure 5 shows the firewall control registers for each region. There are at least 4 control registers for each region—registers 500, 506, 507 and 508.);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teaching of Mundra regarding a set of groups to the method of Mochizuki in order to better secure access by ensuring restricted access to protected regions (Mundra ¶0003).
Mochizuki in view of Mundra does not disclose:
a set of debug permission registers configured to store a second respective permission for each group of the set of groups; and a processor device coupled to the memory,
configured to execute the instructions, and configured to: receive a debug instruction that is associated with a target memory address and a debug action;
determine, based on the target memory address and using the set of APRs, the first respective permission for each group of the set of groups; and
determine, based on a debug credential and using the set of debug permission registers, the second respective permission for each group of the set of groups,
wherein the processor device includes a circuit configured to determine whether to permit the debug action based on the first respective permission for each group of the set of groups and the second respective permission for each group of the set of groups.
However, Mendes teaches a set of debug permission registers configured to store a second respective permission for each group of the set of groups; and a processor device coupled to the memory, (¶0037-0038: In one embodiment, debug port address manager 113 defines a number of dedicated slave addresses 242, 244, 246 (e.g., according to the I2C specification) associated with SMBus port 216. Each of the slave addresses can be separately addressed by host system 120 for different data and/or requests sent over SMBus 124. Debug slave address 246 can be one of multiple slave address associated with SMBus port 216, and can be dedicated for use in transferring debug information to host system 120. In one embodiment, debug slave address 246 is a static (i.e., default) address defined by debug port address manager 113 of memory sub-system 110.);
configured to execute the instructions, and configured to: receive a debug instruction that is associated with a target memory address and a debug action; (¶0016: With this address, the host system can issue firmware or hardware debug print events (i.e., requests to pull debugging information) to the memory sub-system. In response, the memory sub-system can provide a response including the requested debugging information sent to the host system over the SMBus. As further shown in ¶0056 and Figure 6, at operation 610, host system 120 sends a connection request to memory sub-system 110, including a request for a debug slave address 246 associated with SMBus port 216 of memory sub-system 110. In one embodiment, host system 120 sends a vendor specific command to memory sub-system 110 to request the debug slave address 246. );
determine, based on the target memory address and using the set of APRs, the first respective permission for each group of the set of groups; and (¶0078-0081 If the connection request included the privilege key, memory sub-system 110 can further authenticate the privilege key and identify a level of access (i.e., a privilege level) associated with the privilege key. A);
determine, based on a debug credential and using the set of debug permission registers, the second respective permission for each group of the set of groups, (¶0056: If the connection request included the privilege key, memory sub-system 110 can further authenticate the privilege key and identify a level of access (i.e., a privilege level) associated with the privilege key. As seen in Figure 7, at operation 705, the processing logic provides a privilege key to host system 120. In one embodiment, the privilege key has an associated level of access (i.e., privilege level) to debug information associated with memory sub-system 110. The privilege key thus indicates the type/level/amount of debug information to which the corresponding host system 120 is entitled. At operation 710, the processing logic receives a privilege key from host system 120. Depending on the embodiment, the privilege key can be received with a request for a debug slave address 246 associated with a system management bus port 216 of memory sub-system 110, received with a request to enable the system management bus port 216 to receive a request for debug information directed to the debug slave address 246, received with some other message, or received separately from any other message.);
wherein the processor device includes a circuit configured to determine whether to permit the debug action based on the first respective permission for each group of the set of groups and the second respective permission for each group of the set of groups. (¶0036-0040: As see
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teaching of Mendes of debug permission register to the method of Mochizuki in view of Mundra in order to prevent unauthorized access to the data stored in memory (Mendes ¶0014).
Mochizuki in view of Mundra and Mendes does not disclose:
determine, based on the target memory address and using the set of APRs, the first respective permission for each group of the set of groups; and
wherein the processor device includes a circuit configured to determine whether to permit the debug action based on the first respective permission for each group of the set of groups and the second respective permission for each group of the set of groups.
Within the context of Mochizuki in view of Mundra and Mendes, Mendes does disclose the debugging concepts in view of permissions/authorization, but Mochizuki in view of Mundra and Mendes does not disclose gaining permission based on the determination of first and second respective permissions. However, Renno teaches determine, based on the target memory address and using the set of APRs, the first respective permission for each group of the set of groups; and (¶0007: The method can further include determining a region and sub-region associated with the specific location in memory (target memory address). Determining the region associated with the specific location in memory can include comparing an address associated with the specific location to address values stored in one or more address registers. Determining the region associated with the specific location in memory can include comparing an address associated with the specific location to size values stored in the one or more address registers (first respective permission for each group of set of groups) . )
wherein the processor device includes a circuit configured to determine whether to permit the debug action based on the first respective permission for each group of the set of groups and the second respective permission for each group of the set of groups. (¶0007-0008: Determining the sub-region associated with the specific location in memory can include selecting a sub-region from a plurality of sub-regions in a determined region based on the address associated with the specific location and a size of the determined region (second respective permission of each group of the set of groups). Obtaining the selection value can include determining a specific portion of a selection register from which to obtain the selection value based on a determined sub-region. Further, exemplified ¶0022 and Figure 1 , if the execution unit 104 executes a read instruction directed to a specific address in instruction memory 114, the memory protection unit 102 can identify a configured region and sub-region (e.g., a region or sub-region within the memory map that is characterized by values in the registers 110) that includes the specific address (first and second respective permission) . The memory protection unit 102 can then determine which set of memory protection attributes (e.g., memory protection attributes 130 or 132) are to be applied to the relevant region and sub-region. Based on the appropriate set of memory protection attributes, the memory protection unit 102 can determine whether to allow or inhibit the memory access.);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teaching of Renno of permitting access based on the first respective permission for each group of the set of groups and the second respective permission for each group of the set of groups to the method of Mochizuki in view of Mundra and Mendes in order to prevent malicious actions such as data corruption via unauthorized access (Schulz ¶0004).
Conclusion
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/T.P.V./ Examiner, Art Unit 2437
/MENG LI/ Primary Examiner, Art Unit 2437
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