DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/26/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8-10, 12-15, 17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shah et al. (US 20030123231, hereinafter Shah) and further in view of Smith et al. (US 20020011859, hereinafter Smith).
Regarding to claim 1, Shah discloses a device for testing characteristics of a device under test (DUT), the DUT being a first bare chip, the device (abstract discloses debug and test operations) comprising:
a main printed circuit board (PCB) comprising a main circuit (fig. 1[40]);
a first interposer (fig. 1[50]) arranged on a surface of the main PCB (fig. 1[40]);
a second interposer (fig. 1[70]) arranged over the first interposer (fig. 1[50]) and the surface of the main PCB (fig. 1[40]), wherein the first bare chip and a second bare chip (fig. 1[60] as LGA packages or modules which indicates there are more than one) are arranged between the second interposer (fig. 1[70]) and the first interposer (fig. 1[50]) for testing the first bare chip (fig. 1[60]); and
at least one pressing plate configured to apply a pressing force against the second interposer for pressing the second interposer toward the first interposer and the main PCB (paragraph 0034 discloses heatsink 110 compresses onto the thermal interface 100 which in turn applies pressure to the LGA 60),
wherein the first interposer (fig. 1[50]) is configured to provide first electrical connections with the first bare chip, the second bare chip, and the main circuit by contact during the testing, without soldering (paragraph 0018 discloses each interposer contact bump includes electrically conductive surfaces that are shaped to abut a contact pad of the LGA package and a contact pad on the PCB),
wherein the second interposer (fig. 1[70]) is configured to provide second electrical connections with the first bare chip, the second bare chip, and the main circuit by contact during the testing, without soldering (paragraph 0018 discloses each interposer contact bump includes electrically conductive surfaces that are shaped to abut a contact pad of the LGA package and a contact pad on the PCB), and
wherein the pressing force applied by the at least one pressing plate enhances the first and second electrical connections during the testing of the first bare chip (abstract discloses debug and test operations and the pressing plate (heatsink) provide electrical contacts from the PCBs to the LGA packages).
Shah does not disclose to test the bare chip and the first bare chip and second bare chip.
Smith discloses an apparatus and method for testing bare singulated die (paragraph 0030) included a main printed circuit board (PCB) comprising a main circuit (fig. 7[90] or fig. 6 show pins 5 would connect to a circuit board);
a first interposer (fig. 7[44] or fig. 6[4]) arranged on a surface of the main PCB (fig. 7[90]);
a second interposer (fig. 7[80] or fig. 6[20c]) arranged over the first interposer (fig. 7[44]) and the surface of the main PCB (fig. 7[90]), wherein the first bare chip and a second bare chip (fig. 7[30 is a wafer included a plurality of bare chips]) are arranged between the second interposer and the first interposer (fig. 7[44]) for testing the first bare chip (fig. 7[80] or fig. 6[2]); and
at least one pressing plate configured to apply a pressing force against the second interposer for pressing the second interposer toward the first interposer and the main PCB (fig. 6 shows 20c being pressed by plate 20a to press bare die 2 mated with interposer 4 and fig. 7 shows 80 being pressed pushing 30 to 38 and 44 therefore it would has necessitated that there is a pusher to push 80).
Therefore, at the time before the effective filing date, it would be obvious to a POSITA to incorporate the test more than one bare chip in order to reduce cost.
Regarding to claim 2, Shah in view of Smith discloses the device of claim 1, further comprising: a plurality of alignment pins configured to align the main PCB, the first interposer, and the second interposer for the testing, while enabling the second interposer to move vertically relative to the first interposer to accommodate a thickness of the first bare chip and the second bare chip (Smith discloses alignment to provide precise electrical contacts and Shah and Smith both show the second interposer move vertically relative to the first interposer and It would has necessitated that the vertical move of the second interposer to move vertically relative to the first interposer to accommodate a thickness of the first bare chip and the second bare chip in order to make good contacts without damage the chips or the testing apparatus).
Regarding to claim 3, Shah in view of Smith discloses the device of claim 1, wherein each of the first interposer and the second interposer comprises a thin flexible substrate (fig. 1 of Shah shows thin flexible interposers).
Regarding to claim 8, Shah in view of Smith discloses the device of claim 1, except wherein at least the first bare chip comprises a wide bandgap (WBG) power device.
However, at the time before the effective filing date it would be obvious to a POSITA to test the bare chip comprises a wide bandgap (WBG) power device as a matter of intended use.
Regarding to claim 9, Shah in view of Smith discloses the device of claim 8, except wherein at least the first bare chip is a gallium nitride (GaN) field-effect transistor (FET) or a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET).
However, at the time before the effective filing date it would be obvious to a POSITA to test the bare chip as gallium nitride (GaN) field-effect transistor (FET) or a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) as a matter of intended use.
Regarding to claim 10, Shah in view of Smith discloses the device of claim 9, except wherein the second bare chip is a FET functioning as a transistor or as a diode.
However, at the time before the effective filing date it would be obvious to a POSITA to test the bare chip as a FET functioning as a transistor or as a diode as a matter of intended use.
Regarding to claim 12, Shah discloses a system for testing characteristics of the DUT, the system comprising: the device of claim 1; a test fixture configured to mount the device; and a pressing force assembly configured to apply the pressing force to the at least one pressing plate, which transfers the pressing force to the second interposer (see fig. 4 of Shah).
Regarding to claim 13, Shah in view of Smith discloses the system of claim 12, wherein the pressing force assembly comprises: a frame; a plurality of fasteners configured to physically attach the frame to the test fixture or the main PCB; and at least one set screw passing through the frame and configured to apply the pressing force to the at least one pressing plate upon operation (see fig. 6 of Smith).
Regarding to claim 14, Shah discloses a device for testing characteristics of a device under test (DUT), the DUT being a first bare chip (abstract discloses debug and test operations), the device comprising:
a main printed circuit board (PCB) comprising a main circuit (fig. 1[40]);
a first interposer (fig. 1[50]) arranged on a surface of the main PCB (fig. 1[40]);
a second interposer (fig. 1[70]) arranged over the first interposer (fig. 1[50]) and the surface of the main PCB (fig. 1[40]), wherein the first bare chip (fig. 1[60]) is arranged between the second interposer (fig. 1[70]) and the first interposer (fig. 1[50]) in a first orientation for testing of the first bare chip, and a second bare chip is arranged between the second interposer and the first interposer in a second orientation for the testing of the first bare chip, wherein the second orientation is opposite the first orientation (fig. 1[60] as LGA packages or modules which indicates there are more than one); and
at least one pressing plate configured to apply a pressing force against the second interposer for pressing the second interposer toward the first interposer and the main PCB (paragraph 0034 discloses heatsink 110 compresses onto the thermal interface 100 which in turn applies pressure to the LGA 60) to enhance electrical connections between each of the first and second bare chips (fig. 1[60] as LGA packages or modules which indicates there are more than one) and the first interposer (fig. 1[50]), between each of the first and second bare chips(fig. 1[60]) and the second interposer (fig. 1[70]), and between each of the first (fig. 1[50]) and second interposers (fig. 1[70]) and the main PCB (fig. 1[40]).
Shah does not disclose to test the bare chip and the first bare chip and second bare chip.
Smith discloses an apparatus and method for testing bare singulated die (paragraph 0030) included a main printed circuit board (PCB) comprising a main circuit (fig. 7[90] or fig. 6 show pins 5 would connect to a circuit board);
a first interposer (fig. 7[44] or fig. 6[4]) arranged on a surface of the main PCB (fig. 7[90]);
a second interposer (fig. 7[80] or fig. 6[20c]) arranged over the first interposer (fig. 7[44]) and the surface of the main PCB (fig. 7[90]), wherein the first bare chip and a second bare chip (fig. 7[30 is a wafer included a plurality of bare chips]) are arranged between the second interposer and the first interposer (fig. 7[44]) for testing the first bare chip (fig. 7[80] or fig. 6[2]); and
at least one pressing plate configured to apply a pressing force against the second interposer for pressing the second interposer toward the first interposer and the main PCB (fig. 6 shows 20c being pressed by plate 20a to press bare die 2 mated with interposer 4 and fig. 7 shows 80 being pressed pushing 30 to 38 and 44 therefore it would has necessitated that there is a pusher to push 80).
Therefore, at the time before the effective filing date, it would be obvious to a POSITA to incorporate the test more than one bare chip in order to reduce cost.
Shah in view of Smith disclose a second bare chip is arranged between the second interposer (fig. 1[50]) and the first interposer (fig. 1[57]) in the same orientation of the first bare chip instead of in a second orientation for the testing of the first bare chip, wherein the second orientation is opposite the first orientation.
Since the claim does not disclose criticality of having the second bare chip arranged between the second interposer and the first interposer in a second orientation for the testing of the first bare chip, wherein the second orientation is opposite the first orientation.
Therefore, at the time before the effective filing date, it would be obvious to a POSITA to have the second bare chip arranged between the second interposer and the first interposer in a second orientation for the testing of the first bare chip, wherein the second orientation is opposite the first orientation as matter of design choice without unexpected results.
Regarding to claim 15, Shah in view of Smith discloses the device of claim 14, further comprising: a plurality of alignment pins configured to align the main PCB, the first interposer, and the second interposer in a vertical direction for the testing of the first bare chip (Smith discloses alignment to provide precise electrical contacts and Shah and Smith both show the second interposer move vertically relative to the first interposer and It would has necessitated that the vertical move of the second interposer to move vertically relative to the first interposer to accommodate a thickness of the first bare chip and the second bare chip in order to make good contacts without damage the chips or the testing apparatus).
Regarding to claim 17, Shah in view of Smith discloses the device of claim 14, wherein each of the first interposer and the second interposer comprises a flexible substrate (fig. 1 of Shah shows thin flexible interposers).
Regarding to claim 19, Shah in view of Smith discloses the device of claim 14, except wherein the first bare chip is a gallium nitride (GaN) field-effect transistor (FET) or a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), and wherein the second bare chip is a FET functioning as a transistor or as a diode.
However, at the time before the effective filing date it would be obvious to a POSITA to test the bare chip as gallium nitride (GaN) field-effect transistor (FET) or a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) as a matter of intended use.
Regarding to claim 20, Shah discloses a method for testing a device under test (DUT) (abstract discloses debug and test operations), the method comprising:
arranging a first interposer (fig. 1[50]) on a surface of a main printed circuit board (PCB) (fig. 1[40]) comprising a main circuit;
arranging a first bare chip and a second bare chip on (fig. 1[60] as LGA packages or modules which indicates there are more than one) a surface of the first interposer (fig. 1[50]), wherein the first bare chip is the DUT (fig. 1[60]), wherein the first interposer (fig. 1[40] provides first electrical connections with the first bare chip, the second bare chip, and the main circuit by contact, without soldering (paragraph 0018 discloses each interposer contact bump includes electrically conductive surfaces that are shaped to abut a contact pad of the LGA package and a contact pad on the PCB);
arranging a second interposer (fig. 1[70]) arranged over the first bare chip (fig. 1[60]), the second bare chip (fig. 1[60]), the first interposer (fig. 1[50]) and the main PCB (fig. 1[40]), such that the first bare chip and a second bare chip (fig. 1[60]) are between the second interposer (fig. 1[70]) and the first interposer (fig. 1[50]) for testing of the first bare chip (fig. 1[60]), wherein the second interposer (fig. 1[70]) is configured to provide second electrical connections with the first bare chip, the second bare chip, and the main circuit by contact, without soldering (paragraph 0018 discloses each interposer contact bump includes electrically conductive surfaces that are shaped to abut a contact pad of the LGA package and a contact pad on the PCB);
arranging at least one pressing plate on at least one portion of the second interposer (paragraph 0034 discloses heatsink 110 compresses onto the thermal interface 100 which in turn applies pressure to the LGA 60);
applying a pressing force to the pressing plate for pressing the second interposer toward the first interposer and the main PCB, wherein the pressing force enhances the first and second electrical connections (paragraph 0034 discloses heatsink 110 compresses onto the thermal interface 100 which in turn applies pressure to the LGA 60); and
testing at least one characteristic of the first bare chip while applying the pressing force against the second interposer (abstract discloses debug and test operations and the pressing plate (heatsink) provide electrical contacts from the PCBs to the LGA packages).
Shah does not disclose to test the bare chip and the first bare chip and second bare chip.
Smith discloses an apparatus and method for testing bare singulated die (paragraph 0030) included a main printed circuit board (PCB) comprising a main circuit (fig. 7[90] or fig. 6 show pins 5 would connect to a circuit board);
a first interposer (fig. 7[44] or fig. 6[4]) arranged on a surface of the main PCB (fig. 7[90]);
a second interposer (fig. 7[80] or fig. 6[20c]) arranged over the first interposer (fig. 7[44]) and the surface of the main PCB (fig. 7[90]), wherein the first bare chip and a second bare chip (fig. 7[30 is a wafer included a plurality of bare chips]) are arranged between the second interposer and the first interposer (fig. 7[44]) for testing the first bare chip (fig. 7[80] or fig. 6[2]); and
at least one pressing plate configured to apply a pressing force against the second interposer for pressing the second interposer toward the first interposer and the main PCB (fig. 6 shows 20c being pressed by plate 20a to press bare die 2 mated with interposer 4 and fig. 7 shows 80 being pressed pushing 30 to 38 and 44 therefore it would has necessitated that there is a pusher to push 80).
Therefore, at the time before the effective filing date, it would be obvious to a POSITA to incorporate the test more than one bare chip in order to reduce cost.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shah in view of Smith as applied to claim 1 above, and further in view of Hamel et al. (US 20120249173, hereinafter Hamel).
Regarding to claim 11, Shah in view of Smith discloses the device of claim 1, except wherein the main circuit comprises at least a decoupling capacitor, a load inductor, and a bank capacitor.
However, it would be obvious to a POSITA to design a test circuit includes decoupling capacitor, a load inductor, and a bank capacitor as a well-known and conventional.
Furthermore, paragraph 0032 Hamel, discloses a modular test probe that includes integration of embedded or fully integrated components including but not limited to resistors, capacitors, inductors, or registers as well as assembly of discrete components including but not limited to resistors, capacitors, inductors, or registers to facilitate and/or enhance testing functions
Therefore, at the time before the effective filing date, it would be obvious to a POSITA to incorporate design a test circuit includes decoupling capacitor, a load inductor, and a bank capacitor which are basic required components of circuit.
Allowable Subject Matter
Claims 4-7, 16 and 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claims 4 and 18, the prior arts of record, alone or in combination, do not fairly teach or suggest “wherein the second interposer includes outer conductors on an outer surface, facing away from the first and second bare chips, wherein the outer conductors electrically connect the first and second bare chips to the main circuit, and wherein the thin flexible substrate of the second interposer acts as an insulator and enhances insulation voltage between the outer conductors on the outer surface of the second interposer and each of the first bare chip, the second bare chip, and the main circuit” including all of the limitations of the base claim and any intervening claims.
Claims 5-7 are objected for further limit claim 4.
Regarding to claim 16, the prior arts of record, alone or in combination, do not fairly teach or suggest “wherein the first bare chip is a first field effect transistor (FET) and the second bare chip is a second FET, wherein the first FET is arranged in the first orientation between the second interposer and the first interposer such a first drain electrode of the first FET is in contact with the second interposer, and a first source electrode, a first gate electrode and a first Kelvin source electrode of the first FET are in contact with the first interposer for the testing of the first FET, and wherein the second FET is arranged in the second orientation between the second interposer and the first interposer such a second drain electrode of the second FET is in contact with the first interposer, and a second source electrode, a second gate electrode and a second Kelvin source electrode of the second FET are in contact with the second interposer for the testing of the first FET” including all of the limitations of the base claim and any intervening claims .
Conclusion
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/SON T LE/ Primary Examiner, Art Unit 2858