DETAILED ACTION
Status of Claims
This action is in reply to the application filed on 07/12/2024.
Claims 1-20 are currently pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-9, 11-16, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kissell (US 2024/0378475 A1).
Claims 1, 8, and 15:
Kissell discloses the limitations as shown in the following rejections:
[Claim 8, 15] A computer device, comprising a processor and a memory, the memory/non-transitory computer-readable storage medium having a computer program stored therein that, when loaded and executed by the processor, causes the computer device to implement a quantum task execution method (FIG. 2; ¶0045, 0088-0090).
obtaining a logical quantum circuit, the logical quantum circuit being an abstract logic circuit configured to execute a quantum task (¶0030, 0041-0043).
generating a virtual quantum circuit (qubit configuration, compiled program for the quantum computation) of the quantum task according to topology information represented by a virtual quantum chip (abstract qubit surface) and the logical quantum circuit, the virtual quantum chip corresponding to a partial structure (region) in a physical quantum chip (“Regions of the array of qubits, e.g., subsets of qubits included in the array, are referred to herein as qubit surfaces”), the topology information (qubit geometry) being configured for representing a topology relationship between virtual qubits comprised in the virtual quantum chip (¶0044-0049, 0077) disclosing a compiler which produces a compiled program that specifies qubit geometry and required qubit surface to be used to perform the quantum computation that are abstracted (virtual) from the physical quantum chip.
“compiled program 210 can reference qubits included in the qubit configuration by relative grid addresses, e.g., beginning at 0.0…The compiled program 210 expresses the full physical parallelism possible for the program, independent of the resource constraints of a particular quantum processor” (¶0044).
“The program specifies an abstract qubit surface (also referred to herein as a first qubit surface) required to perform the quantum computation. The first qubit surface has a geometry that specifies a number of qubits required to perform the quantum computation and a type of qubit connectivity required to perform the quantum computation” (¶0077).
generating a physical quantum circuit (transpiled/transformed program) in the physical quantum chip for the quantum task according to the virtual quantum circuit and a bit mapping relationship between the virtual quantum chip and the physical quantum chip, the bit mapping relationship being configured for indicating physical qubits corresponding to the virtual qubits (logical qubits) in the physical quantum chip (¶0053-0057; 0068, 0071, 0074, 0081-0085) disclosing the method finds a region of the physical qubit array that matches the required qubit geometry and then uses a “transpiler to rewrite (and optimize) the control operations included in the binary program to match the constraints and characteristics of the available region” (¶0057) including mapping the abstract surface to a physical surface of the quantum processor where “the mapped qubit surface includes multiple pluralities of physical qubits, each plurality of the multiple pluralities corresponding to a respective logical qubit” (¶0085)
executing the physical quantum circuit through the partial structure in the physical quantum chip, to obtain an execution result of the quantum task (¶0064, 0070, 0086: “provides the transformed program to the available quantum processor to perform the quantum computation using the plurality of physical qubits in the mapped qubit surface”)
Claims 2, 9, and 16:
Kissell discloses the limitations as shown in the rejections above. Kissell further discloses: wherein the executing the physical quantum circuit through the partial structure in the physical quantum chip, to obtain an execution result of the quantum task comprises: executing a physical quantum circuit corresponding to a first quantum task through a first partial structure in the physical quantum chip, to obtain a first execution result corresponding to the first quantum task; and executing a physical quantum circuit corresponding to a second quantum task through a second partial structure in the physical quantum chip, to obtain a second execution result corresponding to the second quantum task, the first quantum task and the second quantum task being synchronously at the same time) executed different tasks, and the first partial structure (region) and the second partial structure having a relative independency relationship (do not interfere with one another) in the physical quantum chip (see at least FIG. 1, ¶0030-0031, 0057, 0064-0065) disclosing the scheduler allows multiple different requests to run on different regions and is configured to “select a qubit surface for each of the multiple binary programs such that the quantum processor 204 performs multiple quantum computations at the same time” (¶0064)…configured to select the multiple qubit surfaces such that noise and interference effects do not take an executing qubit surface out of specification” (¶0065).
Claims 4, 11, and 18:
Kissell discloses the limitations as shown in the rejections above. Kissell further discloses obtaining a logical quantum circuit comprises: obtaining task indication information (request for quantum computation), the task indication information being configured for indicating a target quantum task (information defining the quantum computation); determining, for any one of operation indications comprised in the task indication information, a first gate unit corresponding to the operation indication and at least one logical qubit on which the first gate unit is configured to perform logical processing; and performing, according to timing information (performance targets) of the operation indications comprised in the task indication information, timing association on the first gate units respectively corresponding to the operation indications, to generate the logical quantum circuit of the quantum task (see at least ¶0030, 0041-0043, 0053) disclosing the request includes information defining the quantum computation including control sequences of quantum gates to be applied to the qubits and computation time requirements:
“information that defines the quantum computation to be performed, e.g., data specifying the type of quantum computation and variables of the quantum computation. For example, the input data received by the quantum compiler 202 can include a request to solve a combinatorial optimization problem. In this example, the input data can include data specifying an objective function to be optimized and optionally one or more problem constraints (¶0041)…the input data 208 can also include data representing user-specified performance targets for the quantum computation to be performed, e.g., a maximum acceptable computational runtime, a minimum required computational accuracy or an error tolerance threshold, or a maximum acceptable cost” (¶0042).
Claims 5, 12, and 19:
Kissell discloses the limitations as shown in the rejections above. Kissell further discloses
obtaining request information (request for quantum computation) configured for establishing the virtual quantum chip; determining, according to the request information, the bit mapping relationship and requirement topology information of the virtual quantum chip, the requirement topology information being configured for representing the topology relationship required to be met between the virtual qubits comprised in the virtual quantum chip; and determining the partial structure (region) corresponding to the virtual quantum chip in the physical quantum chip according to the bit mapping relationship and the requirement topology information of the virtual quantum chip (see at least ¶0030, 0041-0043, 0049-0050, 0053, 0077) disclosing the request includes information defining the quantum computation including control sequences of quantum gates to be applied to the qubits and performance and timing requirements .
Claims 6 and 13:
Kissell discloses the limitations as shown in the rejections above. Kissell further discloses
determining, from the physical quantum chip according to the bit mapping relationship of the virtual quantum chip, to-be-mapped physical qubits respectively corresponding to the virtual qubits comprised in the virtual quantum chip; determining, when the to-be-mapped physical qubits are all in an unoccupied state (available, idle), a topology relationship between the to-be-mapped physical qubits according to a physical topology of the physical quantum chip; and determining, if the topology relationship between the to-be-mapped physical qubits meets the requirement topology information, a partial structure comprising the to-be-mapped physical qubits in the physical quantum chip as the partial structure corresponding to the virtual quantum chip in the physical quantum chip (see at least ¶0049-0051, 0057, 0060, 0074, 0079), e.g. The binding of logical qubits to physical qubits need not be static. In some implementations control systems of the quantum processor can set up and change bindings as necessary, given the requirements of the program and the constraints of the hardware.
Claims 7, 14, and 20:
Kissell discloses the limitations as shown in the rejections above. Kissell further discloses determining, according to the bit mapping relationship, physical qubits respectively corresponding to at least one virtual qubit comprised in the virtual quantum chip; and replacing each virtual qubit in the virtual quantum circuit with the physical qubit corresponding to the virtual qubit, to obtain the physical quantum circuit of the quantum task (¶0068, 0074, 0085):
transform the compiled program 210 by replacing relative qubit grid addresses included in the binary program with addresses of qubits in the suitable qubit surface…by replacing quantum computing operations on the first qubit surface to quantum computing operations on the mapped qubit surface. In some implementations generating the transformed program includes replacing relative qubit grid addresses in the program with addresses of qubits in the mapped qubit surface” (¶0085)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kissell in view of Niu et al. (“Enabling Multi-programming Mechanism for Quantum Computing in the NISQ Era”, 02/2023).
Claims 3, 10, and 17:
Kissell discloses the limitations as shown in the rejections above. Kissell further discloses generating the virtual quantum circuit in the physical quantum chip for the quantum task according to the second gate units respectively corresponding to the first gate units and a timing relationship of the first gate units in the logical quantum circuit (see at least ¶0041-0043) disclosing “user-specified performance targets for the quantum computation to be performed, e.g., a maximum acceptable computational runtime, a minimum required computational accuracy...control and measurement operations to be implemented by the quantum processor 204 when performing the quantum computation can include, e.g., control sequences of quantum gates to be applied to the qubits”.
Kissell does not specifically disclose determining, according to the topology information of the virtual quantum chip, second gate units respectively corresponding to first gate units in the logical quantum circuit, the first gate units being quantum gates configured to perform logical processing on logical qubits in the logical quantum circuit, and the second gate units being quantum gates configured to perform the same logical processing on the virtual qubits as the first gate units.
Niu, however, discloses an analogous method to implement multiprogramming on a quantum processor including a mapping algorithm which accounts for cross talk and teaches the limitation (pg. 7-9) determining, according to the topology information of the virtual quantum chip, second gate units respectively corresponding to first gate units in the logical quantum circuit, the first gate units being quantum gates configured to perform logical processing on logical qubits in the logical quantum circuit, and the second gate units being quantum gates configured to perform the same logical processing on the virtual qubits as the first gate units (see at least pg. 7-9:
“For the next circuit, a subgraph with the required number of qubits is assigned and we check if there is an overlap on this partition to partitions of previous circuits. If not, the subgraph is a partition candidate for the given circuit and the same process is applied to each subsequent circuit. To account for crosstalk, we check if any pairs in a subgraph have strong crosstalk effect caused by the allocated partitions of other circuits. If so, the score of the subgraph is adjusted to take crosstalk error into account. In order to evaluate the reliability of a partition, three factors need to be considered: partition topology, error rates of two-qubit links, and readout error of each qubit. One-qubit gates are ignored for simplicity and because of their relatively low error rates compared to the other quantum operations.”
It would have been obvious to one of ordinary skill in the art prior to the filing date of the invention to modify Kissell’s in view of Niu’s cross-talk aware quantum multiprogramming to “achieve crosstalk mitigation during simultaneous executions…improve the mapping transition step to execute multiple quantum circuits on quantum hardware with a reduced number of additional gates and better fidelity” Niu, pg. 3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
The following references are directed to quantum processor multitasking: US 20240061724 A1, US 20250036994 A1, S 20230342652 A1, US 20230102347 A1; “A Case for Multi-Programming quantum Computers, “Bringing the Concepts of Virtualization to Gate-based Quantum Computing”
Any inquiry of a general nature or relating to the status of this application or concerning this communication or earlier communications from the Examiner should be directed to Paul Mills whose telephone number is 571-270-5482. The Examiner can normally be reached on Monday-Friday 11:00am-8:00pm. If attempts to reach the examiner by telephone are unsuccessful, the Examiner’s supervisor, April Blair can be reached at 571-270-1014.
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/P. M./
Paul Mills
06/25/2026
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
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