Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
As per the instant application having Application No. 18/772,031, the amendment filed on 2/12/2026 is herein acknowledged. Claims 1, 3, 5, 11, 13 and 15 have been amended and claims 6 and 16 have been canceled. Claims 1-5, 7-15 and 17-20 are pending.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement(s) dated 12/17/2025 is/are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy (copies) of the PTOL-1449(s) initialed and dated by the examiner is/are attached to the instant office action.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 7-15 and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 1, the limitations “wherein the boundary is determined based on a distance from the third memory address” renders claim 1 indefinite as it is not clear where the claimed distance from the third memory address is from in order to determine the claimed boundary. Thus, the metes and bounds of the claimed boundary are unclear since other than reciting that the boundary is from the third memory address, the claim does not specify to where the boundary reaches. Other than reciting that the third memory address is based on a second memory address and modified based on the first memory address and that the addresses are associated with a first region, claim 1 does not clearly specify the order or locations represented by these addresses within the claimed region.
Additionally, regarding claim 1, it is not clear whether the limitations “identify a second memory address” in line 13 refer to the “one or more second memory addresses associated with the first region” of line 9 or to different second addresses.
Appropriate correction and/or clarification is required.
Independent claim 11 is rejected for the reasons indicated above with respect to claim 1.
Dependent claims 2-5, 7-10, 12-15 and 17-20 are rejected for encompassing the deficiencies found in the independent claims upon which they depend.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 7-8, 11-12 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Rafacz et al. (US 2017/0091104) in view of Roberts et al. (US 2022/0019530).
1. A storage device comprising: a first storage medium; a second storage medium; and [Rafacz teaches L1 cache 14, L2 cache 18 and memory 22 (fig. 1 and related text; par. 0028)]
a processor configured to: identify a first memory address of a memory access request; [Rafacz teaches “[0029] FIG. 2 schematically illustrates prefetch circuitry 30 in one embodiment. This prefetch apparatus 30 may for example be provided as the prefetch circuitry 16 in the data processing system 10 of FIG. 1. This prefetch apparatus 30 receives cache line load requests which include an access request address associated with the particular cache line being requested. Thus, where the cache storage device (such as the level one cache 14 shown in FIG. 1) receives an access request relating to a given data item from the core 12 (specified in terms of its memory address), it will initiate a cache line load request if it is determined that the required data item is not currently stored in that cache.”]
identify a first region of the first storage medium based on the first memory address; [Rafacz teaches “…The request tracking storage 38 is capable of storing a number of region entries, wherein each region entry corresponds to a range of memory addresses. The correspondence between memory addresses and regions is predefined, such that on receipt of an access request address the prefetch control circuitry 36 can determine the base address of the region to which it belongs…” (par. 0030)]
… track activity within a boundary of the first region, …[Rafacz teaches “[0030] The prefetch apparatus is also provided with tracking storage 38 and prefetch generation circuitry 40. Note that although the prefetch control circuitry 36 and tracking storage 38 are shown as separate components in FIG. 2, this is predominantly for clarity of illustration and the two may form a combined system component, for example where the prefetch control circuitry 36 is an extension of the control circuitry of the tracking storage 38. The request tracking storage 38 is capable of storing a number of region entries, wherein each region entry corresponds to a range of memory addresses. The correspondence between memory addresses and regions is predefined, such that on receipt of an access request address the prefetch control circuitry 36 can determine the base address of the region to which it belongs. For simplicity of illustration, the request tracking storage 38 shown in FIG. 2 only shows four region entries, but the request tracking storage is in no way constrained to only hold four region entries and the number of region entries is a system configuration parameter which may be freely set in dependence on the system requirements. On receipt of an access request address, the prefetch control circuitry 36 responds by comparing this access request address with the region information which it receives from the request tracking storage 38. This enables the prefetch control circuitry to determine if a region entry already exists in the request tracking storage corresponding to this access request address. The prefetch control circuitry 36 passes an indication of the access request address to the tracking storage 38, in which (in the embodiment shown in FIG. 2) each region entry stores access information associated with each region in the form of a marker which indicates whether a particular access request address within that region has been accessed. In the example of FIG. 2, the region entries in the request tracking storage 38 each correspond to 16 64-byte cache lines (and therefore each region corresponds to 1 kB of memory). Thus, when a cache line load request is received by the prefetch apparatus 30 in FIG. 2, where a corresponding region entry already exists for the region of memory to which this cache line load request belongs, then the request tracking storage 38 marks the corresponding access information in that region entry to show that access to this particular cache line has been carried out during the lifetime of this region entry within the request tracking storage.” (see par. 0031)]
identify a second memory address based on tracking activity within the boundary of the first region; and retrieve data associated with the second memory address from the first storage medium and store the data in the second storage medium [Rafacz teaches “no region entry currently exists within the request tracking storage 38 for the cache line load request which it has received, then a new region entry is allocated into the request tracking storage… The prefetch generation circuitry 40 then begins generating cache line prefetch request corresponding to the new region, either incrementing or decrementing through the region as appropriate.” (par. 0031; fig. 2 and related text) “The control circuitry 58 is configured to signal to prefetch generation circuitry that prefetch requests should be initiated for the access request address plus the stride length, namely in the expectation that the next access request address to be received will be that of the current access request address incremented by the stride length (thus, identifying a second address)” (par. 0032; fig. 3 and related text) “This prefetching is handled by the shifter 112 and the predicted prefetch generation 114, which creates entries in the prefetch (PF) generation table 108, indicating the cache lines (which include addresses) which should be prefetched and these are then forwarded to level 2” (par. 0033; fig. 4 and related text) where “These regions may be defined in terms of individual memory addresses at a finer level of granularity, or for example in terms of cache lines (each comprising a number of memory addresses) each defined by a corresponding starting memory address.” (par. 0013)]; thus identifying cache lines to prefetch based on a first request address includes identifying a second address from which to prefetch data based on the tracking of the access to the first region.
Rafacz does not expressly disclose “identify a third memory address of the first region based on one or more second memory addresses associated with the first region; modify the third memory address based on the first memory address; … wherein the boundary is determined based on a distance from the third memory address”; however, regarding these limitations, Roberts teaches [“[0050] In FIG. 1-1, the cache memory 106-2 is a consumer 115 of the access metadata 112 and may utilize the access metadata 112 to prefetch addresses of the backing memory 108. The adaptive tracking engine 110 can receive feedback pertaining to prefetch performance within respective regions covered by the access metadata 112 and can adjust the address ranges covered by the access metadata 112 for improved precision, resulting in more accurate address predictions with limited resource overhead. The adaptive tracking engine 110 may, therefore, improve memory I/O performance by, inter alia, enabling the cache memory 106-2 to improve prefetch performance, resulting in a lower cache miss rate… [0057] The update logic 224 is configured to update, refine and/or determine access metadata 112 in response to, inter alia, operations pertaining to addresses 202 covered by the access metadata 112. The access metadata 112 can be updated in response to any suitable type of operation, directive, message, command, and/or indication thereof to retrieve, modify, manipulate and/or otherwise access data (generally referred to as a command 201 herein) including, but not limited to: data access requests, read requests, write requests, copy requests, clone requests, trim requests, erase requests, delete requests, cache misses, cache hits, and/or the like (which correspond to a first memory address of a memory access request).”] “[0137]…The adaptive tracking engine 110 captures access metadata 112 pertaining to address regions covered by respective entries 211 of the dataset 210, as disclosed herein. The entries 211 can be updated in response to cache requests (which also correspond to access requests having a first memory address), such as cache hits, cache misses, and/or the like.” Thus, since the updates to the address ranges based on data access requests, which have a first address, which may include any of the accesses identified in par. 0057 or 0137, a third or bound address of the range is updated based on the access address or first address. Additionally, note the third address has not been defined within the claim such as to preclude this interpretation].
“track activity within a boundary of the first region, wherein the boundary is determined based on a distance from the third memory address” [“[0053] As illustrated in FIG. 2, the entries 211 of the access dataset 210 include access metadata 112 pertaining to specified address ranges. The access metadata entries 211 may, therefore, be configured as range entries 211, tracking entries 211, range tracking entries 211, access metadata tracking entries 211, and/or the like. An entry 211 may include any suitable information pertaining to the access metadata 112, including, but not limited to: range metadata 214 to specify the address range covered by the entry 211, access metadata 112 pertaining to the covered address range, and so on. The range metadata 214 may define covered address ranges using any suitable information including, but not limited to: address bounds, minimum and maximum address bounds (where the maximum address bound of the range may correspond to the third address associated with the accessed range as claimed), address tags, address tag bounds, minimum and maximum address tags, a base address and length, one or more tuples, and/or the like. The address range covered by an entry 211 may, therefore, be specified, defined, modified, and/or manipulated by, inter alia, writing one or more bits to the memory 208 (e.g., writing one or more bits to the range metadata 214 of the entry 211 maintained within the memory 208).” [0060] As disclosed in further detail herein, the management logic 226 of the adaptive tracking engine 110 may be configured to adjust the address ranges covered by the access metadata 112 and/or the size of such ranges in accordance with, inter alia, utility metrics 213 of the access metadata. In some examples, the address ranges covered by access metadata entries 211 having relatively high utility metrics 213 may be expanded, whereas the address ranges covered by entries 211 having relatively low utility metrics 213 may be contracted (or removed). Access metadata entries 211 that cover adjacent address ranges and have similar utility metrics 213 may be merged, thereby lowering overhead. In some aspects, address ranges and/or range sizes covered by respective access metadata entries 211 of the dataset 210 can be tuned in accordance with an adjustment policy. The adjustment policy may define thresholds and/or other criteria to trigger modifications to the set of address ranges covered by the access metadata 112, such as modifications to increase the size of one or more address ranges, decrease the size of one or more address ranges, merge one or more address ranges, split one or more address ranges, remove one or more address ranges, and/or the like. Alternatively, or in addition, the set of address ranges covered by the access metadata 112 may be adjusted in accordance with an optimization algorithm. The optimization algorithm may be configured to determine address ranges for respective entries 211 that produce optimal utility metrics 213 at minimal cost, which may be quantified in terms of resource requirements, management overhead, and/or the like.” “[0104]… the size of the address range covered by the modified access metadata entry 211-3 may be promoted from the smallest range size to the next larger range size of level 320-2. As illustrated in FIG. 5-5, the entry 211-3 is modified to cover a second-level address range {“0x662000”, “0x662FFF”} of node 311-6 rather than the smaller, first-level address range {“0x662100”, “0x6621FF”}.” (as address ranges may be shrunk, a third address within that range indicating a range bound may be modified to no longer belong within a given range or as ranges may be expanded, the ending or bound address corresponding to the range bound may be modified) thus, teaching a boundary as a distance from the third address to for example, the beginning of the range. Further note a maximum address bound of the region or range corresponding to the third address, is also determined based on the beginning of the range or a second address].
Rafacz and Roberts are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Rafacz to update the third memory address based on the first memory address and the first range of memory addresses associated with the first region as taught by Roberts since doing so would provide the benefits of [“[0060]… The adjustment policy may define thresholds and/or other criteria to trigger modifications to the set of address ranges covered by the access metadata 112, such as modifications to increase the size of one or more address ranges, decrease the size of one or more address ranges, merge one or more address ranges, split one or more address ranges, remove one or more address ranges, and/or the like. Alternatively, or in addition, the set of address ranges covered by the access metadata 112 may be adjusted in accordance with an optimization algorithm. The optimization algorithm may be configured to determine address ranges for respective entries 211 that produce optimal utility metrics 213 at minimal cost, which may be quantified in terms of resource requirements, management overhead, and/or the like.”].
Therefore, it would have been obvious to combine Rafacz with Roberts for the benefit of creating a storage system/method to obtain the invention as specified in claim 1.
2. The storage device of claim 1, wherein the first storage medium includes non-volatile memory and the second storage medium includes volatile memory [Rafacz teaches memory 22 corresponding to the first storage medium and caches 14, 18 corresponding to the second storage medium (fig. 1 and related text; par. 0028)] but does not expressly disclose the caches as volatile and memory 22 as non-volatile; however, it is well known in the art to implement caches which are used for temporary storage using volatile memory and main memory, such as memory 22 which is used for longer term storage as non-volatile memory, as evidenced by [Roberts “[0044] In example implementations, the apparatus 100 includes at least one host 102, at least one processor 103, at least one memory controller 104, and at least one cache memory 106. The apparatus 100 can also include at least one interconnect 105, and at least one backing memory 108. The backing memory 108 may represent main memory, system memory, backing storage, a combination thereof, and so forth. The backing memory 108 may be realized with any suitable memory facility including, but not limited to: a memory array, semiconductor memory, random-access memory (RAM), a Dynamic RAM (DRAM) device or module, a Static RAM (SRAM) device or module, a three-dimensional (3D) stacked DRAM device or module, Double Data Rate (DDR) memory, a Synchronous DRAM (SDRAM) device or module, a high bandwidth memory (HBM) device or module, a hybrid memory cube (HMC), and/or the like. Alternatively, or in addition, the backing memory 108 may be realized with a device or module including storage-class memory, such as a solid-state memory, Flash memory, 3D XPoint™ memory, phase-change memory (PCM), and/or the like. Other examples of the backing memory 108 are described herein. In some aspects, the host 102 can further include and/or be coupled to non-transitory storage, which may be realized with a device or module including any suitable non-transitory, persistent, solid-state, and/or non-volatile memory… [0182] The system 1700 may further include a memory 1708, which may include, but is not limited to: a memory, a memory device, a memory component, memory circuitry, a memory array, semiconductor memory, a memory bank, a memory chip, volatile memory, RAM, DRAM, SRAM, SDRAM, DDR memory, non-volatile memory, solid-state memory, a memory 208, a first memory 608, a second memory 618, and/or the like.”].
7. The storage device of claim 1, wherein the processor is further configured to: assign a first value to the first region based on the activity of the first region; determine, based on the first value, a first number of accesses to the second storage medium allotted to the first region [Rafacz teaches “…The request tracking storage 38 is capable of storing a number of region entries, wherein each region entry corresponds to a range of memory addresses. The correspondence between memory addresses and regions is predefined, such that on receipt of an access request address the prefetch control circuitry 36 can determine the base address of the region to which it belongs…” (par. 0030) “[0016] The access information may be stored in other ways (as an alternative, or in addition) and in some embodiments the plurality of region entries each comprise a counter and the access information in each region entry comprises a count value of the counter. Thus, when an access request address is received in association with an access request the counter for the region to which that access request address belongs is incremented to indicate that an access request address within this region has been accessed. The definition of the predetermined number may then be made with reference to a given counter value when the counter is examined.” (see pars. 0035-0036; fig. 5 and related text)].
8. The storage device of claim 7, wherein the processor is further configured to: identify an increase in the activity of the first region; assign a second value to the first region based on identifying the increase; and determine, based on the second value, a second number of accesses to the second storage medium allotted to the first region [The rationale in the rejection of claim 7 is herein incorporated. Note that the access counter for a region is incremented to a second value in response to increase activity/accesses and the second value representing the number of accesses to the first region].
11. A method comprising: identifying a first memory address of a memory access request; identifying a first region of a first storage medium based on the first memory address; identifying a third memory address of the first region based on one or more second memory addresses associated with the first region; modifying the third memory addresses based on the first memory address; tracking activity within a boundary of the first region wherein the boundary is determined based on a distance from the third memory address; identifying a second memory address based on the tracking of the activity of the first region; and retrieving data associated with the second memory address from the first storage medium and storing the data in a second storage medium [The rationale in the rejection of claim 1 is herein incorporated].
12. The method of claim 11, wherein the first storage medium includes non-volatile memory and the second storage medium includes volatile memory [The rationale in the rejection of claim 2 is herein incorporated].
17. The method of claim 11 further comprising: assigning a first value to the first region based on the activity of the first region; determining, based on the first value, a first number of accesses to the second storage medium allotted to the first region [The rationale in the rejection of claim 7 is herein incorporated].
18. The method of claim 17 further comprising: identifying an increase in the activity of the first region; assigning a second value to the first region based on identifying the increase; and determining, based on the second value, a second number of accesses to the second storage medium allotted to the first region [The rationale in the rejection of claim 8 is herein incorporated].
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Rafacz et al. (US 2017/0091104) in view of Roberts et al. (US 2022/0019530) as applied in the rejection of claim 1 above, and further in view of Sha et al. (US 2023/0205699).
3. The combination of Rafacz and Roberts teaches The storage device of claim 1, but does not expressly disclose wherein the processor is further configured to: compute a difference between the first memory address and the third memory address; and determine that the difference satisfies a threshold value; however, regarding these limitations, Sha teaches [“[0032] In one or more embodiments, memory may be managed using region-based memory management. In region-based managed memory, the memory may be organized in multiple memory regions (e.g., linear address regions), and each memory allocation is assigned to a particular memory region. This enables objects to be efficiently allocated, and allocated objects to be efficiently deallocated. In the example of computing system 100, main memory 130 is depicted with example memory regions 132(1)-132(b), which may be defined for a program to execute on processor 102. In one or more embodiments of region aware delta prefetching, each memory region may be divided into multiple subregions. For example, memory region 132(1) is shown with subregions 134(1)-134(c). Within each subregion, multiple cache lines may be stored. Any number (e.g., 0, 1, 2, etc.) of the cache lines in a subregion may be stored the caches, including L1 cache 122, at any given time, depending on which memory regions and subregions are being accessed by the program at that time. “ “[0036] In a region aware delta prefetcher 110, a delta value represents the distance from one cache line to another cache line within a subregion. Moreover, each delta value may be a positive or negative value.” “[0081] In one example scenario, three temporal offsets (or any other suitable number of temporal offsets) that can be used to identify the three most recently accessed cache lines in subregion 542(1) in an access map of the subregion entry 512(1), may be stored in subregion entry 512(1) as, for example, temporal offsets 252(1)-252(3). Accordingly, when a subsequent access to the subregion 542(1) is detected, the access map in subregion entry 512(1) can be updated to identify the cache line targeted by the subsequent access. A delta value can be calculated based on the difference between an offset to the bit in the access map identifying the cache line of the subsequent access and the first offset stored in subregion entry 512(1).” Where “. In one embodiment, delta values having the highest frequency of occurrence (or determined to satisfy a threshold) may be identified by sorting the delta values based on frequency values mapped to the delta values in the first subregion entry.” (par. 0099)].
Rafacz, Roberts and Sha are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Rafacz and Roberts to have the system/method of Rafacz e compute a difference between the first memory address and the third memory address; and determine that the difference satisfies a threshold value as taught by Sha since doing so would provide the benefits of allowing for “[0026] A region aware delta prefetcher, as disclosed herein, advantageously improves accuracy and performance. The combined spatial and temporal components of a RAD prefetcher offer significant advantages. Learning multiple deltas (spatial component) can increase the coverage of prefetches as the system is not limited to a single delta value for calculating memory addresses to be prefetched. Thus, having multiple deltas increases the number of predictions that are possible and therefore, prefetching coverage is increased. Additionally, learning these deltas per large address region, enables high accuracy.”.
Therefore, it would have been obvious to combine Rafacz and Roberts with Sha for the benefit of creating a storage system/method to obtain the invention as specified in claim 3.
13. The method of claim 11, wherein the first region is associated with a first range of addresses, the method further comprising: computing a difference between the first memory address and the third memory address; and determining that the difference satisfies a threshold value [The rationale in the rejection of claim 3 is herein incorporated].
Claims 4-5 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Rafacz et al. (US 2017/0091104) in view of Roberts et al. (US 2022/0019530) and Sha et al. (US 2023/0205699) as applied in the rejection of claims 3 and 13 above, and further in view of de la Iglesia et al. (US 2010/0115206).
4. The combination of Rafacz, Roberts and Sha teaches The storage device of claim 3, wherein the processor is further configured to: identify a second region based on the first memory address, wherein the second region is associated with a second range of addresses, wherein the second region is of a preset size [Rafacz teaches “The request tracking storage 38 is capable of storing a number of region entries, wherein each region entry corresponds to a range of memory addresses. The correspondence between memory addresses and regions is predefined, such that on receipt of an access request address the prefetch control circuitry can determine the base address of the region to which it belongs” (par. 0030) “The prefetch generation circuitry 40 then begins generating cache line prefetch request corresponding to the new region, either incrementing or decrementing through the region as appropriate.” (par. 0031; fig. 2 and related text) “The control circuitry 58 is configured to signal to prefetch generation circuitry that prefetch requests should be initiated for the access request address plus the stride length, namely in the expectation that the next access request address to be received will be that of the current access request address incremented by the stride length” (par. 0032; fig. 3 and related text) “This prefetching is handled by the shifter 112 and the predicted prefetch generation 114, which creates entries in the prefetch (PF) generation table 108, indicating the cache lines (which include addresses) which should be prefetched and these are then forwarded to level 2” (par. 0033; fig. 4 and related text) where “These regions may be defined in terms of individual memory addresses at a finer level of granularity, or for example in terms of cache lines (each comprising a number of memory addresses) each defined by a corresponding starting memory address.” (par. 0013) (par. 0033; fig. 4 and related text). Thus, identifying second areas/regions to prefetch including addresses as each line includes a number of memory addresses. Sha teaches “[0105] At 818, once the prefetch candidates (e.g., linear addresses of cache lines to be prefetched (corresponding to second regions associated with a second range of addresses)) have been identified, a certain number of the prefetch candidates may be selected to issue a prefetch request. For example, two prefetch candidates may be selected in one or more embodiments. This can ensure that the system can process the prefetches without significantly impacting performance.”], but the combination of Rafacz, Roberts and Sha does not expressly refer to the prefetch areas as second regions associated with a second range of addresses, where the second region is of a preset size; however, regarding these limitations, de la Iglesia teaches [“[0053] Referring to FIG. 5 and as discussed above, the storage device 20 may be partitioned in to multiple different blocks O-N each comprising a particular amount of storage space. Particular groups of blocks are logically grouped together into highly clustered address regions/areas 40 according to the previously monitored read and write access patterns by one or more clients 10 (FIG. 1) as described above in FIGS. 2-4. Each address region has a particular starting block address and a particular ending block address (and is thus considered of a preset size).” Where (fig. 8 and related text) where “[0071] FIG. 8 describes another pre-fetch scheme that can be used in conjunction or independently from the pre-fetch scheme described in FIG. 7. In FIG. 8, both the statistical record 220 and the historical record 240 are used to pre-fetch an address region different from the address region currently being accessed. “ “[0080] Any number of different address regions might be linked together and be triggered for prefetching based on an access to a particular address region. For instance, the example described above in FIG. 8 determined that address region 40B should be prefetched whenever address region 40A is accessed. However, the statistical record 220 and historical record 240 for address region 40Z may indicate that address region 40Z should be prefetched whenever address region 40B is accessed. Accordingly, the access to address region 40A may trigger the prefetching of both address region 40B and address region 40Z.”]; thus, also teaching a first address associated with second region representing an address range.
Rafacz, Roberts, Sha and de la Iglesia are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Rafacz, Roberts and Sha to have the second region identified for a first address prefetch areas as second regions associated with a second range of addresses, where the second region is of a preset size as taught by de la Iglesia since doing so would allow for the benefits of [“0079]… s dynamic determination of address regions/block clusters for contiguously accessed blocks of storage. These address regions are then dynamically analyzed to determine their suitability for prefetch operations whenever that particular address region is accessed. Different associations between the address regions are analyzed to determine if an address region, other than the currently accessed address region, should be prefetched.”]
Therefore, it would have been obvious to combine Rafacz, Roberts and Sha with de la Iglesia for the benefit of creating a storage system/method to obtain the invention as specified in claim 4.
5. The combination of Rafacz and Sha teaches The storage device of claim 4, wherein the second region includes the first region, wherein the processor is configured to identify the first region includes the processor being configured to: identify the second region based on the first memory address; and identify the first region based on the processor being configured to identify the second region [Sha teaches each region comprising subregions and “[0032] In one or more embodiments, memory may be managed using region-based memory management. In region-based managed memory, the memory may be organized in multiple memory regions (e.g., linear address regions), and each memory allocation is assigned to a particular memory region. This enables objects to be efficiently allocated, and allocated objects to be efficiently deallocated. In the example of computing system 100, main memory 130 is depicted with example memory regions 132(1)-132(b), which may be defined for a program to execute on processor 102. In one or more embodiments of region aware delta prefetching, each memory region may be divided into multiple subregions. For example, memory region 132(1) is shown with subregions 134(1)-134(c). Within each subregion, multiple cache lines may be stored. Any number (e.g., 0, 1, 2, etc.) of the cache lines in a subregion may be stored the caches, including L1 cache 122, at any given time, depending on which memory regions and subregions are being accessed by the program at that time.” Where lines and subregions accessed are included in a first region thus including a second region in the first region. “[0036] In a region aware delta prefetcher 110, a delta value represents the distance from one cache line to another cache line within a subregion. Moreover, each delta value may be a positive or negative value.” “[0081] In one example scenario, three temporal offsets (or any other suitable number of temporal offsets) that can be used to identify the three most recently accessed cache lines in subregion 542(1) in an access map of the subregion entry 512(1), may be stored in subregion entry 512(1) as, for example, temporal offsets 252(1)-252(3). Accordingly, when a subsequent access to the subregion 542(1) is detected, the access map in subregion entry 512(1) can be updated to identify the cache line targeted by the subsequent access. A delta value can be calculated based on the difference between an offset to the bit in the access map identifying the cache line of the subsequent access and the first offset stored in subregion entry 512(1).” “[0105] At 818, once the prefetch candidates (e.g., linear addresses of cache lines to be prefetched) have been identified, a certain number of the prefetch candidates may be selected to issue a prefetch request. For example, two prefetch candidates may be selected in one or more embodiments. This can ensure that the system can process the prefetches without significantly impacting performance. [0106] At 820, the selected prefetch candidates are used to issue prefetch request(s). The prefetched cache lines may be brought directly into the L1 cache in one or more embodiments.” Thus, identifying prefetch candidates based on an access to the subregion and also identifying the accessed subregion based on the processor configured to identify the prefetch candidates or second region] but the combination of Rafacz and Sha does not expressly refer to identify the second region based on the first memory address; and identify the first region based on the processor being configured to identify the second region; however, regarding these limitation, de la Iglesia teaches [“[0080] Any number of different address regions might be linked together and be triggered for prefetching based on an access to a particular address region. For instance, the example described above in FIG. 8 determined that address region 40B should be prefetched whenever address region 40A is accessed. However, the statistical record 220 and historical record 240 for address region 40Z may indicate that address region 40Z should be prefetched whenever address region 40B is accessed. Accordingly, the access to address region 40A may trigger the prefetching of both address region 40B and address region 40Z.”]; thus identifying a second region based on accesses to a first region and the first region is linked to the second region which includes identifying the first regions based on identifying the second region.
Rafacz, Sha and de la Iglesia are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Rafacz and Sha to identify the second region based on the first memory address; and identify the first region based on the processor being configured to identify the second region as taught by de la Iglesia since doing so would allow for the benefits of [“0079]… s dynamic determination of address regions/block clusters for contiguously accessed blocks of storage. These address regions are then dynamically analyzed to determine their suitability for prefetch operations whenever that particular address region is accessed. Different associations between the address regions are analyzed to determine if an address region, other than the currently accessed address region, should be prefetched.”]
Therefore, it would have been obvious to combine Rafacz with Sha and de la Iglesia for the benefit of creating a storage system/method to obtain the invention as specified in claim 5.
14. The method of claim 13 further comprising: identifying a second region based on the first memory address, wherein the second region is associated with a second range of addresses, wherein the second region is of a preset size [The rationale in the rejection of claim 4 is herein incorporated].
15. The method of claim 14, wherein the second region includes the first region, wherein the identifying of the first region includes: identifying the second region based on the first memory address; and identifying the first region based on the identifying of the second region [The rationale in the rejection of claim 5 is herein incorporated].
Claims 9-10 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Rafacz et al. (US 2017/0091104) and Roberts et al. (US 2022/0019530) as applied in the rejection of claim 7 above, and further in view of Dugast et al. (US 2022/0050722).
9. The combination of Rafacz and Roberts teaches The storage device of claim 7, but does not expressly disclose wherein the processor is further configured to: divide the first region into a second region and a third region, wherein the second region is allotted the first number of accesses to the second storage medium, and the third region is allotted the first number of accesses to the second storage medium; however, regarding these limitations, [Dugast teaches “ Hot pages can refer to memory pages with high-access frequency by a process or group of processes whereas cold pages can refer to memory pages with low-access frequency by a process or group of processes.” (par. 0070) “[0078] FIG. 14 depicts an example process. At 1402, determine access rates of pages of memory. For example, memory can include local memory to a processor that executes a process that accesses data from the pages as well as one or more network or fabric connected memory pools. At 1404, group pages within access rate buckets and associated pages within buckets with clusters. For example, kernel-space metadata on page accesses can be surfaced to a user space process and access rates for pages can be tracked. Pages with access rates that fit within a same window can be grouped into a same cluster. At 1406, an AI model can be trained based on access patterns to subclusters. For example, a cluster of data that does not include excluded categories (described earlier) can be divided into subclusters and hot and cold states of subclusters can be identified. Based on hot and cold states of subclusters, an AI model can be trained. At 1408, a prediction can be made as to whether to pre-fetch data, migrate data, or retain data in its memory device. Data can be pre-fetched into local or faster memory based on a predicted hot state of the data in a time window of interest. Data can be migrated into remote pooled memory or slower memory based on a predicted slow state of the data in a time window of interest. Data can be retained in a memory location if a prediction of a hot or cold state in the time window of interest aligns with the memory that stores that data.”].
Rafacz, Roberts and Dugast are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Rafacz and Roberts to divide the first region into a second region and a third region, wherein the second region is allotted the first number of accesses to the second storage medium, and the third region is allotted the first number of accesses to the second storage medium as taught by Dugast since doing so would provide the benefits of allowing for allocating optimal storage according to access frequency of the data thus providing faster accesses to frequently used data.
Therefore, it would have been obvious to combine Rafacz and Roberts with Dugast for the benefit of creating a storage system/method to obtain the invention as specified in claim 9.
10. The storage device of claim 7, wherein the processor is further configured to: identify a decrease in the activity of the first region; and change a status of the first region based on the decrease in the activity [Dugast teaches access rates are determined to classify pages as hot or cold where “At 1404, group pages within access rate buckets and associated pages within buckets with clusters. For example, kernel-space metadata on page accesses can be surfaced to a user space process and access rates for pages can be tracked. Pages with access rates that fit within a same window can be grouped into a same cluster. At 1406, an AI model can be trained based on access patterns to subclusters. For example, a cluster of data that does not include excluded categories (described earlier) can be divided into subclusters and hot and cold states of subclusters can be identified. Based on hot and cold states of subclusters, an AI model can be trained. At 1408, a prediction can be made as to whether to pre-fetch data, migrate data, or retain data in its memory device. Data can be pre-fetched into local or faster memory based on a predicted hot state of the data in a time window of interest. Data can be migrated into remote pooled memory or slower memory based on a predicted slow state of the data in a time window of interest.” (pars. 0076, 0078; figs. 13A and 14 and related text) thus, lower access rates or lower or decrease activity would classify pages as cold and cause the predictive system to migrate these pages to slower memory due to the decreased access rate or activity].
19. The method of claim 17 further comprising: dividing the first region into a second region and a third region, wherein the second region is allotted the first number of accesses to the second storage medium, and the third region is allotted the first number of accesses to the second storage medium [The rationale in the rejection of claim 9 is herein incorporated].
20. The method of claim 17 further comprising: identifying a decrease in the activity of the first region; and changing a status of the first region based on the decrease in the activity [The rationale in the rejection of claim 10 is herein incorporated].
ACKNOWLEDGEMENT OF ISSUES RAISED BY APPLICANT
Response to Amendment
Applicant's arguments filed 2/12/2026 have been fully considered but are not deemed persuasive.
As required by M.P.E.P. § 707.07(f), a response to these arguments appears below.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Claims must be given the broadest reasonable interpretation during examination and limitations appearing in the specification but not recited in the claim are not read into the claim (See M.P.E.P. 2111 [R-1]).
Applicant argues the prior art of record, including Roberts ‘530 does not disclose “modify the third memory address based on the first memory address” and “track activity within a boundary of the first region, wherein the boundary is determined based on a distance from the third memory address.”
In response, these arguments have been fully considered but are not deemed persuasive.
First, Applicant should note that the claimed third address recited in the rejected claim(s) has not been defined as described in paragraphs 0068-0069 and 0080 of the Specification. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Thus, the third address has been interpreted as an address corresponding to the range, such as one of the bound addresses. Note that nothing in the pending claims precludes this interpretation.
Roberts teaches “modify the third memory address based on the first memory address”as [“[0050] In FIG. 1-1, the cache memory 106-2 is a consumer 115 of the access metadata 112 and may utilize the access metadata 112 to prefetch addresses of the backing memory 108. The adaptive tracking engine 110 can receive feedback pertaining to prefetch performance within respective regions covered by the access metadata 112 and can adjust the address ranges covered by the access metadata 112 for improved precision, resulting in more accurate address predictions with limited resource overhead. The adaptive tracking engine 110 may, therefore, improve memory I/O performance by, inter alia, enabling the cache memory 106-2 to improve prefetch performance, resulting in a lower cache miss rate… [0057] The update logic 224 is configured to update, refine and/or determine access metadata 112 in response to, inter alia, operations pertaining to addresses 202 covered by the access metadata 112. The access metadata 112 can be updated in response to any suitable type of operation, directive, message, command, and/or indication thereof to retrieve, modify, manipulate and/or otherwise access data (generally referred to as a command 201 herein) including, but not limited to: data access requests, read requests, write requests, copy requests, clone requests, trim requests, erase requests, delete requests, cache misses, cache hits, and/or the like (which correspond to a first memory address of a memory access request).”] “[0137]…The adaptive tracking engine 110 captures access metadata 112 pertaining to address regions covered by respective entries 211 of the dataset 210, as disclosed herein. The entries 211 can be updated in response to cache requests (which also correspond to access requests having a first memory address), such as cache hits, cache misses, and/or the like.” Thus, since the updates to the address ranges based on data access requests, which have a first address, which may include any of the accesses identified in par. 0057 or 0137, a third or bound address of the range is updated based on the access address or first address. Additionally, note the third address has not been defined within the claim such as to preclude this interpretation].
“track activity within a boundary of the first region, wherein the boundary is determined based on a distance from the third memory address” [Roberts teaches “[0053] As illustrated in FIG. 2, the entries 211 of the access dataset 210 include access metadata 112 pertaining to specified address ranges. The access metadata entries 211 may, therefore, be configured as range entries 211, tracking entries 211, range tracking entries 211, access metadata tracking entries 211, and/or the like. An entry 211 may include any suitable information pertaining to the access metadata 112, including, but not limited to: range metadata 214 to specify the address range covered by the entry 211, access metadata 112 pertaining to the covered address range, and so on. The range metadata 214 may define covered address ranges using any suitable information including, but not limited to: address bounds, minimum and maximum address bounds (where the maximum address bound of the range may correspond to the third address associated with the accessed range as claimed), address tags, address tag bounds, minimum and maximum address tags, a base address and length, one or more tuples, and/or the like. The address range covered by an entry 211 may, therefore, be specified, defined, modified, and/or manipulated by, inter alia, writing one or more bits to the memory 208 (e.g., writing one or more bits to the range metadata 214 of the entry 211 maintained within the memory 208).” [0060] As disclosed in further detail herein, the management logic 226 of the adaptive tracking engine 110 may be configured to adjust the address ranges covered by the access metadata 112 and/or the size of such ranges in accordance with, inter alia, utility metrics 213 of the access metadata. In some examples, the address ranges covered by access metadata entries 211 having relatively high utility metrics 213 may be expanded, whereas the address ranges covered by entries 211 having relatively low utility metrics 213 may be contracted (or removed). Access metadata entries 211 that cover adjacent address ranges and have similar utility metrics 213 may be merged, thereby lowering overhead. In some aspects, address ranges and/or range sizes covered by respective access metadata entries 211 of the dataset 210 can be tuned in accordance with an adjustment policy. The adjustment policy may define thresholds and/or other criteria to trigger modifications to the set of address ranges covered by the access metadata 112, such as modifications to increase the size of one or more address ranges, decrease the size of one or more address ranges, merge one or more address ranges, split one or more address ranges, remove one or more address ranges, and/or the like. Alternatively, or in addition, the set of address ranges covered by the access metadata 112 may be adjusted in accordance with an optimization algorithm. The optimization algorithm may be configured to determine address ranges for respective entries 211 that produce optimal utility metrics 213 at minimal cost, which may be quantified in terms of resource requirements, management overhead, and/or the like.” “[0104]… the size of the address range covered by the modified access metadata entry 211-3 may be promoted from the smallest range size to the next larger range size of level 320-2. As illustrated in FIG. 5-5, the entry 211-3 is modified to cover a second-level address range {“0x662000”, “0x662FFF”} of node 311-6 rather than the smaller, first-level address range {“0x662100”, “0x6621FF”}.” (as address ranges may be shrunk, a third address within that range indicating a range bound may be modified to no longer belong within a given range or as ranges may be expanded, the ending or bound address corresponding to the range bound may be modified) thus, teaching a bound as a distance from the third address to for example, the beginning of the range].
Regarding all other Claims not specifically traversed above and whose rejections were upheld, the Applicant contends that the listed claims are allowable by virtue of their dependence on other allowable claims. As this dependence is the sole rationale put forth for the allowability of said dependent claims, the Applicant is directed to the Examiner's remarks above. Additionally, any other arguments the Applicant made that were not specifically addressed in this Office Action appeared to directly rely on an argument presented elsewhere in the Applicant’s response that was traversed, rendered moot or found persuasive above.
All arguments by the applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated 2/12/2026.
CLOSING COMMENTS
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). Any new grounds of rejection have been necessitated by Applicant’s amendment.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-5, 7-15 and 17-20 have received an action on the merits and are subject to a final rejection.
a(2) CLAIMS NO LONGER UNDER CONSIDERATION
Claims 6 and 16 have been canceled.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIMA RIGOL whose telephone number is (571)272-1232. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached on (571) 272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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April 1, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135