DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6 April 2026 and 5 August 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Response to Request for Reconsideration
The Response filed 12 June 2026 has been entered. Claims 1-5, 7-15, and 17-20 remain pending in the application. Examiner acknowledges arguments concerning rejections under 35 USC § 103 which have been found unpersuasive.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 7-14, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Anastasiev et al (U.S. Patent Pub. No. 2020/0371942), hereinafter referred to as Anastasiev, in view of Kwon et al (U.S. Patent Pub. No. 2014/0379995), hereinafter referred to as Kwon, and Radhakrishnan et al (U.S. Patent Pub. No. 2016/0054997), hereinafter referred to as Radhakrishnan.
In regard to claim 1, Anastasiev teaches a storage device comprising: a first storage medium (Fig. 2 Disks 3); a processor (Fig. 2 Read-ahead module 4) configured to: identify a first distance between first memory addresses accessed by a computing device that satisfies a first criterion; add the first distance as a first entry of a pattern (Paragraph 0046, a first interval i.e. distance is placed in read-ahead list if longer than threshold).
Anastasiev does not teach the remaining limitations of claim 1. However, Kwon teaches an embodiment including: based on adding the first distance as the first entry of the pattern: monitor for a second memory access that has the first distance between accessed second memory addresses (¶ 0019, plurality of stride detectors monitor continuously for patterns and generate prefetch addresses based on a pattern; ¶ 0048, request is monitored to determine if it matches the pre-selected pattern); and retrieve data from the first storage medium based on a first entry and a second entry of the pattern (¶ 0071-0072, prefetch requests generated by pattern detectors are used to satisfy read requests i.e. data is retrieved based on the plurality of detected strides stored in sub-detectors). A person of ordinary skill in the art could easily implement the pattern detectors of Kwon in a memory controller utilizing request queues, known in prior art (see Fig. 5). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Kwon in order to identify and prioritize a plurality of different stride patterns as well as control prefetch operations simply on the basis of a read request address (Paragraph 0085, lines 1-3) and reduce the possibility of prefetch address mismatches (¶ 0085, lines 3-6).
The previously cited references do not explicitly teach an embodiment including the limitations: based on detecting the second memory access that has the first distance, monitor a plurality of third memory accesses by the computing device; detect that the plurality of the third memory accesses have a second distance between accessed third memory addresses; and based on detecting that the plurality of the third memory accesses have the second distance, add the second distance as a second entry of the pattern. However, Radhakrishnan teaches a pattern detector (¶ 0050) that can monitor for repeated strides and update a pattern to include a different stride (¶ 0071, prefetch pattern info is updated with single stride pattern data that can be updated again or turned into a multi-stride pattern e.g. when a second distance is detected; Fig. 11 pattern updating is performed continuously), achieving the claimed limitation when implemented in combination with Anastasiev and Kwon. Radhakrishnan additionally teaches adding a distance entry to a prefetching pattern based on a detected number of repeated strides (¶ 0153, training states must reach a detected number threshold before being used for prefetching, including multi-stride patterns; ¶ 0172-0190 elaborate on the cited multi-stride pattern detection in the embodiment) reaching a threshold greater than one (¶ 0161, lines 1-2 example is of a single stride pattern, but the threshold is 2 and one of ordinary skill could easily implement this in a multi-stride pattern as disclosed). Radhakrishnan ¶ 0161-0164 disclose the process of adding a distance to a pattern after it is used for two sequential accesses (in the example, memory address A plus offset 5, followed immediately by A plus offset 10, the same distance sequentially accessed), achieving the claimed limitations. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Radhakrishnan in order to detect and update multi-stride access patterns continuously and detect access patterns accurately and quickly without predetermined patterns (¶ 0021, lines 1-3).
As for claim 2, the previously cited references teach the storage device of claim 1. Additionally, Anastasiev teaches a second storage medium including volatile memory (Fig. 2, RAM-cache 2), wherein the processor is configured to retrieve data from the first storage medium and store the data in the second storage medium (Paragraph 0036, lines 5-8), achieving the claimed limitation.
In regard to claim 3, the previously cited references teach the storage device of claim 1. Additionally, Kwon teaches an embodiment wherein a stride pattern is selected for later use in a sub detector (monitoring accesses including successive addresses e.g. identifying distances, see Paragraph 0023, lines 1-3 and Paragraph 0033, lines 1-4; Paragraph 0034) when it has been detected a threshold number of times (Paragraphs 0034-0035). When combined with the continuous pattern recording and updating of Radhakrishnan cited in the rejection of claim 1, the claimed limitation is achieved.
As for claim 4, the previously cited references teach the storage device of claim 3. Additionally, Kwon teaches an embodiment wherein multiple pattern sub detectors 110 (Fig. 1) may have different detection thresholds, which when combined with previous disclosures would achieve the claimed limitations by allowing for a second detection threshold for a second distance.
As for claim 7, the previously cited references teach the storage device of claim 1. Additionally, Anastasiev teaches identifying a first region based on first memory addresses and determining the subsequent memory addresses are associated with that region (Paragraph 0048, an overlap of new request with previous interval is determined, e.g. subsequent memory addresses are determined to be associated with a first region). Anastasiev also teaches based on determining that the subsequent memory addresses are associated with the first region, identify the second distance between the subsequent memory addresses. In Fig. 3, the process of determining an overlap must happen before interval set lists (distance lists) are updated (step 309) wherein lists of all intervals are updated (Paragraph 0056), which would include recording (i.e. identifying) the latest interval (including start address and length i.e. distance, Paragraphs 0040-0042), achieving the claimed limitation.
As for claim 8, the previously cited references teach the storage device of claim 7. Additionally, Anastasiev teaches determining an overlap which would functionally require computing a difference between one of the first memory addresses in an interval and a third memory address (determine overlap, Paragraph 0048), and determining if the first memory address is a threshold distance from the third (intervals only include starting address and length (Paragraphs 0040-0042), and a complete overlap must be determined (Paragraph 0049), which functionally requires determining if the address is a threshold distance from the last memory address in the memory address range).
The previously cited references do not teach the remaining limitations of claim 8. However, Kwon teaches identifying a third memory address from a first range of addresses (Paragraph 0023, operates in phase 2 mode when an input address is provided between two input addresses e.g. identified from first range). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Kwon in order to detect overlapping and control prefetch operations simply on the basis of a read request address, without a program counter (Paragraph 0085, lines 1-3).
As for claim 9, the previously cited references teach the storage device of claim 7. Additionally, Anastasiev teaches identifying a second region based on the first memory addresses, wherein the second region is associated with a second range of addresses (after determining an overlap, bounds of an existing first interval are expanded e.g. a second region is identified based on first memory addresses, Paragraph 0053), wherein the second region is of a preset size, wherein the second region includes the first region. (Paragraph 0055, bounds are expanded to the size of the current request (i.e. preset size), and an expansion of bounds without explicit relocation must functionally include the previous region), achieving the claimed limitation.
As for claim 10, the previously cited references teach the storage device of claim 7. Additionally, Anastasiev teaches identifying a second region based on at least one of the first memory addresses (If there is no intersection with previous intervals (distances including first memory addresses), a new random interval is recorded i.e. second region Paragraph 0050), and identify the first region based on the processor being configured to identify the second region. (Fig. 3 steps 302-309 Interval set lists are updated and transferred for processing e.g. existing first regions are identified only after a new random interval is recorded), achieving the claimed limitation.
As for claim 11, Applicant is directed to the rejection of claim 1 above, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 12, the previously cited references teach the method of claim 11. For remaining limitations, Applicant is directed to the rejection of claim 2 above, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 13, the previously cited references teach the method of claim 11. For remaining limitations, Applicant is directed to the rejection of claim 3 above, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 14, the previously cited references teach the method of claim 13. For remaining limitations, Applicant is directed to the rejection of claim 4 above, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 17, the previously cited references teach the method of claim 11. For remaining limitations, Applicant is directed to the rejection of claim 7 above, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 18, the previously cited references teach the method of claim 17. For remaining limitations, Applicant is directed to the rejection of claim 8 above, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 19, the previously cited references teach the method of claim 17. For remaining limitations, Applicant is directed to the rejection of claim 9 above, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 20, the previously cited references teach the method of claim 17. For remaining limitations, Applicant is directed to the rejection of claim 10 above, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
Claims 5-6 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Anastasiev, Kwon, Radhakrishnan, and Chou (U.S. Patent Pub. No. 2017/0010970).
In regard to claim 5, the previously cited references teach the storage device of claim 1. They do not explicitly teach the remaining limitations of claim 5. However, Chou teaches a stream prefetcher which can identify a two-stride access pattern (Paragraph 0030, e.g. an access pattern of multiple different distances). A prefetcher as known in the art will then functionally identify third and fourth distances (Fig. 6, step 608 a two-stride pattern results in prefetch instructions for a data sequence having two or more different strides (e.g. differing first and second distances which will result in differing third and fourth distances)), a prefetch results in data from specified addresses being returned i.e. some signal is generated based on identifying third and fourth distances and addresses; Paragraph 0080). Additionally, Radhakrishnan ¶ 0071 discloses that prefetch pattern info is updated with single stride pattern data that can be updated again or turned into a multi-stride pattern e.g. when a second, third, fourth, etc. distance is detected (e.g. a four-stride pattern would be detected and updated i.e. generate a signal), and in Fig. 11 pattern updating is performed continuously. If Chou is combined with these disclosures wherein criterion are used for pattern matching and recording distances as pattern entries, the claimed limitation is achieved. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Chou in order to prefetch data based on different stride patterns (Chou Paragraph 0030, lines 3-7).
As for claim 6, the previously cited references teach the storage device of claim 1. They do not teach the remaining limitations of claim 5. However, Chou teaches a stream prefetcher which can identify a two-stride access pattern (Paragraph 0030, e.g. an access pattern of multiple different distances). This prefetcher will functionally identify third and fourth distances as being equal to first and second distances, respectively (Fig. 6, step 608 a two-stride pattern results in prefetch instructions for a data sequence identified as having two or more different strides), a prefetch results in data from specified addresses being returned i.e. some signal is generated based on identifying fourth and fifth addresses; Paragraph 0080). Additionally, Radhakrishnan ¶ 0071 discloses that prefetch pattern info is updated with single stride pattern data that can be updated again or turned into a multi-stride pattern e.g. when a second, third, fourth, etc. distance is detected. Chou’s disclosure combined with those previously cited would continuously create and update pattern entries and detect a two-stride access pattern as claimed. If combined with previous disclosures wherein criterion are used for pattern matching and recording distances as pattern entries, the claimed limitation is achieved. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Chou in order to prefetch data based on different stride patterns (Chou Paragraph 0030, lines 3-7).
As for claim 15, the previously cited references teach the method of claim 11. For remaining limitations, Applicant is directed to the rejection of claim 5 above, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
As for claim 16, the previously cited references teach the method of claim 11. For remaining limitations, Applicant is directed to the rejection of claim 6 above, as the claims are directed to the same limitations and are therefore rejected on the same rationale.
Response to Arguments
Applicant’s arguments (see pages 7-8 of response filed 12 June 2026) with respect to the rejections of amended claims 1 and 11 under 35 U.S.C 103 were considered but found unpersuasive. Arguments directed to Radhakrishnan’s suitability in teaching a multi-stride pattern detection requiring a threshold occurrence greater than 1 were unpersuasive. Radhakrishnan ¶ 0153 briefly explains the process for adding a multi-stride pattern using thresholds, and ¶ 0161 explains the pattern threshold for an example single-stride recognition. Multi-stride detection is explicitly addressed in this same embodiment later in the reference, beginning in ¶ 0172. As seen in the disclosed process for detecting a multi-stride pattern in the same manner as a single-stride pattern beginning in Radhakrishnan ¶ 0172, in ¶ 0181 the pattern threshold used is a value greater than 1 to prevent erroneous detection of a single stride pattern. Then, in ¶ 0188-0190 multi-stride detectors are used to detect a multi-stride pattern wherein the stride count is explicitly greater than 1 (2 in the example). The rejection of claim 1 has been modified for clarity to indicate the additional information related to the embodiment. Applicant’s reference to Fig. 7 is not relevant to the claimed limitation of adding a stride to a pattern entry, as the disclosure of Radhakrishnan first recognizes patterns for training using atoms (such as in Fig. 7), then adds them to prefetch pattern information based on thresholds (see ¶ 0161 or ¶ 0181). This second step is mapped to the claimed pattern entries in the rejection.
Applicant’s arguments (see page 8 of response) that the inclusion of Radhakrishnan would make the invention unfit for its intended purpose are unpersuasive. Applicant has not provided reasoning to support this statement, and the invention of Radhakrishnan would be carrying out its intended purpose of stride pattern detection in the cited combination.
Applicant is reminded that a reference may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art, and disclosed examples and preferred embodiments do not constitute a teaching away from a broader disclosure or nonpreferred embodiments (see MPEP § 2123).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZAKARIA MOHAMMED BELKHAYAT/ Examiner, Art Unit 2139
/REGINALD G BRAGDON/ Supervisory Patent Examiner, Art Unit 2139
Prosecution Insights