DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities:
Page 1, line 6, “The entity” should be changed to “The entirety”.
Page 4, line 20, “for some reason” is very vague language and should be changed to “due to a fault” or “due to a ground fault condition”.
Page 4, lines 9-10, “may arbitrarily adjust an output voltage” is odd due to the fact the term “arbitrarily” means something based on a whim or random. The term “arbitrarily” should be deleted as it is clear the control is not done randomly.
In multiple locations the language of “a dividing resistor” is used, however, this is incorrect phrasing as is known in the art and should be changed to “a resistor divider”.
The specification provided has paragraph numbers, however, some paragraphs do not have numbers but seem to indicate a new paragraph has started. For example, Page 4, Paragraph 0013, starts with “The ground” then a new paragraph starting with “The comparison circuit 21” begins, however, no numbering is provided. This is present throughout the Specification provided and should be corrected accordingly.
Appropriate correction is required.
Claim Objections
Claims 1-7 are objected to because of the following informalities:
Claim 1, lines 3-4, “an adjustment voltage input to a voltage adjustment port” should be changed to “an adjustment voltage is input into a voltage adjustment port”.
Claim 1, lines 9-10, “upon monitor the adjustment voltage detecting the voltage adjustment port having a ground fault” should be changed to “upon monitoring the adjustment voltage and detecting that the voltage adjustment port has a ground fault”.
Claim 1, line 3, “a dividing resistor” is awkward language and should be changed to a “resistor divider”.
Claims 2 and 4 each recite the language “dividing resistor” which should be changed to “resistor divider”.
Claim 2, line 5, recites “a first MOS transistor having a source connected to an output port” should be changed to “a first MOS transistor having a source connected to the output port”.
Claim 3, line 2, “is composed of” which should be changed to “comprises”
Claim 3, line 1, “comprising:” should be removed as it is not necessary here.
Claim 4, line 10, recites “a first MOS transistor having a source connected to an output port” should be changed to “a first MOS transistor having a source connected to the output port”.
Claim 5, line 3, “a backflow prevention element at the drain” should be changed to “a backflow prevention element connected to the drain”.
Claim 6, line 3, “a pull-up element on the gate” should be changed to “a pull-up element connected to the gate”.
Claim 7, line 3, “a pull-up element on the gate” should be changed to “a pull-up element connected to the gate”.
Appropriate correction is required.
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US 2018/0120875 A1) in view of Sutardja (US 2009/0167275 A1).
Regarding claim 1, Suzuki teaches a voltage regulator (Figure 1), comprising: an output transistor (Figure 1 Component 12) which outputs an output voltage (Figure 1 Component Vout) to an output port (Figure 1 Component 14); a dividing resistor which divides the output voltage (Figure 1 Component VD1; Paragraph 0042 “dividing the output voltage VOUT by the voltage divider circuit VD1”) and outputs a feedback voltage (Figure 1 Component VD1 output voltage at node N1); a first reference voltage circuit (Figure 1 Component 1) which outputs a first reference voltage (Figure 1 Component Vref); an error amplifier circuit (Figure 1 Component 11; Paragraph 0028 “voltage regulator 100 includes an error amplifier 11”) which controls a gate voltage of the output transistor (Paragraph 0034 “An output of the error amplifier 11 is connected to a gate of the output transistor 12”) based on the first reference voltage and the feedback voltage (Paragraph 0034 “error amplifier 11 has an inverting input terminal connected to a reference voltage circuit 1, which is configured to generate a reference voltage VREF, and a non-inverting input terminal connected to the node N1”); and a ground fault protection circuit (Figure 1 Components VD2+13+16+R5 form a ground fault protection; Paragraph 0042-0044 highlight an operation wherein these components operate when a large current flows through the load and a surge in current as such can be seen as a ground fault condition) which, upon monitoring the output voltage having a ground fault (Paragraphs 0042-0044), changes the feedback voltage in comparison to the first reference voltage (Paragraph 0043 highlights that when a large current is detected to have occurred then Component 16 is turned on which decreases the reference voltage).
Suzuki does not teach wherein the feedback dividing resistor receives an adjustment voltage input to a voltage adjustment port; a circuit component, upon monitoring the adjustment voltage detecting the voltage adjustment port having a fault condition, increasing the feedback voltage to the first reference voltage.
Sutardja teaches a power conversion circuit (Figure 2), comprising: an output transistor (Figure 2 Component 34; Paragraph 0014 “The voltage regulator 34 may be any type of voltage regulator such as switching regulators and linear regulators”; A linear regulator is known to have a pass transistor) which outputs an output voltage (Figure 2 Component Vc) to an output port (Figure 2 Component 38); a feedback network (Figure 2 Component 50) that receives an adjustment voltage (Figure 2 Component Vout) input to a voltage adjustment port (Figure 2 component 44); and a circuit component, upon monitoring the adjustment voltage detecting the voltage adjustment port having a fault condition, increasing the feedback voltage towards a reference voltage (Paragraph 0016 highlights that when a degradation is detected, which is a fault condition, the pull up resistor and voltage, seen in Figure 2 Component 46 and the voltage, increase the feedback voltage; Paragraph 0019-0020 highlight that the pull up can be increased to a capped value which can be seen as a reference voltage).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Suzuki to incorporate the teachings of Sutardja by providing a feedback node that receives an externally influenced voltage, such as from an adjustment voltage port, and by configuring the feedback modification circuitry to increase the feedback voltage rather than only decreasing it. The advantage of this medication is that it provides additional flexibility in controlling the regulator, including enabling alternative protection responses under abnormal conditions, as well as allowing the regulator to respond to externally defined voltage conditions leading to both a more efficient system overall and also a more applicable one over a range of differing conditions.
Allowable Subject Matter
Claims 2-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the ground fault protection circuit comprises: a comparison circuit which compares the adjustment voltage and a second reference voltage; and a first MOS transistor having a source connected to an output port, a drain connected to an output port of the dividing resistor, and a gate connected to an output port of the comparison circuit. Claim 3 depends upon claim 2 therefore is also objected to.
Regarding claim 4, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the ground fault protection circuit comprises: a second reference voltage circuit comprising a current source and a resistor connected in series between an input port and a ground port; a comparison circuit which comprises: a second MOS transistor provided between the current source and the resistor and having a gate connected to a drain; a third MOS transistor having a gate connected to the gate of the second MOS transistor; and a fourth MOS transistor having a gate and a drain connected to a drain of the third MOS transistor, and which compares the adjustment voltage and the second reference voltage, and a first MOS transistor having a source connected to an output port, a drain connected to an output port of the dividing resistor, and a gate connected to the gate of the fourth MOS transistor of the comparison circuit. Claims 5-7 depend upon claim 4 therefore are also objected to.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang (US 2023/0122458 A1) teaches a low dropout linear voltage regulator and a control circuit thereof. The control circuit includes an error amplifier and a backflow prevention circuit, which compares an input voltage with an output voltage, to switch a substrate voltage and a voltage at a control terminal of the power transistor to a higher one of the input voltage and the output voltage, thus the power transistor and its parasitic diode can be turned off in time when the output voltage is greater than the input voltage, so as to prevent the power transistor from being damaged by current backflow and improve reliability of the low dropout linear regulator.
Fujiwara (US 2016/0054749 A1) teaches a regulator circuit (1) that has a regulator portion generate a constant internal power supply voltage based on an external power supply voltage. A current detecting portion includes a current detecting transistor (11) and voltage compensation portion includes an output transistor (10) which is current mirror-connected with transistor and compensation amount setting resistor connected to output side for setting compensation amount.
Nakashimo (US 2012/0194947 A1) teaches a voltage regulator capable of providing overcurrent protection without increasing current consumption even when an output current increases. An overcurrent protection circuit includes: a sense resistor provided to a drain of an output transistor, for sensing an output current; an offset comparator for comparing voltages at both terminals of the sense resistor; and a first transistor including a gate connected to an output of the offset comparator. A current path between a detection transistor and the sense resistor is eliminated, and hence a current for detection does not increase even when an output current is large.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahzeb K. Ahmad whose telephone number is (571)272-0978. The examiner can normally be reached Monday - Friday 8 A.M. to 5 P.M..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Shahzeb K Ahmad/Examiner, Art Unit 2838
Prosecution Insights