Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner cites particular columns or paragraphs, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Objections
Claim 1 is objected to because of the following informalities: the claim recites “and are electrically connected to the pixels” in lines 10-11, which appear to be “and [[are]] electrically connected to the pixels”. Appropriate correction is required.
Claims 2-12 are objected based on their dependence from claim 1.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18533185 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other as shown below:
Instant Application 18772286
Co-Pending Application 18533185
A transparent display apparatus, comprising:
a transparent substrate, having a plurality of display areas and a plurality of transparent
areas;
a pixel array, disposed on the transparent substrate, wherein the pixel array
comprises:
a plurality of pixels, arranged in an array
in a first direction and a second direction,
wherein the first direction and the second direction intersect, and each of the pixels
overlaps with a corresponding one of the display areas; and
a plurality of openings, wherein each of the openings is surrounded by a
part of the pixels, and the each of
the openings overlaps with a
corresponding one of the transparent areas;
a plurality of signal lines, disposed on the transparent substrate and are electrically
connected to the pixels; and
a light blocking element, comprising a plurality of light blocking pillars spaced apart
from each other, wherein the transparent substrate has a first side and a second side opposite to each other, the pixels
are disposed on the first side of the transparent substrate, and
the light blocking pillars are
disposed on the second side of the transparent substrate.
A transparent display apparatus, comprising:
a transparent substrate, having a plurality of display areas and a plurality of transparent
areas;
a first pixel array, disposed on the transparent substrate, wherein the first pixel array
comprises
a plurality of first pixels, arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect, and each of the plurality of first pixels overlaps a corresponding display area; and
a plurality of first openings, wherein each of the plurality of first openings is surrounded by a portion of the plurality of first pixels, and each of the plurality of first openings overlaps with a corresponding transparent area;
a plurality of signal lines, disposed on the transparent substrate and are electrically
connected to the plurality of first pixels; and
a light leakage suppression element, comprising a plurality of light blocking structures spaced apart from each other, wherein the transparent substrate has a first side and a second side opposite to each other, the plurality of first pixels are disposed on the first side of the transparent substrate, and
at least a portion of each of the plurality of light blocking structures of the light leakage suppressing element is
disposed on the second side of the transparent
substrate.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Allowable Subject Matter
Claim 1 would be allowable upon overcoming the above claim objection and upon overcoming the above Double Patenting Rejection.
Claims 2-12 are objected to as being dependent upon a rejected base claim but would be allowable upon overcoming the above claim objections and upon overcoming the above Double patenting Rejection, based on their dependence from claim 1.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, Ye et al. (CN 117456849 A) (provided by the applicant on the record, machine translation provided by the examiner) discloses a transparent display apparatus (see Fig. 1), comprising:
a transparent substrate, having a plurality of display areas and a plurality of transparent areas (see transparent substrate 10 in Figs. 1-2);
a pixel array, disposed on the transparent substrate (regarding Figs. 1-2 and 4, “three light emitting diodes 30 are provided in a cup cover 50 to form a complete display unit package module”; “These display unit packaging modules can be regarded as a complete pixel unit”; see the array of pixels in Figs. 1-2), wherein the pixel array comprises:
a plurality of pixels, and each of the pixels overlaps with a corresponding one of the display areas (see the pixels in Figs. 1-2, each overlapping corresponding display areas); and
a plurality of openings, wherein each of the openings is surrounded by a part of the pixels, and the each of the openings overlaps with a corresponding one of the transparent areas (see openings between the pixels in Figs. 1-2, each overlapping corresponding transparent areas);
a plurality of signal lines, disposed on the transparent substrate and are electrically connected to the pixels (see in Figs. 1-2 “first circuit 20 is disposed on one side of the transparent substrate 10, and has a conductive line and a conductive pad for supplying power to the light emitting diode 30”; “the conductive line mainly includes lines such as VCC, GND, Din, Dout and so on, for transmitting electrical signals between the light emitting diode 30, the driving circuit, the digital control circuit and so on”); and
a light blocking element (see in Figs. 1-2 anti-reflection structure 40), wherein the transparent substrate has a first side and a second side opposite to each other (see opposite sides of the transparent substrate 10 in Figs. 1-2), the pixels are disposed on the first side of the transparent substrate (see pixels disposed on first side of the transparent substrate 10 in Figs. 1-2), and the light blocking element disposed on the second side of the transparent substrate (see in Figs. 1-2 “the anti-reflection structure 40 is disposed on the other side of the transparent substrate 10”).
Cho et al. (US 2020/0185453 A1) a plurality of pixels, arranged in an array in a first direction and a second direction, wherein the first direction and the second direction intersect (see in Fig. 2 “first to third micro-LEDs 51, 52, and 53… be formed as a single pixel”; para[0075]).
However, prior art, taken alone or in combination, fails to teach or suggest the following limitations in combination with the rest of the claim, that is, the claim as a whole: “…a light blocking element, comprising a plurality of light blocking pillars spaced apart from each other, wherein the transparent substrate has a first side and a second side opposite to each other, the pixels are disposed on the first side of the transparent substrate, and the light blocking element pillars are disposed on the second side of the transparent substrate”, as claimed in claim 1.
Regarding claims 2-12, these claims would be allowable based on their dependence from claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GLORYVID FIGUEROA-GIBSON whose telephone number is (571)272-5506. The examiner can normally be reached on 9am-5pm, Monday -Friday, Eastern Time.
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/GLORYVID FIGUEROA-GIBSON/Patent Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628