DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuchiya et al. (USPAPN 2007/0216381).
With respect to claim 1, Tsuchiya et al. discloses, in Fig. 6, a low dropout regulator (Fig. 6), comprising:
an amplifier (11), comprising a non-inverting input terminal (gate of Tr3), an inverting input terminal (gate of Tr2), an internal cascade node (node connected to the drains of Tr2 and T4, wherein Tr2 and T4 are connected in cascode) and an output terminal (node at the drains of Tr7 and Tr9);
a buffer circuit (12), comprising an input terminal (gate of Tr10) and an output terminal (drain of Tr10), wherein the input terminal of the buffer circuit is coupled to the output terminal of the amplifier (11 and 12 are connected as claimed);
an output circuit (Tr1 with r1 and R2), comprising an input terminal (gate of Tr1) and an output terminal (drain of Tr1), wherein the input terminal of the output circuit is coupled to the output terminal of the buffer circuit (Tr1 and 12 are connected as claimed), and the output terminal of the output circuit is configured to output an output voltage (Vo);
a first compensation capacitor, coupled between the output terminal of the output circuit and the internal cascade node of the amplifier (C4), and configured to separate a first pole frequency in a Bode plot of the low dropout regulator from a power supply rejection ratio corner frequency of the low dropout regulator (a bode plot of the low dropout regulator is merely a graphical representation of the low dropout regulator and not part of the low dropout regulator. Thus, the bode plot is merely a function limitation of the connections and operations of the circuitry. Additionally, C4 is connected as claimed and provides for such a separation of the first pole); and
a second compensation capacitor (C3), coupled between the input terminal of the buffer circuit (gate of Tr10) and an input power source (Vi), and configured to separate a second pole frequency and a third pole frequency in the Bode plot of the low dropout regulator (again, the bode plot of the low dropout regulator is merely a graphical representation of the low dropout regulator and not part of the low dropout regulator. Thus, the bode plot is merely a function limitation of the connections and operations of the circuitry. Additionally, C3 is connected as claimed and provides for such a separation of the second and third pole frequencies. It is further noted that C3 and C4 are connected in essentially the same fashion as claimed and in the same fashion as Applicant’s claimed compensation capacitors. Thus, the compensation capacitors of Tsuchiya et al. operate as claimed),
wherein a conduction state between the second compensation capacitor and the input power source is independent of a buffer voltage output by the buffer circuit (C3 is directly connected to Vi and is not controlled responsive to the buffer output voltage of 12. Thus, the circuit is connected and operative as claimed).
With respect to claim 2, the low dropout regulator of claim 1, wherein the inverting input terminal of the amplifier is configured to receive a reference voltage (e1), the non-inverting input terminal of the amplifier is configured to receive a feedback voltage (Via R1 and R2), and the amplifier is configured to output a control voltage at the output terminal of the amplifier based on the reference voltage and the feedback voltage, so as to adjust the output voltage of the output circuit (the amplifier operates as claimed to generate the control voltage at the drains of Tr7 and Tr9).
With respect to claim 3, the low dropout regulator of claim 2, wherein the input terminal of the buffer circuit is configured to receive the control voltage (gate of Tr10 receives the voltages at the drains of Tr7 and Tr9), and the buffer circuit is configured to output the buffer voltage at the output terminal of the buffer circuit based on the control voltage (output voltage of Tr10 to the gate of Tr1).
With respect to claim 4, the low dropout regulator of claim 3, wherein the output circuit comprises a power transistor (Tr1), a control terminal of the power transistor is coupled to the output terminal of the buffer circuit (gate of Tr1 connected as claimed), a first terminal of the power transistor is coupled to the input power source (source of Tr1 connected to Vi), and a second terminal of the power transistor is coupled to the output terminal of the output circuit (drain of Tr1 connected to Vo).
With respect to claim 5, the low dropout regulator of claim 4, wherein the control terminal of the power transistor is configured to receive the buffer voltage (gate of Tr1 receivers the output voltage of 12).
With respect to claim 6, the low dropout regulator of claim 4, wherein the output circuit further comprises a voltage divider circuit (R1 with R2) , the voltage divider circuit is coupled to the second terminal of the power transistor (R1 connected to the drain of Tr1), the non-inverting input terminal of the amplifier (node between R1 and R2 connected to gate of Tr3) and a ground (R2 connected to GND), and configured to output the feedback voltage to the non-inverting input terminal of the amplifier based on the output voltage (voltage output from R1 and R2 to the gate of Tr3).
With respect to claim 7, the low dropout regulator of claim 6, wherein the voltage divider circuit comprises a first divider resistor (R1) and a second divider resistor (R2), the first divider resistor is coupled between the second terminal of the power transistor and a first node (R1 connected as claimed), the second divider resistor is coupled between the first node and the ground (R2 connected as claimed), and the non-inverting input terminal of the amplifier is coupled to the first node (gate of Tr3 connected as claimed).
With respect to claim 8, the low dropout regulator of claim 1, wherein the first pole frequency in the Bode plot is related to the capacitance of the first compensation capacitor, and the second pole frequency in the Bode plot is related to the capacitance of the second compensation capacitor (the poles are set according to the capacitances as claimed).
With respect to claim 9, the low dropout regulator of claim 1, wherein in the Bode plot, the first pole frequency is lower than the second pole frequency (C4 is set for high frequencies see para 0048 and C3 is set for low frequencies, i.e., lower than high frequencies, see para 0065).
Claims 19-20 merely recite the method of constructing/operating the circuit of as recited in claims 1 and 9. Claims 19-20 are rejected for essentially the same reasons as claims 1 and 9.
Claim(s) 10-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hua et al. (USPAPN 2016/0266591).
With respect to claim 10, a low dropout regulator (Fig. 3, operational details disclosed in Figs. 4-6), comprising:
an amplifier (302 with 304 and current mirror connected to 304), comprising a non-inverting input terminal (gate of transistor of 302 that is connected to VFB), an inverting input terminal (gate of transistor of 302 that is connected to VREF), an internal cascade node (N1) and an output terminal (VHIZ terminal);
a buffer circuit (204), comprising an input terminal (input connected to VHIZ) and an output terminal (output connected to 216), wherein the input terminal of the buffer circuit is coupled to the output terminal of the amplifier (at the VHIZ terminal);
an output circuit (M1 with R1 and R2), comprising an input terminal (gate of M1) and an output terminal (drain of M1), wherein the input terminal of the output circuit is coupled to the output terminal of the buffer circuit (at 216), and the output terminal of the output circuit is configured to output an output voltage (VOUT);
a first compensation capacitor (CC1), coupled between the output terminal of the output circuit (drain of M1) and the internal cascade node of the amplifier (N1), and configured to separate a first pole frequency in a Bode plot of the low dropout regulator from a power supply rejection ratio corner frequency of the low dropout regulator (a bode plot of the low dropout regulator is merely a graphical representation of the low dropout regulator and not part of the low dropout regulator. Thus, the bode plot is merely a function limitation of the connections and operations of the circuitry. Additionally, CC1 is connected as claimed and provides for such a separation of the first pole, see 0 to P1 of the bode plots of Figs. 4 and 5); and
a second compensation capacitor (CC2), coupled between the input terminal (VHIZ terminal) and the output terminal of the buffer circuit (via the gate to drain connection of M2), and configured to separate a second pole frequency and a third pole frequency in the Bode plot of the low dropout regulator (again, the bode plot of the low dropout regulator is merely a graphical representation of the low dropout regulator and not part of the low dropout regulator. Thus, the bode plot is merely a function limitation of the connections and operations of the circuitry. Additionally, CC2 is connected as claimed and provides for such a separation of the second and third pole frequencies, see P2 to P3 of the bode plots of Figs. 4 and 5).
With respect to claim 11, the low dropout regulator of claim 10, wherein the inverting input terminal of the amplifier is configured to receive a reference voltage (VREF), the non-inverting input terminal of the amplifier is configured to receive a feedback voltage (VFB), and the amplifier is configured to output a control voltage at the output terminal of the amplifier based on the reference voltage and the feedback voltage, so as to adjust the output voltage of the output circuit (VHIZ is generated at the VHIZ terminal as recited).
With respect to claim 12, the low dropout regulator of claim 11, wherein the input terminal of the buffer circuit is configured to receive the control voltage (input of 204 receiving VHIZ), and the buffer circuit is configured to output a buffer voltage at the output terminal of the buffer circuit based on the control voltage (VGATE).
With respect to claim 13, the low dropout regulator of claim 12, wherein the output circuit comprises a power transistor (MOSFET M1), a control terminal of the power transistor is coupled to the output terminal of the buffer circuit (gate terminal), a first terminal of the power transistor is coupled to the input power source (source terminal), and a second terminal of the power transistor is coupled to the output terminal of the output circuit (drain terminal).
With respect to claim 14, the low dropout regulator of claim 13, wherein the control terminal of the power transistor is configured to receive the buffer voltage (gate of M1 receives VGATE).
With respect to claim 15, the low dropout regulator of claim 13, wherein the output circuit further comprises a voltage divider circuit (R1 and R2), the voltage divider circuit is coupled to the second terminal of the power transistor (drain), the non-inverting input terminal of the amplifier (VFB via 202) and a ground (ground at R2), and configured to output the feedback voltage to the non-inverting input terminal of the amplifier based on the output voltage (VFB is generated as claimed).
With respect to claim 16, the low dropout regulator of claim 15, wherein the voltage divider circuit comprises a first divider resistor (R1) and a second divider resistor (R2), the first divider resistor is coupled between the second terminal of the power transistor (Drain) and a first node (VFB node), the second divider resistor is coupled between the first node (VFB node) and the ground (ground), and the non-inverting input terminal of the amplifier is coupled to the first node (gate is connected to the VFB node).
With respect to claim 17, the low dropout regulator of claim 10, wherein the first pole frequency in the Bode plot is negatively related to the capacitance of the first compensation capacitor, and the second pole frequency in the Bode plot is positively related to the capacitance of the first compensation capacitor (first pole frequency the bode plot is negatively related to the capacitance of CC1 and the second pole is positively related to the capacitance of CC1 due to the pole splitting provided by CC1, see paragraphs 0030 and 0039) and the and negatively related to the capacitance of the second compensation capacitor (the second pole is negatively related to capacitance of CC2 due to the zero setting of CC2, to suppress the gain peaking of P2, see paragraphs 0039 and 0040).
With respect to claim 18, the low dropout regulator of claim 10, wherein in the Bode plot, the first pole frequency is lower than the second pole frequency (f1 of P1 of Figs. 4 and 5 is lower than f2 of P2 of Figs. 4 and 5).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-9 and 19-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The argument that Hua et al. fails to disclose “(a) a second compensation capacitor, coupled between the input terminal and the output terminal of the buffer circuit (hereinafter referred to as "second distinguishing feature")” is not persuasive. As can be seen. The output of buffer 204 is connected to the input (i.e., gate) of transistor M2 of 204. Furthermore, the output of 204 (i.e., drain terminal) is connected to a first terminal of Cc2 and the second terminal of Cc2 is connected to the input of 204. Thus, Cc2 is connected between the input terminal (i.e., termina at the input of 204) of the buffer and the output terminal (i.e., VGATE) via the input (gate) to output (drain) path of M2. It is known in the art that the gate of a transistor may be interpreted as the input of the transistor and the output of a transistor may be interpreted as the output of the transistor. As is known the drain current (i.e., output of a transistor) is proportional to the gate voltage (i.e., input voltage), this is further evidenced in paragraph 0041 which states “[a]s the drive signal VGATE increases to increase current across M1, the VGS of M1 and M2 will increase”. It can be seen that both the drain currents of M1 and M2 are proportional to the gate voltage VGATE, as evidenced by Hua et al. Thus, one may interpret the gate of M2 as an input of M2 and the drain terminal of M2 as the output of M2. Therefore, Cc2 is connected between the input and output of 204 via the input (i.e., gate) of M2 and the output (i.e., drain) of M2. Therefore, Applicant’s arguments are not persuasive.
The argument that “[h]owever, according to common sense, the gate to drain conduction path of a transistor is typically non-conductive; otherwise, this transistor would fail” is not persuasive, since it is an incorrect assumption as evidenced by paragraph 0041 of Hua et al. As discussed above, the drain current is of M2 is proportional to the gate voltage of M2/output of 204. Again, paragraph 0041 of Hua et al. states “[a]s the drive signal VGATE increases to increase current across M1, the VGS of M1 and M2 will increase”. Furthermore, it is common to consider the gate terminal of a transistor as the input and the drain terminal of a transistor as the output terminal. Moreover, assuming, arguendo, that “the gate to drain conduction path of a transistor is typically non-conductive”. Hua et al. evidences that at least during some time of operation the gate to drain path of M2 is conductive, since, as evidenced in paragraph 0041, “as the drive signal VGATE increases to increase current across M1, the VGS of M1 and M2 will increase”. Therefore, the Cc2 will be connected and operative as claimed during the above time in operation and thus meets the claimed limitations.
The argument that “the capacitor Cc2 should not be considered as being coupled to the output terminal of the amplifier 204, because the gate to drain connection of the transistor M2 is typically non-conductive” is not persuasive for the reasons discussed above. The gate to drain connection (i.e., input to output) of M2 is conductive while the circuit operates. Furthermore, the above connections are required to be conductive to provide the required resistance tuning of M2 when the circuit is operative.
Cited art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Feldman (USPN 9,231,525) discloses in Fig. 5 a “second compensation capacitor” (Ccomp) serially connected to an adjustable resistor (Rcomp). Ccomp and Rcomp are operative to provide essentially the same functionality as M2 and Cc2 of Hua et al. (USPAPN 2016/0266591). However, it can be seen that the order of Ccomp and Rcomp of Feldman is rearranged such that a conduction state between the second compensation capacitor (Ccomp) and the input power source (vdd) is independent of a buffer voltage output by the buffer circuit, since Ccomp is directly connected to vdd the conduction stage between Ccomp and vdd is independent of the output of a buffer. As can be seen Feldman evidences that it is obvious to move the position of the compensation capacitor and the compensation resistor in a circuit connected in essentially the same way as M2 and Cc2 of Hua et al. If one was to rearrange the adjustable resistor and compensation capacitor of Hua et al. in the a similar fashion as Ccomp and Rcomp of Feldman the rearranged circuit of Hua et al. would be connected as recited in claim 1. Furthermore, it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Bakkaloglu et al. (USPN 8,604,762) discloses, in Fig. 6, regulator comprising a first compensation capacitor (Cc) and second compensation capacitor (Cz). The second compensation capacitor being connected between the input of a buffer (gate of M11) and the output of a buffer (drain of M11).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2849