Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species III in the reply filed on 11/25/2025 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kusuda et al. (US 7764118 B2 and Kusuda hereinafter.) in view of Denison et al. (US 20100327887 A1 and Denison hereinafter.).
Regarding claim 1, Kusuda discloses a signal generation circuit [fig. 2], comprising: a first chopper [14]; an operational transconductance amplifier [GM1] comprising a differential input circuit [inverting and noninterfering inputs of GM1] and an amplifier circuit [unlabeled circuitry associated with amplification within GM1], wherein the differential input circuit is coupled to the first chopper to receive a differential input signal [Vin on through 14 and onto GM1]; a second chopper [32] coupled to the operational transconductance amplifier [as shown], wherein the differential input signal is processed into an output signal at an output node of the amplifier circuit [output of GM1] and the second chopper [output of Gm1 into 32]; and a ripple reduction loop circuit [12, col 4 lines 24-31] coupled between the output node and a compensation node (VC1,VC2)[56 and 58] and comprising: a third chopper [40] configured to convert a ripple in the output signal into a direct current offset signal [col 4 lines 24-31]; and an operational amplifier [GM4] coupled to the third chopper [as shown] and configured to convert the direct current offset signal into a compensation signal [col 4 lines 24-31], wherein the compensation signal is configured to input to the compensation node [56 and 58 onto 24 and 26]. Kusuda does not explicitly disclose the operational transconductance amplifier comprises a current mirror circuit. Wherein the differential input signal is processed into an output signal at an output node by the current mirror circuit. The ripple reduction loop circuit coupled between the output node and the compensation node of the current mirror circuit.
However, Denison discloses [fig. 2 and 6] the operational transconductance amplifier [14] comprises a current mirror circuit [M6 and M7]. Wherein the differential input signal [input A and B] is processed into an output signal [31] at an output node by the current mirror circuit [M6 and M7 effecting M10 and therefore 31]. The ripple reduction loop [Feedback path 16] circuit coupled between the output node and the compensation node [output of 17 on 16] of the current mirror circuit [as shown]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Kusuda to include the operational transconductance amplifier comprises a current mirror circuit. Wherein the differential input signal is processed into an output signal at an output node by the current mirror circuit. The ripple reduction loop circuit coupled between the output node and the compensation node of the current mirror circuit as taught by Denison to improve power and noise performance in a circuit.
Regarding claim 6, Kusuda discloses a circuit, comprising: a signal generation circuit [fig. 2] comprising: a first chopper [14]; an operational transconductance amplifier [Gm1] coupled to the first chopper [as shown] to receive a differential input signal [inverting and noninterfering inputs of GM1]; a second chopper [32] coupled to the operational transconductance amplifier [as shown], wherein the differential input signal is processed into an output signal at an output node by the operational transconductance amplifier [output of Gm1] and the second chopper [output of Gm1 into 32]; and a ripple reduction loop circuit [12, col 4 lines 24-31] coupled to the output node to receive the output signal [as shown], and comprising a third chopper [40] and an operational amplifier [Gm4], wherein the third chopper is configured to convert a ripple in the output signal into a direct current offset signal [col 4 lines 24-31], and the operational amplifier is configured to convert the direct current offset signal into a compensation signal [56 and 58 onto 24 and 26] to compensate for an offset voltage in the operational transconductance amplifier [col 4 lines 24-31]. Kusuda does not explicitly disclose the circuit as a frequency locked loop and a voltage controlled oscillator coupled to the signal generation circuit, and configured to generate a reference clock signal according to the output signal.
However, Denison discloses [fig. 2, 6 and 15b] the circuit as a frequency locked loop [para. 180] and a voltage controlled oscillator [562 and 564] coupled to the signal generation circuit [14 of fig. 2 and 6 corresponding to 560 of fig. 15b], and configured to generate a reference clock signal according to the output signal [para. 193-194]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Kusuda to include the circuit as a frequency locked loop and a voltage controlled oscillator coupled to the signal generation circuit, and configured to generate a reference clock signal according to the output signal as taught by Denison to improve power and noise performance in a circuit.
Regarding claim 7, Kusuda in view of Denison discloses further wherein the operational transconductance amplifier comprises a current mirror circuit [Denison, M6 and M7] and an amplifier circuit [Denison, para. 54], the differential input signal [Denison, input A and input B] is processed into the output signal at the output node by the current mirror circuit [as shown], the amplifier circuit and the second chopper [as shown], and the compensation signal is configured to input to a compensation node of the current mirror circuit [Denison, m6 and m7 processing input from M1 and M2.
Claims 2-3, 5 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kusuda in view of Denison further in view of Wu et al. (IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, VOL. 63, NO. 4, APRIL 2016 and Wu hereinafter.).
Regarding claim 2, Kusuda in view of Denison discloses all the features regarding claim 1 as indicated above. Kusuda in view of Denison does not explicitly disclose wherein the ripple reduction loop circuit further comprises: a fourth chopper coupled to between the third chopper and the operational amplifier; and a fifth chopper coupled to the operational amplifier to receive the compensation signal.
However, Wu discloses [fig. 1] wherein the ripple reduction loop circuit [RRL] further comprises: a fourth chopper [unlabeled chopper accepting fhigh signal to right of Gm3] coupled to between the third chopper [chopper accepting fchop signal] and the operational amplifier [Gm3]; and a fifth chopper [unlabeled chopper accepting fhigh signal to left of Gm3] coupled to the operational amplifier to receive the compensation signal [output of Gm3]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Kusuda in view of Denison to include the ripple reduction loop circuit further comprises: a fourth chopper coupled to between the third chopper and the operational amplifier; and a fifth chopper coupled to the operational amplifier to receive the compensation signal as taught by Wu to improve low power and low noise performance in a ripple reduction circuit.
Regarding claim 3, Kusuda in view of Denison further in view of Wu discloses further wherein the compensation node comprises a first compensation node [Wu, a first input of Gm1] and a second compensation node [Wu, a second input of Gm1] to receive a first compensation signal [Wu, a first output o Gm3] and a second compensation signal [Wu, a second output of Gm3] of the compensation signal, and the ripple reduction loop circuit further comprises: a filter circuit [Wu, C3] coupled to two output terminals of the fifth chopper [as shown], and configured to generate the first compensation signal and the second compensation signal [as shown], wherein a voltage difference is between the first compensation signal and the second compensation signal [Wu, fig. 2, RRL output signals into M2 and M3].
Regarding claim 5, Kusuda in view of Denison discloses all the features regarding claim 1 as indicated above. Kusuda in view of Denison does not explicitly disclose wherein the third chopper receives the output signal by a filter capacitor.
However, Wu discloses [fig. 1] wherein the third chopper [chopper accepting fchop signal] receives the output signal by a filter capacitor [Cs capacitors]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Kusuda in view of Denison to include the third chopper receives the output signal by a filter capacitor as taught by Wu to improve low power and low noise performance in a ripple reduction circuit.
Regarding claim 8, Kusuda in view of Denison discloses all the features regarding claim 1 as indicated above. Kusuda in view of Denison does not explicitly disclose wherein the ripple reduction loop circuit further comprises: a fourth chopper coupled to between the third chopper and the operational amplifier; and a fifth chopper coupled to the operational amplifier to receive the compensation signal.
However, Wu discloses [fig. 1] wherein the ripple reduction loop circuit [RRL] further comprises: a fourth chopper [unlabeled chopper accepting fhigh signal to right of Gm3] coupled to between the third chopper [chopper accepting fchop signal] and the operational amplifier [Gm3]; and a fifth chopper [unlabeled chopper accepting fhigh signal to left of Gm3] coupled to the operational amplifier to receive the compensation signal [output of Gm3]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Kusuda in view of Denison to include the ripple reduction loop circuit further comprises: a fourth chopper coupled to between the third chopper and the operational amplifier; and a fifth chopper coupled to the operational amplifier to receive the compensation signal as taught by Wu to improve low power and low noise performance in a ripple reduction circuit.
Regarding claim 9, Kusuda in view of Denison further in view of Wu discloses further wherein the compensation node comprises a first compensation node [Wu, a first input of Gm1] and a second compensation node [Wu, a second input of Gm1] to receive a first compensation signal [Wu, a first output o Gm3] and a second compensation signal [Wu, a second output of Gm3] of the compensation signal, and the ripple reduction loop circuit further comprises: a filter circuit [Wu, C3] coupled to two output terminals of the fifth chopper [as shown], and configured to generate the first compensation signal and the second compensation signal [as shown], wherein a voltage difference is between the first compensation signal and the second compensation signal [Wu, fig. 2, RRL output signals into M2 and M3].
Allowable Subject Matter
Claims 4 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
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/JAMES G YEAMAN/Examiner, Art Unit 2842
/LINCOLN D DONOVAN/Supervisory Patent Examiner, Art Unit 2842