DETAILED ACTION
This non-final office action is in response to claims 1-19 filed July 15, 2024 for examining. Claims 1-19 are being examined and are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 10/13/2024 and 05/19/2025 has been placed in the application file and the information referred to therein has been considered as to the merits.
Drawings
The drawings filed on 07/15/2024 have been accepted.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-19 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-19 of prior U.S. Patent No. 12,105,857 B2 (application S/N # 17/599,603). Although the conflicting claims are not identical, they are not patentably distinct from each other because the referenced US Patent and the instant application are claiming common subject matter, as follows (some of the claims are shown as example):
Claim Comparison Table:
Instant Application
(# 18/353,155)
US Patent # 12,105,857 B2
(# 17/599,603)
1. A method for detection of counterfeit and cyber electronic components, comprising:
obtaining one or more features from a plurality of electronic components of a first type and from a plurality of electronic components of a second type: processing the one or more features to create a unique model related to an electronic component of the first type and to an electronic component of the second type;
examining a detected electronic component by obtaining one or more features of the detected electronic component;
executing the unique model with the one or more features of the detected electronic component;
determining if the detected electronic component is an authentic electronic component of the first type or the second type; and
evaluating the state of the detected electronic component's soldering pads, thereby enabling to detect reworking of a soldering pad of the detected electronic component as an indication of counterfeiting and to evaluate the quality of the pad for solderability.
1. A method for detection of counterfeit and cyber electronic components, comprising:
obtaining one or more features from a plurality of electronic components of a first type and from a plurality of electronic components of a second type:
processing the one or more features to create a unique model related to an electronic component of the first type and to an electronic component of the second type;
examining a detected electronic component by obtaining one or more features of the detected electronic component;
executing the unique model with the one or more features of the detected electronic component;
determining if the detected electronic component is an authentic electronic component of the first type or the second type; and compiling quality related features of the one or more features of the detected electronic component to a quality index determining whether the electronic component is acceptable for use in production, wherein the quality index compiles the output of the unique model for authentic components and classifies components with different types of faults.
13. The method according to claim 1, further comprising evaluating the state of the detected electronic component's soldering pads, thereby enabling to detect reworking of a soldering pad of the detected electronic component as an indication of counterfeiting and to evaluate the quality of the pad for solderability.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20180101945 A1 (Stone et al.): A method includes obtaining data associated with an electronic component. The method also includes conducting a multi-tier inspection process to verify a conformance of the electronic component. Each of the tiers includes a different type of identification test, and at least one of the tiers is configured to provide fuzzy outputs. The method further includes analyzing the data associated with the electronic component using one or more first tests associated with a first of the tiers to determine whether the electronic component conforms to a pre-specified requirement. In addition, the method includes generating an output based on the analysis and determining whether additional testing is required using one or more next-level tests associated with another of the tiers. Abstract.
CN 105940354: in step S92, the device state value when the processing object soldering pad (unqualified product) present in a condition representing the device state value of the abnormal value, the abnormality detection section 66 judges that abnormality occurs in a manufacturing facility so as to execute necessary processing (step S93). information (e.g., device name) indicating an abnormality of the device status values, strategy (e.g., change, repair and restoration method of operating conditions) etc. may be taken, for example, for informing the occurrence of abnormality to the user and configured to analyzing device, an operation terminal, the corresponding production device outputs determining the presence abnormal suspected of producing device At this time, the priority output information related to the unqualified product (determining object substrate and the information object soldering pad, the unqualified determination of joint state of characteristic quantity and its value indicates the abnormal product, etc.), state value and defective distribution of the device status values and product state value. the output method information may be a monitor display, printer, using the speaker to output sound, and any method such as sending mail. Alternatively, the abnormality detection section 66 in order to correct the abnormal, also can determine how to change the production device operating conditions, to change the operating condition of the corresponding production device (mounting program). In this case, the abnormality detection section 66 can also be automatically changed production operating condition of the device, also can be the analyzing device, an operation terminal, displaying ' change operating condition monitor of the production device is? such as to inquire of the user whether changing after receiving changes from the user permission to execute the action condition of the change processing.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWNCHOY RAHMAN whose telephone number is (571)270-7471. The examiner can normally be reached Monday - Friday 8:30A-5P ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taghi T Arani can be reached at 5712723787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Shawnchoy Rahman/Primary Examiner, Art Unit 2438