DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al (US 7,298,173).
The reference to jiang et al shows an integrated data signal transmitter, with a standby voltage generator configured to output: (i) a data signal(data bit=H=1) during an active operation mode(i.e. transmit mode OE=H), and (ii) first and second standby voltages(+/-bias voltages), having different (+/-)magnitudes(+Vbias and -Vbias) from each other, during a standby operation mode(one particular mode when there is no transmission of data); and a data repeater block including: a first CMOS inverter(46-1) configured to receive the first standby voltage during the standby operation mode, said first CMOS inverter including a first PMOS transistor and a first NMOS transistor (see figure 7); and a second CMOS inverter(46-2) configured to receive the second standby voltage during the standby operation mode, said second CMOS inverter including a second PMOS transistor and a second NMOS transistor (see figure 7).
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930
1246
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As noted in col. 4, ll. 34-43:
“(17) Turning now to FIG. 4, a partial schematic diagram is shown of the output port circuit 40. The three lines of delay time input 44 are shown individually as 44-1, 44-2, and 44-3. The delay time input 44 is connected to a digital-to-analog converter (current DAC) 63. A current output of the DAC 63 is applied to a bias voltage generator 64. The DAC 63 receives the delay signal and converts it to a current as is described later. The bias voltage generator 64 converts the current to a positive bias voltage 66 and a negative bias voltage 68. The positive and negative bias voltages 66, 68 are applied to each of the cascaded delay cells 46. The cascaded delay cells 46 use the positive and negative bias voltages 66, 68 …”
Shown below is the representation of the delay cells(46-1…N) that repeat/delay the data signal.
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926
1336
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The reference does not show the delay cells where the PMOS in each cell being different , that is, having the 2nd PMOS in the 2nd delay cell line with a lVlthp2<lVlthp1, likewise, for the NMOS transistors of each cell, for example.
The examiner notes that the dimensional parameters of the PMOS and NMOS elements can be designed to affect the point at which these elements are biased ON/OFF and is functionally equivalent to using the current/bias means where as noted in top of col.6, “sizes of PFETs Q15-Q18 can be unequal to provide up to eight discrete levels of current flow through the programmable current output 78…”. That is, PMOS/NMOS delay elements can be designed having different sizing based on the need to affect the delay thru each one as desired.
The reference also does not explicitly describe selectively output of data during active mode, but as was noted above, and shown by table 5(noting the 3state and 0 state) : there are distinct inputs when OE and Datain are both ‘0’ and standby mode, that is, active low signal mode. 3state (Hi-Z mode allows for isolation of the outputs)
In light of the above it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have recognized that the apparatus as shown by Jiang et al shows shows the data transmission and use of delay cells to provide repeated outputs to a driver where the adjustment of the PMOS and NMOS sizing may be enhanced to affect the delay thru each stage as noted above. The various modes as described above based on the signal levels for OE and data signal levels include ‘active’ when both signals are 1 and ‘standby’ when both are 0/low.
Allowable Subject Matter
Claims 11-19 are allowed.
Claims 2-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2836
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