DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communication: an amendment
filed on 02/05/2026.
Claims 1-20 are currently pending and presented for examination.
Response to Arguments
Applicant’s remarks and amendments filed on 02/05/2026 with respect to prior art rejection of claim 1 have been considered but are moot because the arguments do not apply to the combination of the references being used in the current rejection. Applicant’s remarks and amendments filed on 02/05/2026 with respect to prior art rejection of claims 10 and 17 have been considered and are persuasive. Claims 10-20 are allowed. Interpretation under 35 U.S.C 112(f) is withdrawn since the claims have been amended to overcome the interpretation under 35 U.S.C 112(f),
Claim Rejections - 35 USC § 102
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,2,7,8 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Kaneda (US Pub. No.: US 2011/0134493 A1).
Regarding claim 1, Kaneda discloses an image processing circuit (Para 32-33; Fig. 1; image forming apparatus 100) comprising:
a scan conversion circuit (Para 34- 38; image reading unit 105 , DMA controller 305 and raster conversion unit 306) configured to receive tiled images ( Para 38; The tile image data stored in the image memory 304 is read out and transferred by a DMA controller 305. Processing for reading out tile image data from the image memory 304 is controlled by the DMA controller 305 in response to an instruction from the CPU 309) and non-tiled images (Para 34; image reading unit 105 that includes an original platen and an automatic document feeder (ADF). The image reading unit 105 irradiates a bundle of originals or a single original with a light source (not shown), and provides a reflected image from the original on a solid-state image sensing element by means of a lens. Thus, the image reading unit 105 acquires an image read signal in a raster shape from the solid-state image sensing element as a raster image of a predetermined density (for example, 600 dpi). ) from a plurality of channels (Para 34-38; wherein the image reading unit 105 obtains images from solid-state image sensing element; DMA controller obtains tied image data from image memory 304 wherein solid-state image sensing element and image memory can be considered as channels) connected to a plurality of imaging devices (Para 32-38; Figs. 1-3; wherein the solid-state image sensing element and memory are connected to display unit 102 and printing unit 107; wherein those are both imaging devices to output image data) and to generate output data; and
an image signal processor ( Para 39; The CPU 309 performs control of each of the above-described blocks according to a mode designated by the operation unit 104 or the data processing unit 101) configured to receive and process the output data from the scan conversion circuit, wherein the scan conversion circuit is configured to determine a scan method for generating the output data according to a first operation mode or a second operation mode (Para 38-41; The CPU 309 gives an instruction to the DMA controller 305 by writing appropriate values into the respective registers of the register unit 501; If the address data is tile image data, the bus interface 503 writes the data into a FIFO (First-In First-Out) 504, and if the data is table data ("table"), the bus interface 503 sends the data to the address generation unit 502. Tile image data that is read from the image memory 304 is temporarily stored in the FIFO 504. Even if a time period temporarily occurs during which input of data to the raster conversion unit 306 is not possible, the DMA controller 305 stores the tile image data in the FIFO 504. The data can either be written into a FIFO or to the address generation unit 502; Para 9, 44; output control unit configured to read out a block of image data stored in the storage unit in a main scanning direction; Para 37; the image data generation unit 303 analyzes the print data and creates intermediate language information based on the analysis result, and also generates and converts tile image data or bitmap image data, and converts display colors R, G, and B (additive process) included in the print data into colors Y, M, C, and K (subtractive process) that can be processed by the printing unit 107).
Regarding claim 2, Kaneda discloses The image processing circuit of claim 1, wherein the scan conversion controller circuit is configured to scan the output data using a raster scan method in the first operation mode (Para 9, 44; output control unit configured to read out a block of image data stored in the storage unit in a main scanning direction ) and is configured to scan the output data using a tile scan method in the second operation mode (Para 37, 44; the image data generation unit 303 analyzes the print data and creates intermediate language information based on the analysis result, and also generates and converts tile image data or bitmap image data; the bitmap image data is output to the printing unit 107 by switching the line of image data to be output to the printing unit 107 in accordance with the skew of the main scan line ) .
Regarding claim 7, Kaneda discloses the image processing circuit of claim 2, wherein the scan conversion controller circuit is configured to select the first operation mode ( Para 34; The image forming apparatus 100 includes an image reading unit 105 that includes an original platen and an automatic document feeder (ADF). The image reading unit 105 irradiates a bundle of originals or a single original with a light source (not shown), and provides a reflected image from the original on a solid-state image sensing element by means of a lens. Thus, the image reading unit 105 acquires an image read signal in a raster shape from the solid-state image sensing element as a raster image of a predetermined density (for example, 600 dpi)) or the second operation mode to scan images received from each of the plurality of channels (Para 41-44; The CPU 309 gives an instruction to the DMA controller 305 by writing appropriate values into the respective registers of the register unit 501. An address generation unit 502 generates address data for reading out tile image data stored in the image memory 304. The address data ("addr") is generated by referring to the contents of each register of the register unit 501 and a table for reading out tile image data that is created by the CPU 309) .
Regarding claim 8, Kaneda discloses The image processing circuit of claim 2, wherein the scan conversion controller circuit is configured to first output an image that is received first from among the tiled images and untiled images received from the plurality of channels (Para 41; If the address data is tile image data, the bus interface 503 writes the data into a FIFO (First-In First-Out) 504, and if the data is table data ("table"), the bus interface 503 sends the data to the address generation unit 502. Tile image data that is read from the image memory 304 is temporarily stored in the FIFO 504. Even if a time period temporarily occurs during which input of data to the raster conversion unit 306 is not possible, the DMA controller 305 stores the tile image data in the FIFO 504. As a result, the tile image data can be immediately supplied from the FIFO 504 to the raster conversion unit 306 when the raster conversion unit 306 is again able to receive data. A raster conversion unit interface 505 sends the tile image data stored in the FIFO 504 to the raster conversion unit 306.).
Allowable Subject Matter
Claims 3,4,5,6,9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, Kaneda discloses a memory (Para 51; image memory 304 or the RAM 311) .
However, the prior art does not disclose The image processing circuit of claim 2, wherein the scan conversion controller circuit comprises:
a memory configured to store packing data items obtained by packing images received from each of the plurality of channels according to an index allocated to each of the plurality of channels; and a plurality of channel index memories configured to store index information of the memory in which the packing data items are stored according to the plurality of channels.
Claims 4,5,6,9 are objected to as being dependent from claim 3.
Regarding claim 10, prior art on record Amano (US Pub No.: US 2009/0080794 A1) discloses a scan conversion controller (Fig. 5, 8 ; Para 88; Para 111; image data recording system 1 (drive recorder or security camera) using the image processing device according to this embodiment) comprising:
a first data packing circuit configured to receive first line data from a first channel and to pack the first line data into a predetermined data size to generate first packing data ( Para 90-114; Digital signals from the NTSC/PAL video decoders 12-1 to 12-4 can be converted into a JPEG image by combining the second image processing device (interlace/progressive conversion device or IC) 20 with a first image processing device (multi-camera image controller) 30 and the like. Second image processing device includes input controllers 110-1 to 110-4 that control the input timings of image data through the channels 102-1 to 102-4. The second image processing device (multi-video-input interlace/progressive device or IC that converts an interlaced signal into a progressive signal) 20 according to this embodiment includes scalers 110-1 to 110-4 that resize image data output from the input controllers 110-1 to 110-4 ) ;
a second data packing circuit configured to receive second line data from a second channel and to pack the second line data into a predetermined data size to generate second packing data (Para 90-114; Digital signals from the NTSC/PAL video decoders 12-1 to 12-4 can be converted into a JPEG image by combining the second image processing device (interlace/progressive conversion device or IC) 20 with a first image processing device (multi-camera image controller) 30 and the like. Second image processing device includes input controllers 110-1 to 110-4 that control the input timings of image data through the channels 102-1 to 102-4. The second image processing device (multi-video-input interlace/progressive device or IC that converts an interlaced signal into a progressive signal) 20 according to this embodiment includes scalers 110-1 to 110-4 that resize image data output from the input controllers 110-1 to 110-4 ) ;
an arbitration circuit (Para 115; The second image processing device (multi-video-input interlace/progressive device or IC that converts an interlaced signal into a progressive signal) 20 includes a memory controller 140 that writes outputs from the scalers 110-1 to 110-4 into the SRAM 130, reads image data from the SRAM 130 at a predetermined timing, and outputs the image data to a first output line 163, a second output line 165, and a third output line 166.) configured to receive the first packing data and the second packing data and to sequentially output the first packing data and the second packing data;
a memory (Para 115; SRAM 130; The second image processing device (multi-video-input interlace/progressive device or IC that converts an interlaced signal into a progressive signal) 20 includes a memory controller 140 that writes outputs from the scalers 110-1 to 110-4 into the SRAM 130) configured to store the first packing data and the second packing data;
a write circuit configured to control a write operation of the memory ( Para 115; memory controller 140 that writes outputs from the scalers 110-1 to 110-4 into the SRAM 130 ) ;
a read circuit configured to control a read operation of the memory ( Para 115; memory controller 140 reads image data from the SRAM 130 at a predetermined timing, and outputs the image data to a first output line 163, a second output line 165, and a third output line 166.); and
an unpacking circuit configured to generate output data by unpacking read data output from the read circuit (Para 115; memory controller 140; Fig. 8; outputs the image data to a first output line 163, a second output line 165, and a third output line 166.).
However, the prior art does not disclose “a line index circuit configured to manage a first index for a first region in which the first packing data is stored in the memory, and a second index for a second region in which the second packing data is stored in the memory, and to determine a scan method of the first packing data and the second packing data allocated to the first index and the second index, respectively, from among a tile scan method and a non-tile scan method” in combination of other limitation in the claim.
Claims 11-16 are allowed as being dependent from claim 10.
Regarding claim 17, prior art on record Amano discloses a method of operating an image processing circuit including a scan conversion controller including an internal memory ( Fig. 5, 8 ; Para 88; Para 111; image data recording system 1 (drive recorder or security camera; Para 115; includes a memory controller 140 that writes outputs from the scalers 110-1 to 110-4 into the SRAM 130, reads image data from the SRAM 130 at a predetermined timing, and outputs the image data to a first output line 163, a second output line 165, and a third output line 166) using the image processing device according to this embodiment) the method comprising:
packing line data received through each of a plurality of channels into a predetermined data size to generate packing data ( Para 90-114; Digital signals from the NTSC/PAL video decoders 12-1 to 12-4 can be converted into a JPEG image by combining the second image processing device (interlace/progressive conversion device or IC) 20 with a first image processing device (multi-camera image controller) 30 and the like. Second image processing device includes input controllers 110-1 to 110-4 that control the input timings of image data through the channels 102-1 to 102-4. The second image processing device (multi-video-input interlace/progressive device or IC that converts an interlaced signal into a progressive signal) 20 according to this embodiment includes scalers 110-1 to 110-4 that resize image data output from the input controllers 110-1 to 110-4);
unpacking read data read from the internal memory and generating output data (Para 115; memory controller 140; Fig. 8; outputs the image data to a first output line 163, a second output line 165, and a third output line 166).
Hendry et al. (US Pub. No.: US 2023/0108222 A1) discloses determining a scan method of the parking data corresponding to input that is competed based on indices allocated to the image region to which input of line data is completed (Claim 1; Para 86-91; both the HRD at the encoder and the decoder may select a raster scan mechanism or a rectangular mechanism based on the tile group flag 531. The HRD and the decoder can then employ the selected mechanism to determine the assignment of the tiles 523 to the tile group 521 based on the first tile 532 and the last tile 533) ,
outputting index information corresponding to the determined scan method (Claim 1; Para 86-91; both the HRD at the encoder and the decoder may select a raster scan mechanism or a rectangular mechanism based on the tile group flag 531. The HRD and the decoder can then employ the selected mechanism to determine the assignment of the tiles 523 to the tile group 521 based on the first tile 532 and the last tile 533; Para 93-94; As the tiles are indexed in raster scan order, the raster scan mechanism can then add the determined number of tiles to the tile group in raster scan order (e.g., the for loop in the else statement). ); reading the packing data from the internal memory based on the index information; and unpacking read data read from the internal memory and generating output data ( Para 86-91; the decoder can receive the bitstream 500 and determine tile group 521 assignment based on the tile group flag 531, the first tile 532, and the last tile 533. Specifically, both the HRD at the encoder and the decoder may select a raster scan mechanism or a rectangular mechanism based on the tile group flag 531. The HRD and the decoder can then employ the selected mechanism to determine the assignment of the tiles 523 to the tile group 521 based on the first tile 532 and the last tile 533.) .
Prior art on record Park (US Pub. No.: US 2021/0191625 A1) discloses allocating indices corresponding to each of the plurality of channels and writing the packing data to the internal memory based on addresses included in the allocated indices (Fig. 7; Para 43, 19, 127; FIG. 1, the first memory die 240A and the controller 130 may be coupled through a first channel and first way CH1W1, and the second memory die 240B and the controller 130 may be coupled through a first channel and second way CH1W2. Furthermore, the third memory die 240C and the controller 130 may be coupled through a second channel and first way CH2W1, and the fourth memory die 240D and the controller 130 may be coupled through a second channel and second way CH2W2. The valid clusters may be allocated to store data in response to read requests. The plurality of clusters may include attribute information corresponding to the respective clusters. The attribute information on the clusters may include index information (Index #) for identifying the plurality of clusters, data information (DATA #) stored in the output buffer 186 for read requests in response to the respective pieces of index information, control information (Control Information) on control units which have processed data and stored the data in the output buffer 186, task information (Task ID) indicating the request types of the data, and flag information (Flag) for determining whether data is currently stored in a valid cluster and ready to be outputted to the host or the external device); managing indices allocated to each of the plurality of channels ( Para 43,44;45, 62; The plurality of memory dies 240A to 240D within the memory device 150 may be considered as different modules, and coupled to the controller 130 through different data paths. When the plurality of memory dies 240A to 240D and the controller 130 do not exchange data through one data path, the plurality of memory dies 240A to 240D and the controller 130 may exchange data through an interleaving operation therebetween, thereby increasing a data transfer rate. he controller 130 may distribute and store data according to the operation environments and operation states of the plurality of memory dies 240A to 240D within the memory device 150, and try to pair read requests for the plurality of data ) .
However, the prior art does not disclose “wherein the scan method is determined as a tile scan method based on tile indices allocated to the one of the plurality of channels, and wherein the scan method is determined as a non-tile scan method based on non-tile indices allocated to the one of the plurality of channels” in combination of other limitation in the claim.
Claims 18-20 are allowed as being dependent from claim 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Holland et al. (US Pub. No.: 2020/0250097 A1) discloses an intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.
Poddar (US Patent No.: 9,449,362 B2) discloses Various embodiments are generally directed to techniques for reducing storage access bandwidth requirements in retrieving a texture image from a storage for applying textures to rendered objects by rendering the texture image itself into the storage to reduce the storage space in which the texture image is stored and to arrange portions of the texture image to be retrieved with fewer accesses. A device to render images includes a processor component; a color analyzer to determine a clear color of a texture image stored as source texture data; and a rendering routine to render the texture image into a storage as reduced texture data, the rendering routine to selectively store in the reduced texture data pixel color values retrieved from the source texture data that are associated with pixels of the texture image not colored with the clear color. Other embodiments are described and claimed.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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