DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5-9, 12, 14-18, 20, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Godey et al (US PGPUB 2022/0207813).
Regarding claim 1, Figure 1 of Godey discloses a system comprising:
a first processor [104]
a second processor that maintains state information within volatile storage embedded in the second processor [102]
supplies a retention voltage to the volatile storage when the first processor causes the second processor to operate in a low-power state [paragraph 16]
Godey does not explicitly disclose a power multiplexer that supplies a retention voltage to the volatile storage when the first processor causes the second processor to operate in a powered-off state.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Godey by using a power multiplexer to supply retention voltage in a powered-off state as a matter of simple design-choice, since it was well-known in the art to use multiplexers to supply voltages and it would have been a matter of simple substitution of one known element for another to use a powered-off state as the low-power state.
Regarding claim 2, Figure 1 of Godey, as applied to claim 1, discloses wherein the second processor is a graphics processing unit [102], and the first processor causes the graphics processing unit to operate in the powered-off state in-between rendering consecutive graphic frames [paragraphs 16-24].
Regarding claim 5, Figure 1 of Godey, as applied to claim 1, discloses a voltage regulator that supplies a normal voltage to the second processor when the second processor operates in a powered-on state and supplies the retention voltage through the power multiplexer and to the volatile storage when the second processor operates in the powered-off state [inherent; see rejection of claim 1].
Regarding claim 6, Figure 1 of Godey, as applied to claim 5, does not explicitly disclose wherein the voltage regulator is a system voltage regulator that supplies the normal voltage to the second processor through a digital low-dropout regulator when the second processor operates in the powered-on state.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Godey, as applied to claim 5, by using a system voltage regulator and a digital low-dropout regulator as a matter of simple design-choice, since it was well-known in the art to use low-dropout regulators to supply voltage.
Regarding claim 7, Figure 1 of Godey, as applied to claim 6, discloses wherein the digital low-dropout regulator suppresses the normal voltage supplied to the second processor when the second processor operates in the powered-off state [see rejection of claim 6; paragraphs 16-24].
Regarding claim 8, Figure 1 of Godey, as applied to claim 7, discloses wherein the power multiplexer supplies the retention voltage to the volatile storage when the digital low-dropout regulator suppresses the normal voltage supplied to the second processor [see rejection of claim 7; paragraphs 16-24].
Regarding claim 9, Figure 1 of Godey discloses a processing device comprising:
a retention voltage interface that receives a retention voltage when the processing device operates in a low-power state [130]
a normal voltage interface that receives a normal voltage supplied from a voltage regulator when the processing device operates in a powered-on state [130]
an infrastructure processing unit that maintains state information within an embedded volatile storage based on the retention voltage when the processing device operates in the low-power state and based on the normal voltage when the processing device operates in the powered-on state [102; paragraphs 16-24]
Godey does not explicitly disclose a powered-off state.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Godey by using a powered-off state as the low-power state as a matter of simple design-choice, since it was well-known in the art to use powered-off states to conserve power.
Regarding claim 12, Figure 1 of Godey, as applied to claim 9, does not explicitly disclose wherein the retention voltage interface receives the retention voltage from a power multiplexer when the processing device operates in the powered-off state.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Godey, as applied to claim 9, by using a power multiplexor as a matter of simple design-choice, since it was well-known in the art to use multiplexors to supply voltage.
Regarding claim 14, Figure 1 of Godey, as applied to claim 9, does not explicitly disclose wherein the voltage regulator is a digital low-dropout regulator.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Godey, as applied to claim 9, by using a low-dropout regulator as a matter of simple design-choice, since it was well-known in the art to use low-dropout regulators to supply voltage.
Regarding claim 15, Figure 1 of Godey, as applied to claim 9, discloses wherein the embedded volatile storage includes a portion of volatile memory integrated in the infrastructure processing unit [paragraphs 16-24].
Regarding claim 16, Figure 1 of Godey, as applied to claim 9, discloses wherein the embedded volatile storage includes at least one register of a microcontroller integrated in the infrastructure processing unit [paragraphs 16-24].
Regarding claim 17, Figure 1 of Godey discloses a method comprising:
receiving, by a processing device, a normal voltage supplied from a voltage regulator when operating in a powered-on state [paragraphs 16-24]
generating, by the processing device, state information maintained in volatile storage of the processing device when operating in the powered-on state [paragraphs 16-24]
receiving, by the processing device, a retention voltage when operating in a low-power state [paragraphs 16-24]
when operating in the low-power state in-between periods of operating in the powered-on state, preserving, by the processing device, the state information maintained in the volatile storage based on the retention voltage [paragraphs 16-24]
Godey does not explicitly disclose a power multiplexer when operating in a powered-off state.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Godey by using a power multiplexer to supply retention voltage in a powered-off state as a matter of simple design-choice, since it was well-known in the art to use multiplexers to supply voltages and it would have been a matter of simple substitution of one known element for another to use a powered-off state as the low-power state.
Regarding claim 18, Figure 1 of Godey, as applied to claim 17, discloses wherein the processing device is a graphics processing unit, the method further comprising: rendering, by the processing device, one of two consecutive graphic frames during each of the periods of operating in the powered-on state [paragraphs 16-24].
Regarding claim 20, Figure 1 of Godey, as applied to claim 17, discloses executing, by the processing device, firmware or software that controls the power multiplexer to supply the retention voltage when operating in the powered-off state and suppress the retention voltage when operating in the powered-on state [paragraphs 16-24].
Regarding claim 22, Figure 1 of Godey, as applied to claim 9, discloses wherein the retention voltage is a non-zero voltage that is less than the normal voltage [paragraph 16].
Allowable Subject Matter
Claims 4, 10, 11, 21, and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 06/05/2026 have been fully considered but they are not persuasive.
Applicant argues that it would have not been obvious to one skilled in the art to use a multiplexer to supply multiple supply voltages to the circuit. The examiner disagrees. Figure 1 of Godey teaches providing two different supply voltages to the circuit [see rejection of claim 1 above]. It is well-known in the art to use multiplexers to provide multiple supply voltages [see Figure 4 of Kutz et al (US Patent 6854067) and Figure 2 of King (US Patent 6697952)]. Therefore, it would have been a matter of simple design-choice to use a multiplexer to provide the two different supply voltages of Godey. Thus, the applicant’s argument is not persuasive.
Applicant argues that it would not have been obvious to modify the low power state of Godey to be a power-off state. The examiner disagrees. It would have been an obvious matter of simple design-choice to use a powered-off state as a low power state, since it was well-known in the art to retain circuitry in powered-off states [see paragraph 10 of the instant applications specification for applicant’s own admission that using a powered-off state is known in the art]. Thus, the applicant’s argument is not persuasive.
Applicant argues that Godey does not teach an infrastructure processing unit that maintains state information within an embedded volatile storage. The examiner disagrees. Given broadest reasonable interpretation, the retention hardware of Godey meets the limitations above. Thus, the applicant’s argument is not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tomi S Skibinski whose telephone number is (571)270-7581. The examiner can normally be reached Mon. - Thurs. 8am - 6pm.
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/TOMI SKIBINSKI/Primary Examiner, Art Unit 2836
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