DETAILED ACTION
Claims 1-20 are pending in this action with claims 11-20 withdrawn from consideration. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 5 is objected to because of the following informalities: It appears the word “any” should be removed. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement.
As per claim 1, Examiner was unable to find support in the specification for a value comprising three adjacent bit pairs where the difference between each of the pairs are checked to be the same. The remaining claims are rejected based on dependency.
Examiner suggests either including citations to the supporting paragraphs or amending the claim language.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Conti et al. (US PGPUB No. 2007/0226795) [hereinafter “Conti”] in view of Vorbach et al. (WO-9835299-A2) [hereinafter “Vorbach”].
As per claim 1, Conti teaches the system comprising: a processor (Fig. 18, MPU); a set of devices including a first device that includes a set of registers (Fig. 8 and 18, SSM with registers controlling communications to various memory devices see also [0372]); and a set of firewalls, each configured to couple the processor to a respective device of the set of devices (Fig. 18 and [0372], firewalls controlling traffic using registers), wherein: the set of registers configured to store a first value determined by a plurality of bits ([0372]-[0373], registers store and read bits); and the first device is configured to determine whether to cause a first firewall of the set of firewalls to operate in a bypass mode based on a relationship between values of adjacent bits of the first value ([0372], registers used to enable firewall protection to specific memory devices and when not enabled the firewall protections are “bypassed” see also [0157]-[0159]) (Examiner Note: a “relationship” between values of adjacent bits is interpreted to include bits forming a preset pattern like in a stored identifier. These identifiers will be present in the fields in the “firewall controller register” see [0372]).
Conti does not explicitly teach at least three adjacent bit pairs and determining whether a difference between the values of the bits of each adjacent bit pair is the same for each adjacent bit pair. Vorbach teaches at least three adjacent bit pairs (Page 6, para. 9, multi-bit status flag which are assigned comparison commands) and determining whether a difference between the values of the bits of each adjacent bit pair is the same for each adjacent bit pair (Examiner Note: the instant specification does not appear to disclose or support a “determination” of equal differences but only supports the “selection” by a user of a flag with equal differences, i.e. a flag of “1010” is selected which happens to be equal differences apart see instant application at [0024]– however citations will be provided to teach this determination) (Page 6, para. 6, each status flag is a sequent of multi-bits selected and configured to perform a particular command, like “bypassing a firewall” based on a trigger see Page 5, para. 4, setting up a multiple triggers, i.e. trigger vector based on arithmetic comparisons of values).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Conti with the teachings of Vorbach, at least three adjacent bit pairs and determining whether a difference between the values of the bits of each adjacent bit pair is the same for each adjacent bit pair, to reduce the chance of inadvertent or malicious memory space reading or writing due to bit errors. The “bypassing” feature is taught in Conti and would be combined with Vorbach by inserting this command as the execution command predicated on the trigger and status vectors taught by Vorbach.
As per claim 7, the combination of Conti and Vorbach teaches the system of claim 1, wherein: the set of registers includes a first subset configured to store the first value, and a second subset configured to store a second value; and the first device is configured to determine whether to cause a second firewall of the set of firewalls to operate in a bypass mode based on the second value (Conti; Fig. 18 and [0372], SSM registers control access through multiple firewalls).
As per claim 8, the combination of Conti and Vorbach teaches the system of claim 1, wherein the first firewall is coupled between the processor and the first device (Conti; Fig. 18, firewalls are couple between the MPU processor and the various memory devices, flash, ROM, other firewalls, etc.).
As per claim 9, the combination of Conti and Vorbach teaches the system of claim 1, wherein: the set of devices includes a memory; and the first firewall is coupled between the processor and the memory (Conti; Fig. 18, devices are memory devices with a firewall controlling communications with a MPU processor).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Conti and Vorbach in view of Hedin (US Patent No. 5,872,975) [hereinafter “Hedin”].
As per claim 2, the combination of Conti and Vorbach teaches the system of claim 1, wherein the first device is configured to determine whether to cause the first firewall to operate in the bypass mode (Fig. 18 and [0372], firewalls controlling traffic using registers).
The combination of Conti and Vorbach does not explicitly teach whether for each adjacent bit pair, the value of one bit is the inverse of the other bit. Hedin teaches whether for each adjacent bit pair, the value of one bit is the inverse of the other bit (Col. 8, lines 27-30, bits from 16-31 are paired with bits 0-15 and are validated as inverse bits).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Conti and Vorbach with the teachings of Hedin, whether for each adjacent bit pair, the value of one bit is the inverse of the other bit, to reduce the chance of inadvertent or malicious memory space reading or writing due to bit errors.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Conti and Vorbach in view of Sastry et al. (US PGPUB No. 2012/0079590) [hereinafter “Sastry”].
As per claim 3, the combination of Conti and Vorbach teaches the system of claim 1.
The combination of Conti and Vorbach does not explicitly teach wherein: the set of registers includes a first subset configured to store the first value, and a second subset configured to store a second value determined by a plurality of bits; and the first device is configured to determine whether to lock the first subset and the second subset of the set of registers based on the second value. Sastry teaches wherein: the set of registers includes a first subset configured to store the first value, and a second subset configured to store a second value determined by a plurality of bits ([0040], registers including a control policy register that store values, i.e. two sets of registers); and the first device is configured to determine whether to lock the first subset and the second subset of the set of registers based on the second value ([0040], the control policy register can be loaded with zeros which locks it down along with access to other registers until power-on/reset).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Conti and Vorbach with the teachings of Sastry, wherein: the set of registers includes a first subset configured to store the first value, and a second subset configured to store a second value determined by a plurality of bits; and the first device is configured to determine whether to lock the first subset and the second subset of the set of registers based on the second value, to reduce the chance of inadvertent or malicious tampering of address space that doesn’t need to be changed dynamically.
As per claim 4, the combination of Conti, Vorbach and Sastry teaches the system of claim 3, wherein the first device is configured to, when the second value indicates to lock the first subset and the second subset, prohibit a change to either the first value or the second value until after a power-on-reset event (Sastry; [0040], the control policy register is locked until power-up/reset which prevents access to the other registers).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Conti, Vorbach and Sastry in further view of Hedin.
As per claim 5, the combination of Conti, Vorbach and Sastry teaches the system of claim 3, wherein the first device is configured to determine whether to lock the first subset and the second subset of the set of registers.
Conti does not explicitly teach whether each bit of the second value is an inverse of each adjacent bit of the second value. Hedin teaches whether each bit of the second value is an inverse of each adjacent bit of the second value (Fig. 18 and [0372], firewalls controlling traffic using registers).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Conti with the teachings of Hedin, whether each bit of the second value is an inverse of each adjacent bit of the second value, to reduce the chance of inadvertent or malicious memory space reading or writing due to bit errors.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Conti and Vorbach in view of Unavailable (KR-101412450-B1).
As per claim 6, the combination of Conti and Vorbach teaches the system of claim 1.
The combination of Conti and Vorbach does not explicitly teach receive a second value to store in the set of registers and a set of validation bits; verify the second value based on the set of validation bits; and determine whether to store the second value in the set of registers based on verification of the second value based on the set of validation bits. KR ‘450 teaches receive a second value to store in the set of registers and a set of validation bits (Page 7, para. 1, receiving from processor, data with check bits prior to storage see also Abstract); verify the second value based on the set of validation bits (Page 7, para. 1, validating data with the check bits); and determine whether to store the second value in the set of registers based on verification of the second value based on the set of validation bits (Page 6, para. 3, if verification of data in register using the check bits, fails, the data is removed, i.e. not stored, and replaced).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Conti and Vorbach with the teachings of KR ‘450, receive a second value to store in the set of registers and a set of validation bits; verify the second value based on the set of validation bits; and determine whether to store the second value in the set of registers based on verification of the second value based on the set of validation bits, to reduce time and resource waste during events that have been shown to have a higher likely hood of bitwise errors.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Conti, Vorbach in view of Ansari in further view of Kawamura et al. (JP-2001092686-A) [hereinafter “Kawamura”].
As per claim 10, the combination of Conti and Vorbach teaches the system of claim 1.
The combination of Conti and Vorbach does not explicitly teach a set of registers including a first subset configured to store the first value, and a second subset configured to store a second value; and the first device is configured to determine whether to permit, based on the second value, execution of a function from a group consisting of: a trace function, an emulation function, and a debug function. Ansari teaches a set of registers including a first subset configured to store the first value, and a second subset configured to store a second value ([0022], all operational registers used to store values used in the operations of the SoC) (Examiner Note: This would include the operation codes mentioned below.); and the first device is configured to determine whether to permit, based on the second value ([0020], operation codes are command “values” used to determine which mode the SoC is in which determines which operations can be performed see [0028]), execution of a function from a group consisting of: a trace function and a debug function ([0028], these operations include debug and trace operations).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Conti and Vorbach with the teachings of Ansari, a set of registers including a first subset configured to store the first value, and a second subset configured to store a second value; and the first device is configured to determine whether to permit, based on the second value, execution of a function from a group consisting of: a trace function, an emulation function, and a debug function, to ensure that functionalities can be limited on a system-wide level based on a current objective.
The combination of Conti, Vorbach and Ansari does not explicitly teach an emulation function. Kawamura teaches an emulation function (Page 6, para. 4, setting an emulation mode flag to enter emulation mode to allow functions, i.e. emulator function see Abstract and Page 10, para. 12).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Conti, Vorbach and Ansari with the teachings of Kawamura, an emulation function, to ensure that functionalities can be limited on a system-wide level based on a current objective.
Response to Arguments
Applicant’s arguments with respect to the rejection of claims 1-10 under 35 U.S.C. 103 have been considered. In light of the new amendments, new prior art references, Vorbach and Hedin, have been introduced and cited to.
To expedite prosecution, Examiner is open to an after-final interview to discuss claim amendments to overcome the current rejection and/or place the application in condition for allowance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mueller (US Patent No. 4,747,048), Kondo (US Patent No. 3,871,003), Rohleder et al. (US PGPUB No. 2017/0060669), Stark (US PGPUB No. 2015/0088949), Smith et al. (US PGPUB No. 2013/0298221) all disclose various aspects of the claimed invention including firewall control via memory registers and command/data verification.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER C SHAW whose telephone number is (571)270-7179. The examiner can normally be reached Max Flex.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Carl Colin can be reached at 571-272-3862. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PETER C SHAW/Primary Examiner, Art Unit 2493 September 18, 2026
Prosecution Insights