DETAILED ACTION
Claims 1-20 are pending in this action with claims 11-20 withdrawn from consideration.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/23/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 7-9 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Conti et al. (US PGPUB No. 2007/0226795) [hereinafter “Conti”].
As per claim 1, Conti teaches the system comprising: a processor (Fig. 18, MPU); a set of devices including a first device that includes a set of registers (Fig. 8 and 18, SSM with registers controlling communications to various memory devices see also [0372]); and a set of firewalls, each configured to couple the processor to a respective device of the set of devices (Fig. 18 and [0372], firewalls controlling traffic using registers), wherein: the set of registers configured to store a first value determined by a plurality of bits ([0372]-[0373], registers store and read bits); and the first device is configured to determine whether to cause a first firewall of the set of firewalls to operate in a bypass mode based on a relationship between values of adjacent bits of the first value ([0372], registers used to enable firewall protection to specific memory devices and when not enabled the firewall protections are “bypassed” see also [0157]-[0159]) (Examiner Note: a “relationship” between values of adjacent bits is interpreted to include bits forming a preset pattern like in a stored identifier. These identifiers will be present in the fields in the “firewall controller register” see [0372]).
As per claim 7, Conti teaches the system of claim 1, wherein: the set of registers includes a first subset configured to store the first value, and a second subset configured to store a second value; and the first device is configured to determine whether to cause a second firewall of the set of firewalls to operate in a bypass mode based on the second value (Fig. 18 and [0372], SSM registers control access through multiple firewalls).
As per claim 8, Conti teaches the system of claim 1, wherein the first firewall is coupled between the processor and the first device (Fig. 18, firewalls are couple between the MPU processor and the various memory devices, flash, ROM, other firewalls, etc.).
As per claim 9, Conti teaches the system of claim 1, wherein: the set of devices includes a memory; and the first firewall is coupled between the processor and the memory (Fig. 18, devices are memory devices with a firewall controlling communications with a MPU processor).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Conti in view of Takamoto (JP-H11353200-A).
As per claim 2, Conti teaches the system of claim 1, wherein the first device is configured to determine whether to cause the first firewall to operate in the bypass mode (Fig. 18 and [0372], firewalls controlling traffic using registers).
Conti does not explicitly teach whether any adjacent bits of the plurality of bits determining the first value have the same value. Takamoto teaches whether any adjacent bits of the plurality of bits determining the first value have the same value (Page 2, para. 9, checking all adjacent bits that are of the same logical value in a piece of data when determining whether the piece of data is to be written into memory).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Conti with the teachings of Takamoto, whether any adjacent bits of the plurality of bits determining the first value have the same value, to reduce the chance of inadvertent or malicious memory space reading or writing due to bit errors.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Conti in view of Sastry et al. (US PGPUB No. 2012/0079590) [hereinafter “Sastry”].
As per claim 3, Conti teaches the system of claim 1.
Conti does not explicitly teach wherein: the set of registers includes a first subset configured to store the first value, and a second subset configured to store a second value determined by a plurality of bits; and the first device is configured to determine whether to lock the first subset and the second subset of the set of registers based on the second value. Sastry teaches wherein: the set of registers includes a first subset configured to store the first value, and a second subset configured to store a second value determined by a plurality of bits ([0040], registers including a control policy register that store values, i.e. two sets of registers); and the first device is configured to determine whether to lock the first subset and the second subset of the set of registers based on the second value ([0040], the control policy register can be loaded with zeros which locks it down along with access to other registers until power-on/reset).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Conti with the teachings of Sastry, wherein: the set of registers includes a first subset configured to store the first value, and a second subset configured to store a second value determined by a plurality of bits; and the first device is configured to determine whether to lock the first subset and the second subset of the set of registers based on the second value, to reduce the chance of inadvertent or malicious tampering of address space that doesn’t need to be changed dynamically.
As per claim 4, the combination of Conti and Sastry teaches the system of claim 3, wherein the first device is configured to, when the second value indicates to lock the first subset and the second subset, prohibit a change to either the first value or the second value until after a power-on-reset event (Sastry; [0040], the control policy register is locked until power-up/reset which prevents access to the other registers).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Conti and Sastry in further view of Takamoto.
As per claim 5, the combination of Conti and Sastry teaches the system of claim 3, wherein the first device is configured to determine whether to lock the first subset and the second subset of the set of registers.
Conti does not explicitly teach whether any adjacent bits of the plurality of bits determining the second value have the same value. Takamoto teaches whether any adjacent bits of the plurality of bits determining the second value have the same value (Page 2, para. 9, checking all adjacent bits that are of the same logical value in a piece of data when determining whether the piece of data is to be written into memory).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Conti with the teachings of Takamoto, whether any adjacent bits of the plurality of bits determining the second value have the same value, to reduce the chance of inadvertent or malicious memory space reading or writing due to bit errors.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Conti in view of Unavailable (KR-101412450-B1).
As per claim 6, Conti teaches the system of claim 1.
Conti does not explicitly teach receive a second value to store in the set of registers and a set of validation bits; verify the second value based on the set of validation bits; and determine whether to store the second value in the set of registers based on verification of the second value based on the set of validation bits. KR ‘450 teaches receive a second value to store in the set of registers and a set of validation bits (Page 7, para. 1, receiving from processor, data with check bits prior to storage see also Abstract); verify the second value based on the set of validation bits (Page 7, para. 1, validating data with the check bits); and determine whether to store the second value in the set of registers based on verification of the second value based on the set of validation bits (Page 6, para. 3, if verification of data in register using the check bits, fails, the data is removed, i.e. not stored, and replaced).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Conti with the teachings of KR ‘450, receive a second value to store in the set of registers and a set of validation bits; verify the second value based on the set of validation bits; and determine whether to store the second value in the set of registers based on verification of the second value based on the set of validation bits, to reduce time and resource waste during events that have been shown to have a higher likely hood of bitwise errors.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Conti in view of Ansari in further view of Kawamura et al. (JP-2001092686-A) [hereinafter “Kawamura”].
As per claim 10, Conti teaches the system of claim 1.
Conti does not explicitly teach a set of registers including a first subset configured to store the first value, and a second subset configured to store a second value; and the first device is configured to determine whether to permit, based on the second value, execution of a function from a group consisting of: a trace function, an emulation function, and a debug function. Ansari teaches a set of registers including a first subset configured to store the first value, and a second subset configured to store a second value ([0022], all operational registers used to store values used in the operations of the SoC) (Examiner Note: This would include the operation codes mentioned below.); and the first device is configured to determine whether to permit, based on the second value ([0020], operation codes are command “values” used to determine which mode the SoC is in which determines which operations can be performed see [0028]), execution of a function from a group consisting of: a trace function and a debug function ([0028], these operations include debug and trace operations).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Conti with the teachings of Ansari, a set of registers including a first subset configured to store the first value, and a second subset configured to store a second value; and the first device is configured to determine whether to permit, based on the second value, execution of a function from a group consisting of: a trace function, an emulation function, and a debug function, to ensure that functionalities can be limited on a system-wide level based on a current objective.
The combination of Conti and Ansari does not explicitly teach an emulation function. Kawamura teaches an emulation function (Page 6, para. 4, setting an emulation mode flag to enter emulation mode to allow functions, i.e. emulator function see Abstract and Page 10, para. 12).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Conti and Ansari with the teachings of Kawamura, an emulation function, to ensure that functionalities can be limited on a system-wide level based on a current objective.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nobunaga et al. (US PGPUB No. 2006/0168414), Swobada (US PGPUB No. 2006/0212760), Smith et al. (US PGPUB No. 2013/0298221), Grammatikakis et al. ("Security in MPSoCs: A NoC Firewall and an Evaluation Framework," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 8, pp. 1344-1357, Aug. 2015, doi: 10.1109/TCAD.2015.2448684), Cotret et al. ("Bus-based MPSoC Security through Communication Protection: A Latency-efficient Alternative," 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, Toronto, ON, Canada, 2012, pp. 200-207, doi: 10.1109/FCCM.2012.42), Kayssi et al. ("FPGA-based Internet protocol firewall chip," ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445), Jounieh, Lebanon, 2000, pp. 316-319 vol.1, doi: 10.1109/ICECS.2000.911545) and Achballah et al. ("Toward on hardware firewalling of networks-on-chip based systems," 2017 International Conference on Advanced Systems and Electric Technologies (IC_ASET), Hammamet, Tunisia, 2017, pp. 7-13, doi: 10.1109/ASET.2017.7983658) all disclose various aspects of the claimed invention including firewall control via memory registers and command/data verification.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER C SHAW whose telephone number is (571)270-7179. The examiner can normally be reached Max Flex.
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/PETER C SHAW/Primary Examiner, Art Unit 2493 March 20, 2026