DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' application filed on 07/15/24. Claims 1-15 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, 11, 14 rejected under 35 U.S.C. 103 as being unpatentable over SCHAFMEISTER (US 20240317087 A1 and hereinafter as SCHA) in view of Nakagawa et al. (US 20160020708 A1 and hereinafter as Naka)
Regarding claim 1. SCHA teaches a method [abstract] comprising: operating a power converter arrangement in a first operating mode [mode of fig 2],
wherein the power converter arrangement comprises: a first power converter [PFC] comprising input nodes [see EMV filter],
each of the input nodes configured to receive a respective one of input voltages [i.e. each phase],
each of the input voltages referenced to a first ground node [N],
and the first power converter configured to provide first and second intermediate voltages [i.e. 400v for each input terminal for DC/DC device] each referenced to a second ground node [n];
a second power converter [DC/DC device and hereinafter as DCC] connected between the first power converter and an output of the power converter [i.e. Uout] arrangement,
and wherein operating the power converter arrangement in the first operating mode comprises:
adjusting an input power [i.e. converting input of PFC to 400v] received by the first power converter from the input nodes dependent on an output signal [i.e. detected output signal of fig 11] and dependent on a ground signal [i.e. M],
and adjusting each of the first and second intermediate voltages by the second power converter [i.e. regulated Uout], wherein the ground signal is a signal between the first and second ground nodes,
wherein adjusting the input power comprises obtaining switched node voltage references [gate signals adjusting switches state] dependent on the output signal and the ground signal.
While Scha teaches a circuit wherein adjusting the first intermediate voltage comprises selecting a maximum switched node voltage reference [fig 11, ds1DCDC or ds2DCDC high voltage to switch main switches] of the obtained switched node voltage references and wherein adjusting the second intermediate voltage comprises selecting a minimum switched node voltage reference [fig 11, ds1DCDC or ds2DCDC low voltage to switch main switches] of the obtained switched node voltage references.
However, Scha does not explicitly mention a circuit comprising: adjusting the first intermediate voltage such that the first intermediate voltage tracks the maximum switched node voltage reference, and adjusting the second intermediate voltage such that the second intermediate voltage tracks the minimum of the obtained switched node voltage references.
Naka teaches a circuit comprising: adjusting the first intermediate voltage [LH, fig 1] such that the first intermediate voltage tracks the maximum switched node voltage reference [see figure 1 item 61 senses max value switching reference signal], and adjusting the second intermediate voltage [LL, figure 1] such that the second intermediate voltage tracks the minimum of the obtained switched node voltage references [low value switching reference signal detected by item 61].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Naka in order to ensure that the output voltage is stable and accurate, because knowing exactly when the switch is happening, one of ordinary skill in the art can control the timing and make the output match the intended regulated voltage.
Regarding claim 4. Scha as modified teaches the method of claim 1, wherein the output signal (Sout) is an output current (Iout) [Scha fig11, iL4,BattCharge and iL5,BattCharge] of the power converter arrangement.
Regarding claim 5. Scha as modified teaches the method of claim 1, wherein the output signal (Sout) is an output voltage (Vout) of the power converter arrangement [Scha fig11, UBatt].
Regarding claim 6. Scha as modified teaches the method of claim 1, wherein the ground signal (Syn) is a voltage (Vyn) between the first and second ground nodes (n, y) [voltage at M, Scha].
Regarding claim 7. Scha as modified teaches the method of claim 1, wherein the ground signal (Syn) is a current (Iyn) [i.e. current flowing to any ground node, Scha] between the first and second ground nodes (n, y).
Regarding claim 11. Scha teaches a controller [controller for power converter of figure 2] configured to operate a power converter arrangement in a first operating mode [mode for PFC], wherein the power converter arrangement comprises:
a first power converter (1) [PFC] comprising input nodes (a, b, c) [see EMV filter] each configured to receive a respective one of input voltages (Va, Vb, Vc) [i.e. each input phase] each referenced to a first ground node (n) [N],
and configured to provide first and second intermediate voltages (Vx, Vz) [i.e. for hungry bolts for each input terminal for the DC/DC device] each referenced to a second ground node (y) [n];
a second power converter [DC/DC device and hereinafter as DCC] connected between the first power converter (1) and an output (p, r) of the power converter arrangement [i.e. Uout], and wherein to operate the power converter arrangement in the first operating mode comprises:
to adjust an input power received by the first power converter (1) from the input nodes (a, b, c) dependent on an output signal (Sout) [i.e. regulated Uout] and dependent on a ground signal (Syn),
and to adjust each of the first and second intermediate voltages (Vx) by the second power converter (2) [i.e. adjust 400v to be regulated], wherein the ground signal (Syn) [M] is a signal between the first and second ground nodes (n, y),
wherein to adjust the input power received by the first power converter (1) comprises to obtain switched node voltage references (Va\*, Vb\*, Vc\*) [gate signals adjusting switches state] dependent on the output signal (Sout) and the ground signal (Syn) [figure 11 shows output signals being detected by controller],
While Scha teaches a circuit wherein to adjust the first intermediate voltage (Vx) comprises selecting a maximum switched node voltage reference (Vmax) of the obtained switched node voltage references (Va\*, Vb\*, Vc\*) [fig 11, ds1DCDC or ds2DCDC high voltage to switch main switches], and wherein to adjust the second intermediate voltage (Vz) comprises to select a minimum switched node voltage reference (Vmin) of the obtained switched node voltage references (Va\*, Vb\*, Vc\*) [fig 11, ds1DCDC or ds2DCDC low voltage to switch main switches].
However, Scha does not explicitly mention a circuit and to adjust the first intermediate voltage (Vx) such that the first intermediate voltage (Vx) tracks the maximum (Vmax) switched node voltage reference (Va\*, Vb\*, Vc\*), and to adjust the second intermediate voltage (Vz) such that the second intermediate voltage (Vz) tracks the minimum (Vmin) of the obtained switched node voltage references (Va\*, Vb\*, Vc\*).
Naka teaches a circuit comprising: adjust the first intermediate voltage (Vx) [LH, figure 1] such that the first intermediate voltage (Vx) tracks the maximum (Vmax) switched node voltage reference (Va\*, Vb\*, Vc\*) [see figure 1 item 61 senses max value switching reference signal],
to adjust the second intermediate voltage (Vz) [LL, figure 1] such that the second intermediate voltage (Vz) tracks the minimum (Vmin) of the obtained switched node voltage references (Va\*, Vb\*, Vc\*) [low value switching reference signal detected by item 61].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Naka in order to ensure that the output voltage is stable and accurate, because knowing exactly when the switch is happening, one of ordinary skill in the art can control the timing and make the output match the intended regulated voltage.
Regarding claim 14. Scha as modified teaches the controller of claim 11, wherein the output signal (Sout) is one of an output current (Iout) and an output voltage (Vout) of the power converter arrangement [Scha fig11, iL4,BattCharge and iL5,BattCharge].
Allowable Subject Matter
Claims 2-3,8-10 and 12-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838