DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 15th, 2024 has been considered and the listed references were noted.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Th in Figure 5C (This character could refer to when the description mentions threshold value in Paragraph [0060]).
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because of the following minor informality:
For Figure 2 in S120, “Gererate a color mapping…” should read “Generate a color mapping…”
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informality:
In Paragraph [0003], "As a semiconductor process technology becomes more advanced and a line width become finer, types of defects and the amounts of defects are increasing exponentially." should read "As semiconductor process technology becomes more advanced and the line width for the conductive traces of the circuit on the silicon wafer becomes finer, the types of defects and amounts of defects are increasing exponentially" for better clarity.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) are: …measuring unit…, …coloring unit…, seen in claims 1-3, 8, 10, and 12-13.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 17-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter as follows.
Claim 17 recites “A computer program stored in a storage medium, …”. Computer programs, per se, are not in one of the statutory categories of invention because a computer program is merely a set of instructions capable of being executed by a computer - the computer program itself is not a process. MPEP § 2106.
A computer program, at best, is a functional descriptive material per se. Descriptive material can be characterized as either "functional descriptive material" or "nonfunctional descriptive material." Both types of "descriptive material" are nonstatutory when claimed as descriptive material per se, 33 F.3d at 1360, 31 USPQ2d at 1759. When functional descriptive material is recorded on some computer-readable medium, it becomes structurally and functionally interrelated to the medium and will be statutory in most cases since use of technology permits the function of the descriptive material to be realized. Compare In re Lowry, 32 F.3d 1579, 1583-84, 32 USPQ2d 1031, 1035 (Fed. Cir. 1994) )(discussing patentable weight of data structure limitations in the context of a statutory claim to a data structure stored on a computer readable medium that increases computer efficiency) and >In re Warmerdam, 33 F.3d *>1354, 1360- 61,31 USPQ2d *>1754, 1759 (claim to computer having a specific data structure stored in memory held statutory product-by-process claim) with Warmerdam, 33 F.3d at 1361,31 USPQ2d at 1760 (claim to a data structure per se held nonstatutory). See MPEP 2106.01. Claims 18-20 are rejected under this section of rules, because of their dependency from Claim 17.
The rejection of claim 17 above may be overcome by amending the claim to recite, for example, “A non-transitory computer-readable medium storing a computer program, when is executed by a computer, causing the computer to …”. And the preamble of Claims 18-20 must be amended to recite: “The non-transitory computer-readable medium of claim 17, …”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 8-13, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2019/0026881) in view of Onishi et al. (US 2015/0221076).
Regarding Claim 1, Sato discloses (Sato, Paragraph [0044], discloses: “The scanning electron microscope 100 generates at least one wafer image and the computer 150 obtains the wafer image from the scanning electron microscope 100. A plurality of wafer images may be generated by the scanning electron microscope 100. The wafer image includes a plurality of pattern images. The computer 150 extracts a plurality of pattern images from the wafer image based on the two-dimensional design information included in the design data. These pattern images are images of patterns having the same shape. The number of pattern images to be extracted is preset in the computer 150.”; Paragraph [0045] also discloses: “The computer 150 calculates a variance of gray level in the plurality of pattern images 304 shown in FIG. 7 for each of the inspection areas shown in FIG. 6. The gray level in each inspection area on each pattern image is an average of the gray levels of pixels constituting that inspection area. For example, the gray level in the first inspection area on a pattern image is the average of the gray levels of the pixels that make up the first inspection area. The gray level is generally a numerical value within the range of 0 to 255.”); “a color mapping unit configured to generate a color mapping image, based on the pattern image and the gauge data, by mapping a color corresponding to the gauge data to the one or more pattern regions (Sato, Paragraph [0047], discloses: “Thus, in the present embodiment, the computer 150 creates a false-color image by color-coding the plurality of inspection areas according to magnitude of the variance. The computer 150 displays the false-color image on the display device 164. The false-color image is an RGB image, i.e., an image composed of a combination of red, green, and blue. In one embodiment, the computer 150 is configured to apply blue to an inspection area where the variance of the gray level is lower than a first threshold value, apply green to an inspection area where the variance of the gray level falls within a range from the first threshold value to a second threshold value, and apply red to an inspection area where the variance of the gray level is higher than a third threshold value.”); “wherein (Sato, Paragraph [0046] and Figure 5 (see below), discloses: “The pattern images 304 generated by the scanning electron microscope 100 are SEM images expressed in gray scale. When there is no defect in the patterns, there is substantially no variation in the gray scale among the plurality of pattern images 304 at the same position. However, as shown in FIG. 5, when a defect 203 exists in a pattern 303 on a pattern image 304, the variance of the gray level increases because the defect 203 appears white on that pattern image 304.”).
PNG
media_image1.png
321
419
media_image1.png
Greyscale
Sato does not explicitly disclose “A defect region detection device”. However, in an analogous field of endeavor, Onishi discloses “an SEM inspection apparatus includes an arithmetic processor. The arithmetic processor acquires design data corresponding to an inspection region. The arithmetic processor obtains a resistance component between each of wiring lines included in the inspection region and a portion on a substrate connected thereto, on a basis of the design data. The arithmetic processor obtains a capacitance component between each of the wiring lines included in the inspection region and the portion on the substrate connected thereto, on a basis of the design data. The arithmetic processor color-codes the wiring lines included in the inspection region of the design data, on a basis of a combination of the resistance component and the capacitance component. The arithmetic processor corrects a coordinate deviation between an SEM image and the color-coded design data by performing pattern matching between the color-coded design data and the SEM image” (Onishi, Abstract). The apparatus in this instance is comparable to a device, as it is a physical structure that performs the function described in Claim 1. Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the technique of using gauge data and color mapping seen in Sato with the SEM inspection apparatus seen in Onishi to achieve a complete defect detection device for use in semiconductor manufacturing. By using the method using a computer program and SEM to obtain pattern images of silicon wafers and color mapping the regions seen in Sato with the physical SEM apparatus seen in Onishi, one of ordinary skill in the art can easily assess the patterns seen on recently manufactured silicon wafers and identify the defects efficiently due to the pattern regions being color-coded accordingly. Thus, it would be obvious to combine the Sato and Onishi references to achieve the same defect region detection device described in Claim 1.
Regarding Claim 2, the combination of Sato and Onishi discloses “The defect region detection device of claim 1” (Sato, Paragraph [0044]-[0047], and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 1); “wherein the color mapping unit is configured to assign a color, corresponding to a gauged value of the gauge data to each of the one or more pattern regions, from among a plurality of colors” (Sato, Paragraph [0047], discloses: “Thus, in the present embodiment, the computer 150 creates a false-color image by color-coding the plurality of inspection areas according to magnitude of the variance. The computer 150 displays the false-color image on the display device 164. The false-color image is an RGB image, i.e., an image composed of a combination of red, green, and blue. In one embodiment, the computer 150 is configured to apply blue to an inspection area where the variance of the gray level is lower than a first threshold value, apply green to an inspection area where the variance of the gray level falls within a range from the first threshold value to a second threshold value, and apply red to an inspection area where the variance of the gray level is higher than a third threshold value.”); “wherein the gauged value of the gauge data is included in a range from a first value to a second value, and wherein the plurality of colors are within a gradation color range from a first color corresponding to the first value to a second color corresponding to the second value.” (Sato, Paragraph [0045] and Figure 7 (see below), discloses: “The computer 150 calculates a variance of gray level in the plurality of pattern images 304 shown in FIG. 7 for each of the inspection areas shown in FIG. 6. The gray level in each inspection area on each pattern image is an average of the gray levels of pixels constituting that inspection area. For example, the gray level in the first inspection area on a pattern image is the average of the gray levels of the pixels that make up the first inspection area. The gray level is generally a numerical value within the range of 0 to 255.”; Sato, Paragraph [0012], discloses: “In an embodiment, there is provided a defect detection method comprising: generating pattern images with a scanning electron microscope; superimposing the pattern images while aligning positions of patterns in the pattern images; producing data of gray levels for each of inspection areas on the patterns by obtaining gray levels over the pattern images for each of the inspection areas; determining threshold values corresponding respectively to the inspection areas, based on the data of gray levels; comparing a gray level of each one of pixels in the inspection areas with a corresponding threshold value of the threshold values; applying a first color to pixels having gray levels higher than the threshold value, and applying a second color to pixels having gray levels lower than the threshold value, thereby generating a binary image; and detecting a pattern defect by detecting connected pixels of the first color whose number is equal to or greater than a set number.”). Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to apply the known technique of color mapping using a plurality of colors from assessing the gray levels of the pixels in the image seen in the combination of Sato and Onishi to improve the defect region detection device seen in Claim 2.
Regarding Claim 3, the combination of Sato and Onishi discloses “The defect region detection device of claim 1” (Sato, Paragraph [0044]-[0047], and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 1); “wherein the color mapping unit is configured to assign a first color indicating a defect region to a pattern region included in the one or more pattern regions, wherein the first color corresponds to a first gauged value of the gauge data and wherein the first gauged value is greater than or equal to a threshold value.” (Sato, Paragraph [0012], discloses: “In an embodiment, there is provided a defect detection method comprising: generating pattern images with a scanning electron microscope; superimposing the pattern images while aligning positions of patterns in the pattern images; producing data of gray levels for each of inspection areas on the patterns by obtaining gray levels over the pattern images for each of the inspection areas; determining threshold values corresponding respectively to the inspection areas, based on the data of gray levels; comparing a gray level of each one of pixels in the inspection areas with a corresponding threshold value of the threshold values; applying a first color to pixels having gray levels higher than the threshold value, and applying a second color to pixels having gray levels lower than the threshold value, thereby generating a binary image; and detecting a pattern defect by detecting connected pixels of the first color whose number is equal to or greater than a set number.”). Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the known technique of applying a first color to a gauged value to detect a defect as seen in the combination of Sato and Onishi to improve the defect region detection device in the same way. By using the approach outlined in the combination of Sato and Onishi, one of ordinary skill in the art can easily define a color for the gray levels of the pixels in order to distinctly identify where a defect exists on the wafer, which is clearly described by the references. Thus, it would be obvious for one of ordinary skill in the art to use the technique found in the combination of Shi and Onishi to achieve the same device described in claim 3.
Regarding Claim 8, the combination of Sato and Onishi disclose “The defect region detection device of claim 1” (Sato, Paragraph [0044]-[0047], and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 1); “wherein the gauge data includes a gauged value indicating a size of an area occupied by each of the one or more pattern regions” (Sato, Paragraph [0030], discloses: “Still another object of an embodiment is to provide a method of defining areas for minute-defect visualization and minute-defect detection using design data, so that threshold values for use in a binary image generation belong to the areas that have been defined based on the design data, thereby reducing a calculation amount of the threshold values. The design data is classified into lines, spaces, corners, and pattern ends. In addition, it is possible to calculate independent threshold values for an end portion and a central portion of a pattern, and for patterns with different sizes. Pattern center determination, and subdivision of the areas in accordance with pattern size can be freely set. In other words, it is not necessary to provide one million threshold values for an image of 1,000 pixels in the vertical direction and 1,000 pixels in the horizontal direction. In the embodiment, the threshold values belong to a pattern.”); and “wherein the color mapping unit is configured to assign a first color indicating a defect region to a first pattern region included in the one or more pattern regions” (Sato, Paragraph [0012], discloses: “In an embodiment, there is provided a defect detection method comprising: generating pattern images with a scanning electron microscope; superimposing the pattern images while aligning positions of patterns in the pattern images; producing data of gray levels for each of inspection areas on the patterns by obtaining gray levels over the pattern images for each of the inspection areas; determining threshold values corresponding respectively to the inspection areas, based on the data of gray levels; comparing a gray level of each one of pixels in the inspection areas with a corresponding threshold value of the threshold values; applying a first color to pixels having gray levels higher than the threshold value, and applying a second color to pixels having gray levels lower than the threshold value, thereby generating a binary image; and detecting a pattern defect by detecting connected pixels of the first color whose number is equal to or greater than a set number.”); “wherein the first color corresponds to a first gauged value of the gauge data, and wherein the first gauged value is smaller than a first threshold value and is greater than or equal to a second threshold value” (Sato, Paragraph [0047], discloses: “Thus, in the present embodiment, the computer 150 creates a false-color image by color-coding the plurality of inspection areas according to magnitude of the variance. The computer 150 displays the false-color image on the display device 164. The false-color image is an RGB image, i.e., an image composed of a combination of red, green, and blue. In one embodiment, the computer 150 is configured to apply blue to an inspection area where the variance of the gray level is lower than a first threshold value, apply green to an inspection area where the variance of the gray level falls within a range from the first threshold value to a second threshold value, and apply red to an inspection area where the variance of the gray level is higher than a third threshold value.”). Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to apply the known technique of mapping the color of a pattern region based on its gauged value as described in the combination of Sato and Onishi to improve the defect region detection device in the same way.
Regarding Claim 9, the combination of Sato and Onishi discloses “The defect region detection device of claim 1” (Sato, Paragraph [0044]-[0047], and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 1); “wherein one of the one or more pattern regions includes at least a portion of a first pattern and at least a portion of a second pattern overlapping the first pattern, and wherein the gauge data includes a gauged value indicating an overlay between the first pattern and the second pattern” (Sato, Paragraph [0045] and Figures 6 (see below) and 7 (see below), discloses: “Further, as shown in FIG. 7, the computer 150 superimposes these pattern images 304 while aligning positions of the patterns 303 in the plurality of pattern images 304. For the alignment of the patterns 303, a known technique, such as a normalized cross-correlation method, can be used. The computer 150 calculates a variance of gray level in the plurality of pattern images 304 shown in FIG. 7 for each of the inspection areas shown in FIG. 6. The gray level in each inspection area on each pattern image is an average of the gray levels of pixels constituting that inspection area. For example, the gray level in the first inspection area on a pattern image is the average of the gray levels of the pixels that make up the first inspection area. The gray level is generally a numerical value within the range of 0 to 255.”).
PNG
media_image2.png
527
362
media_image2.png
Greyscale
PNG
media_image3.png
772
580
media_image3.png
Greyscale
In this reference, superimposition is the process of placing one image over another so that both are still visible, which is clearly shown in Figure 7. Accordingly, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to use the technique of overlaying multiple pattern images seen in the combination of Sato and Onishi to improve the overlaying of the first and second pattern in the defect region detection device. By using this technique of properly aligning the first and second pattern images together and detecting the overlap as seen in the combination of Sato and Onishi, one of ordinary skill in the art would be able to verify that the defect region determined by the device is accurate according to what it captured on the surface of the wafer. Therefore, it would be obvious to use the superimposition technique seen in the combination of Sato and Onishi to achieve the same defect region detection device disclosed in Claim 9.
Claim 10 recites a system (wafer defect detection system) with features corresponding to the elements of the apparatus (defect region detection device) recited in Claim 1. Therefore, the recited features of this claim are mapped to the proposed combination in the same manner as the corresponding elements in its corresponding system claim. Additionally, the rationale and motivation to combine the Sato and Onishi references, presented in rejection of Claim 1, apply to this claim. Finally, Sato discloses a measurement device to obtain an SEM image of a wafer, whereas “the image generation system includes a scanning electron microscope 100 and a computer 150 for controlling operations of the scanning electron microscope. The scanning electron microscope 100 includes an electron gun 111 that emits an electron beam composed of primary electrons (charged particles), a converging lens 112 that converges the electron beam emitted from the electron gun 111, an X deflector 113 that deflects the electron beam in an X direction, a Y deflector 114 for deflecting the electron beam in a Y direction, and an objective lens 115 for focusing the electron beam on a wafer 124 which is a specimen.” (Sato, Paragraph [0035]), as well as a method for detecting a defect of a pattern formed on a wafer based on the SEM image (for example, see Sato, Abstract).
Regarding Claim 11, the combination of Sato and Onishi discloses “The wafer defect detection system of claim 10” (Sato, Abstract, Paragraphs [0035] and [0044]-[0047], and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 10); “wherein the measurement device is a SEM device (Sato, Paragraph [0035], discloses: “the image generation system includes a scanning electron microscope 100 and a computer 150 for controlling operations of the scanning electron microscope. The scanning electron microscope 100 includes an electron gun 111 that emits an electron beam composed of primary electrons (charged particles), a converging lens 112 that converges the electron beam emitted from the electron gun 111, an X deflector 113 that deflects the electron beam in an X direction, a Y deflector 114 for deflecting the electron beam in a Y direction, and an objective lens 115 for focusing the electron beam on a wafer 124 which is a specimen.”); and “wherein the SEM image is a gray scale image” (Sato, Paragraph [0046], discloses: “The pattern images 304 generated by the scanning electron microscope 100 are SEM images expressed in gray scale. When there is no defect in the patterns, there is substantially no variation in the gray scale among the plurality of pattern images 304 at the same position. However, as shown in FIG. 5, when a defect 203 exists in a pattern 303 on a pattern image 304, the variance of the gray level increases because the defect 203 appears white on that pattern image 304.”). Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to take the image generation system using SEM that uses gray scale images seen in the combination of Sato and Onishi to improve the system described in Claim 11.
Regarding Claim 12, the combination of Sato and Onishi discloses “The wafer defect detection system of claim 10” (Sato, Abstract, Paragraphs [0035] and [0044]-[0047], and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 10); “wherein the color mapping unit is configured to assign a color, corresponding to a gauged value of the gauge data to each of the one or more pattern regions, from among a plurality of colors, wherein the gauged value of the gauge data is included in a range from a first value to a second value” (Sato, Paragraph [0012], discloses: “In an embodiment, there is provided a defect detection method comprising: generating pattern images with a scanning electron microscope; superimposing the pattern images while aligning positions of patterns in the pattern images; producing data of gray levels for each of inspection areas on the patterns by obtaining gray levels over the pattern images for each of the inspection areas; determining threshold values corresponding respectively to the inspection areas, based on the data of gray levels; comparing a gray level of each one of pixels in the inspection areas with a corresponding threshold value of the threshold values; applying a first color to pixels having gray levels higher than the threshold value, and applying a second color to pixels having gray levels lower than the threshold value, thereby generating a binary image; and detecting a pattern defect by detecting connected pixels of the first color whose number is equal to or greater than a set number.”; Paragraph [0045], discloses: “The gray level in each inspection area on each pattern image is an average of the gray levels of pixels constituting that inspection area. For example, the gray level in the first inspection area on a pattern image is the average of the gray levels of the pixels that make up the first inspection area. The gray level is generally a numerical value within the range of 0 to 255.”); and “wherein the plurality of colors are within a gradation color range from a first color corresponding to the first value to a second color corresponding to the second value” (Sato, Paragraph [0047], discloses: “Thus, in the present embodiment, the computer 150 creates a false-color image by color-coding the plurality of inspection areas according to magnitude of the variance. The computer 150 displays the false-color image on the display device 164. The false-color image is an RGB image, i.e., an image composed of a combination of red, green, and blue. In one embodiment, the computer 150 is configured to apply blue to an inspection area where the variance of the gray level is lower than a first threshold value, apply green to an inspection area where the variance of the gray level falls within a range from the first threshold value to a second threshold value, and apply red to an inspection area where the variance of the gray level is higher than a third threshold value.”). Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to use the technique of mapping specific colors such as a first color corresponding to the first value to a second color corresponding to a second value seen in the combination of Sato and Onishi to improve the wafer defect detection system described in Claim 12.
Regarding Claim 13, the combination of Sato and Onishi discloses “The wafer defect detection system of claim 10” (Sato, Abstract, Paragraphs [0035] and [0044]-[0047], and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 10); “wherein the color mapping unit is configured to assign a first color indicating a defect region to a pattern region included in the one or more pattern regions, wherein the first color corresponds to a first gauged value of the gauge data, and wherein the first gauged value is greater than or equal to a threshold value.” (Sato, Paragraph [0012], discloses: “In an embodiment, there is provided a defect detection method comprising: generating pattern images with a scanning electron microscope; superimposing the pattern images while aligning positions of patterns in the pattern images; producing data of gray levels for each of inspection areas on the patterns by obtaining gray levels over the pattern images for each of the inspection areas; determining threshold values corresponding respectively to the inspection areas, based on the data of gray levels; comparing a gray level of each one of pixels in the inspection areas with a corresponding threshold value of the threshold values; applying a first color to pixels having gray levels higher than the threshold value, and applying a second color to pixels having gray levels lower than the threshold value, thereby generating a binary image; and detecting a pattern defect by detecting connected pixels of the first color whose number is equal to or greater than a set number.”; Sato, Paragraph [0047], discloses: “Thus, in the present embodiment, the computer 150 creates a false-color image by color-coding the plurality of inspection areas according to magnitude of the variance. The computer 150 displays the false-color image on the display device 164. The false-color image is an RGB image, i.e., an image composed of a combination of red, green, and blue. In one embodiment, the computer 150 is configured to apply blue to an inspection area where the variance of the gray level is lower than a first threshold value, apply green to an inspection area where the variance of the gray level falls within a range from the first threshold value to a second threshold value, and apply red to an inspection area where the variance of the gray level is higher than a third threshold value.”). Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to use the method to detect a defect region using color mapping to assign a first color to a region based off the gauged value being greater than the threshold value seen in the combination of Sato and Onishi to improve the system described in Claim 13 in the same way.
Claim 17 recites a program with instructions corresponding to the features recited in Claim 10. Therefore, the recited programming instructions of this claim are mapped to the proposed combination in the same manner as the corresponding steps in its corresponding system claim. Additionally, the rationale and motivation to combine the Sato and Onishi references, presented in rejection of Claim 10, apply to this claim. Finally, the combination of Sato and Onishi references discloses a computer readable storage medium (for example, see Sato, Paragraph [0063]).
Regarding Claim 18, the combination of Sato and Onishi discloses “The computer program of claim 17, wherein the computer program, when is executed, further causes the computer to” (Sato, Abstract, Paragraphs [0012], [0035], [0044]-[0047], [0063] and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 17); “assign a color, corresponding to a gauged value of the gauge data to each of the one or more pattern regions, from among a plurality of colors, wherein the gauged value of the gauge data is included in a range from a first value to a second value” (Sato, Paragraph [0012], discloses: “In an embodiment, there is provided a defect detection method comprising: generating pattern images with a scanning electron microscope; superimposing the pattern images while aligning positions of patterns in the pattern images; producing data of gray levels for each of inspection areas on the patterns by obtaining gray levels over the pattern images for each of the inspection areas; determining threshold values corresponding respectively to the inspection areas, based on the data of gray levels; comparing a gray level of each one of pixels in the inspection areas with a corresponding threshold value of the threshold values; applying a first color to pixels having gray levels higher than the threshold value, and applying a second color to pixels having gray levels lower than the threshold value, thereby generating a binary image; and detecting a pattern defect by detecting connected pixels of the first color whose number is equal to or greater than a set number.”; Paragraph [0045], discloses: “The gray level in each inspection area on each pattern image is an average of the gray levels of pixels constituting that inspection area. For example, the gray level in the first inspection area on a pattern image is the average of the gray levels of the pixels that make up the first inspection area. The gray level is generally a numerical value within the range of 0 to 255.”); and “wherein the plurality of colors are within a gradation color range from a first color corresponding to the first value to a second color corresponding to the second value” (Sato, Paragraph [0047], discloses: “Thus, in the present embodiment, the computer 150 creates a false-color image by color-coding the plurality of inspection areas according to magnitude of the variance. The computer 150 displays the false-color image on the display device 164. The false-color image is an RGB image, i.e., an image composed of a combination of red, green, and blue. In one embodiment, the computer 150 is configured to apply blue to an inspection area where the variance of the gray level is lower than a first threshold value, apply green to an inspection area where the variance of the gray level falls within a range from the first threshold value to a second threshold value, and apply red to an inspection area where the variance of the gray level is higher than a third threshold value.”). Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to use the technique of mapping specific colors such as a first color corresponding to the first value to a second color corresponding to a second value seen in the combination of Sato and Onishi to improve the computer-readable storage medium described in Claim 18.
Regarding Claim 19, the combination of Sato and Onishi discloses “The computer program of claim 17, wherein the computer program, when is executed, further causes the computer to” (Sato, Abstract, Paragraphs [0012], [0035], [0044]-[0047], [0063] and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 17); “assign a first color indicating a defect region to a pattern region included in the one or more pattern regions, wherein the first color corresponds to a first gauged value of the gauge data, and wherein the first gauged value is greater than or equal to a threshold value.” (Sato, Paragraph [0012], discloses: “In an embodiment, there is provided a defect detection method comprising: generating pattern images with a scanning electron microscope; superimposing the pattern images while aligning positions of patterns in the pattern images; producing data of gray levels for each of inspection areas on the patterns by obtaining gray levels over the pattern images for each of the inspection areas; determining threshold values corresponding respectively to the inspection areas, based on the data of gray levels; comparing a gray level of each one of pixels in the inspection areas with a corresponding threshold value of the threshold values; applying a first color to pixels having gray levels higher than the threshold value, and applying a second color to pixels having gray levels lower than the threshold value, thereby generating a binary image; and detecting a pattern defect by detecting connected pixels of the first color whose number is equal to or greater than a set number.”; Sato, Paragraph [0047], discloses: “Thus, in the present embodiment, the computer 150 creates a false-color image by color-coding the plurality of inspection areas according to magnitude of the variance. The computer 150 displays the false-color image on the display device 164. The false-color image is an RGB image, i.e., an image composed of a combination of red, green, and blue. In one embodiment, the computer 150 is configured to apply blue to an inspection area where the variance of the gray level is lower than a first threshold value, apply green to an inspection area where the variance of the gray level falls within a range from the first threshold value to a second threshold value, and apply red to an inspection area where the variance of the gray level is higher than a third threshold value.”). Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to use the method to detect a defect region using color mapping to assign a first color to a region based off the gauged value being greater than the threshold value seen in the combination of Sato and Onishi to improve the system described in Claim 19 in the same way.
Claims 4-5, 14-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Onishi, and further in view of Jung et al. (US 2016/0189369) and Hunsche et al. (US 2022/0327364).
Regarding Claim 4, the combination of Sato and Onishi discloses “The defect region detection device of claim 1” (Sato, Paragraph [0044]-[0047], and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 1); (Jung, Paragraph [0038]). Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the defect region detection device seen in the combination of Sato and Onishi with the technique of obtaining a hole pattern seen in Jung to achieve the above-described limitation in Claim 4.
The combination of Sato, Onishi, and Jung does not explicitly disclose “and wherein the gauge data includes a gauged value indicating a critical dimension of the hole pattern”. However, in an analogous field of endeavor, Hunsche discloses “The (e.g., semiconductor) patterning device can comprise, or can form, one or more design layouts. The design layout can be generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional design layouts/patterning devices. These rules are set by processing and design limitations. For example, design rules define the space tolerance between devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the devices or lines do not interact with one another in an undesirable way. The design rules may include and/or specify specific parameters, limits on and/or ranges for parameters, and/or other information. One or more of the design rule limitations and/or parameters may be referred to as a “critical dimension” (CD). A critical dimension of a device can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes, or other features. Thus, the CD determines the overall size and density of the designed device. One of the goals in device fabrication is to faithfully reproduce the original design intent on the substrate (via the patterning device).” (Hunsche, Paragraph [0145]). Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the defect region detection device capable of making hole patterns seen in the combination of Sato, Onishi, and Jung with the technique of measuring the critical dimension of the hole pattern seen in Hunsche to achieve the same defect detection device described in Claim 4.
Regarding Claim 5, the combination of Sato and Onishi discloses “The defect region detection device of claim 1” (Sato, Paragraph [0044]-[0047], and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 1); (Jung, Paragraph [0038]). Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the defect region detection device seen in the combination of Sato and Onishi with the technique of obtaining a hole pattern seen in Jung to achieve the above-described limitation in Claim 5.
The combination of Sato, Onishi, and Jung does not explicitly disclose “and wherein the gauge data includes a gauged value indicating a size of the hole pattern”. However, in an analogous field of endeavor, Hunsche discloses “The (e.g., semiconductor) patterning device can comprise, or can form, one or more design layouts. The design layout can be generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional design layouts/patterning devices. These rules are set by processing and design limitations. For example, design rules define the space tolerance between devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the devices or lines do not interact with one another in an undesirable way. The design rules may include and/or specify specific parameters, limits on and/or ranges for parameters, and/or other information. One or more of the design rule limitations and/or parameters may be referred to as a “critical dimension” (CD). A critical dimension of a device can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes, or other features. Thus, the CD determines the overall size and density of the designed device. One of the goals in device fabrication is to faithfully reproduce the original design intent on the substrate (via the patterning device).” (Hunsche, Paragraph [0145]). Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the defect region detection device capable of making hole patterns seen in the combination of Sato, Onishi, and Jung with the technique of measuring the size of the hole pattern seen in Hunsche to achieve the same defect detection device described in Claim 5.
Regarding Claim 14, the combination of Sato and Onishi discloses “The wafer defect detection system of claim 10” (Sato, Abstract, Paragraphs [0035] and [0044]-[0047], and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 10); (Jung, Paragraph [0038]). Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the defect region detection device seen in the combination of Sato and Onishi with the technique of obtaining a hole pattern seen in Jung to achieve the above-described limitation in Claim 14.
The combination of Sato, Onishi, and Jung does not explicitly disclose “and wherein the gauge data includes a gauged value indicating a critical dimension of the hole pattern”. However, in an analogous field of endeavor, Hunsche discloses “The (e.g., semiconductor) patterning device can comprise, or can form, one or more design layouts. The design layout can be generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional design layouts/patterning devices. These rules are set by processing and design limitations. For example, design rules define the space tolerance between devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the devices or lines do not interact with one another in an undesirable way. The design rules may include and/or specify specific parameters, limits on and/or ranges for parameters, and/or other information. One or more of the design rule limitations and/or parameters may be referred to as a “critical dimension” (CD). A critical dimension of a device can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes, or other features. Thus, the CD determines the overall size and density of the designed device. One of the goals in device fabrication is to faithfully reproduce the original design intent on the substrate (via the patterning device).” (Hunsche, Paragraph [0145]). Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the wafer defect detection system capable of making hole patterns seen in the combination of Sato, Onishi, and Jung with the technique of measuring the critical dimension of the hole pattern seen in Hunsche to achieve the wafer defect detection system described in Claim 14.
Regarding Claim 15, the combination of Sato and Onishi discloses “The wafer defect detection system of claim 10” (Sato, Abstract, Paragraphs [0035] and [0044]-[0047], and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 10); (Jung, Paragraph [0038]). Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the defect region detection device seen in the combination of Sato and Onishi with the technique of obtaining a hole pattern seen in Jung to achieve the above-described limitation in Claim 15.
The combination of Sato, Onishi, and Jung does not explicitly disclose “and wherein the gauge data includes a gauged value indicating a size of the hole pattern”. However, in an analogous field of endeavor, Hunsche discloses “The (e.g., semiconductor) patterning device can comprise, or can form, one or more design layouts. The design layout can be generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional design layouts/patterning devices. These rules are set by processing and design limitations. For example, design rules define the space tolerance between devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the devices or lines do not interact with one another in an undesirable way. The design rules may include and/or specify specific parameters, limits on and/or ranges for parameters, and/or other information. One or more of the design rule limitations and/or parameters may be referred to as a “critical dimension” (CD). A critical dimension of a device can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes, or other features. Thus, the CD determines the overall size and density of the designed device. One of the goals in device fabrication is to faithfully reproduce the original design intent on the substrate (via the patterning device).” (Hunsche, Paragraph [0145]). Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the wafer defect detection system capable of making hole patterns seen in the combination of Sato, Onishi, and Jung with the technique of measuring the size of the hole pattern seen in Hunsche to achieve the same wafer defect detection system described in Claim 15.
Regarding Claim 20, the combination of Sato and Onishi discloses “The computer program of claim 17” (Sato, Abstract, Paragraphs [0012], [0035], [0044]-[0047], [0063] and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 17); (Jung, Paragraph [0038]). Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the defect region detection device seen in the combination of Sato and Onishi with the technique of obtaining a hole pattern seen in Jung to achieve the above-described limitation in Claim 20.
The combination of Sato, Onishi, and Jung does not explicitly disclose “and wherein the gauge data includes a gauged value indicating a critical dimension of the hole pattern”. However, in an analogous field of endeavor, Hunsche discloses “The (e.g., semiconductor) patterning device can comprise, or can form, one or more design layouts. The design layout can be generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional design layouts/patterning devices. These rules are set by processing and design limitations. For example, design rules define the space tolerance between devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the devices or lines do not interact with one another in an undesirable way. The design rules may include and/or specify specific parameters, limits on and/or ranges for parameters, and/or other information. One or more of the design rule limitations and/or parameters may be referred to as a “critical dimension” (CD). A critical dimension of a device can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes, or other features. Thus, the CD determines the overall size and density of the designed device. One of the goals in device fabrication is to faithfully reproduce the original design intent on the substrate (via the patterning device).” (Hunsche, Paragraph [0145]). Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the wafer defect detection system capable of making hole patterns seen in the combination of Sato, Onishi, and Jung with the technique of measuring the critical dimension of the hole pattern seen in Hunsche to achieve the computer-readable storage medium described in Claim 20.
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Onishi, and further in view of Nishihata et al. (US 2021/0027983).
Regarding Claim 6, the combination of Sato and Onishi disclose “The defect region detection device of claim 1” (Sato, Paragraph [0044]-[0047], and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 1); (Nishihata, Paragraph [0071] and Figures 5A, 5B, and 5C (see below)).
PNG
media_image4.png
50
383
media_image4.png
Greyscale
PNG
media_image4.png
50
383
media_image4.png
Greyscale
PNG
media_image5.png
463
431
media_image5.png
Greyscale
Here, we can see that there are multiple pairs of holes that are adjacent to each other at an equal pitch, with Nishihata’s invention having the ability to measure the pitch through further imaging. Nishihata also discloses that “A database of the relationship among the pattern density, the depth and the image signal used here will be described. As a method of creating the database, there is a method of using a standard sample in which the pattern density and the depth of the hole change in a stepwise manner. An image signal and a pattern dimension such as a hole diameter or a pitch of the hole portion is acquired by imaging the standard sample, and the depth of the hole is obtained by a cross-sectional analysis or the like. As shown in FIG. 7, the relationship among a pattern density 701, a depth 702, and an image signal 703 obtained from the hole diameter, the pitch, and the like is stored as a database.” (Nishihata, Paragraph [0071] and Figure 7 (see below)).
PNG
media_image6.png
359
515
media_image6.png
Greyscale
Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the defect region detection device seen in the combination of Sato and Onishi with the technique of obtaining the pitch between two hole patterns seen in Nishihata to obtain the same device disclosed in Claim 6
Regarding Claim 16, the combination of Sato and Onishi disclose “The wafer defect detection system of claim 10” (Sato, Abstract, Paragraphs [0035] and [0044]-[0047], and Figure 5; Onishi, Abstract; please see above-described analysis for Claim 10); (Nishihata, Paragraph [0071] and Figures 5A, 5B, and 5C (see below)).
PNG
media_image4.png
50
383
media_image4.png
Greyscale
PNG
media_image4.png
50
383
media_image4.png
Greyscale
PNG
media_image5.png
463
431
media_image5.png
Greyscale
Here, we can see that there are multiple pairs of holes that are adjacent to each other at an equal pitch, with Nishihata’s invention having the ability to measure the pitch through further imaging. Nishihata also discloses that “A database of the relationship among the pattern density, the depth and the image signal used here will be described. As a method of creating the database, there is a method of using a standard sample in which the pattern density and the depth of the hole change in a stepwise manner. An image signal and a pattern dimension such as a hole diameter or a pitch of the hole portion is acquired by imaging the standard sample, and the depth of the hole is obtained by a cross-sectional analysis or the like. As shown in FIG. 7, the relationship among a pattern density 701, a depth 702, and an image signal 703 obtained from the hole diameter, the pitch, and the like is stored as a database.” (Nishihata, Paragraph [0071] and Figure 7 (see below)).
PNG
media_image6.png
359
515
media_image6.png
Greyscale
Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the wafer defect detection system seen in the combination of Sato and Onishi with the technique of obtaining the pitch between two hole patterns seen in Nishihata to obtain the same wafer defect detection system disclosed in Claim 16.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Onishi, and further in view of Yamaguchi et al. (US 2015/0060667) and Hunsche.
Regarding Claim 7, the combination of Sato and Onishi discloses “The defect region detection device of claim 1” (Yamaguchi, Paragraph [0050] and Figure 11 (see below))
PNG
media_image7.png
236
477
media_image7.png
Greyscale
Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the defect region detection device disclosed in the combination of Sato and Onishi with the technique for obtaining a line pattern in the pattern seen in Yamaguchi to achieve the above-described limitation in Claim 7.
The combination of Sato, Onishi, and Yamaguchi does not explicitly disclose “and wherein the gauge data includes a gauged value indicating a critical dimension of the line pattern”. However, in an analogous field of endeavor, Hunsche discloses “The (e.g., semiconductor) patterning device can comprise, or can form, one or more design layouts. The design layout can be generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional design layouts/patterning devices. These rules are set by processing and design limitations. For example, design rules define the space tolerance between devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the devices or lines do not interact with one another in an undesirable way. The design rules may include and/or specify specific parameters, limits on and/or ranges for parameters, and/or other information. One or more of the design rule limitations and/or parameters may be referred to as a “critical dimension” (CD). A critical dimension of a device can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes, or other features. Thus, the CD determines the overall size and density of the designed device. One of the goals in device fabrication is to faithfully reproduce the original design intent on the substrate (via the patterning device)” (Hunsche, Paragraph [0045]). Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the defect detection device capable of producing pattern images with a line pattern as seen in the combination of Sato, Onishi, and Yamaguchi with the technique of measuring the critical dimension of the line pattern as seen in Hunsche to achieve a complete improvement in the device described in Claim 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gao et al. (US 2015/0221076) teaches systems and methods for classifying defects detected on a wafer using attributes for one of the defects based on a standard reference image corresponding to at least one defect.
Houbin et al. (WO 2023083559 A1) teaches systems and methods for image analysis, including obtaining a plurality of simulation and non-simulation images of a location on the sample not imaged by the non-simulation images.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SORIE I KOROMA JR whose telephone number is (571)272-9259. The examiner can normally be reached Monday - Friday 8AM-6:00PM; Alternate Fridays Off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amandeep Saini can be reached at 571-272-3382. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SORIE I KOROMA JR/Examiner, Art Unit 2662
/AMANDEEP SAINI/Supervisory Patent Examiner, Art Unit 2662
Prosecution Insights