Prosecution Insights
Last updated: April 19, 2026
Application No. 18/772,885

SYSTEM AND METHOD FOR PRE-SOFT-DECODING TRACKING FOR NAND FLASH MEMORIES

Non-Final OA §DP
Filed
Jul 15, 2024
Examiner
HO, HOAI V
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kioxia Corporation
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
To Grant
98%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allow Rate
1010 granted / 1091 resolved
+24.6% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
21 currently pending
Career history
1112
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
25.5%
-14.5% vs TC avg
§102
40.0%
+0.0% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1091 resolved cases

Office Action

§DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 1. This office acknowledges receipt of the following item(s) from the Applicant: Information Disclosure Statement (IDS) was considered. 2. Claims 1-20 are presented for examination. Double Patenting 3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b). Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. 4. Claims 1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-20 of Weingarten U.S. Patent No. 12039191. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows: Claims 1-12 of the examined application are anticipated and the same scope of invention by claims 1-13 of the reference such as a method for performing operations on a flash memory, the method comprising: obtaining a first soft read sample by performing a first read operation on a location of the flash memory with a first reference voltage; determining a second reference voltage based on the first soft read sample; obtaining a second soft read sample by performing a second read operation on the location of the flash memory with the second reference voltage; generating soft information based on the first and second soft read samples; and decoding a result of a third read operation on the location of the flash memory based on the soft information. Claims 13-17 of the examined application are anticipated and the same scope of invention by claims 14-19 of the reference such as a flash memory system comprising: a flash memory; and a circuit for performing operations on the flash memory, the circuit being configured to: obtain a first soft read sample by performing a first read operation on a location of the flash memory with a first reference voltage; determine a second reference voltage based on the first soft read sample; obtain a second soft read sample by performing a second read operation on the location of the flash memory with the second reference voltage; generate soft information based on the first and second soft read samples; and decode result of a third read operation on the location of the flash memory based on the soft information. Claims 18-20 of the examined application are anticipated and the same scope of invention by claims 14 and 18-20 of the reference such as a method for performing operations on a flash memory, the method comprising: obtaining one or more soft read samples; estimating reference voltages from the one or more soft read samples; and performing read operations on locations of the flash memory with the estimated reference voltages, wherein estimating reference voltages comprises: determining a sampling range based on a first one of the one more soft read samples; determining a second reference voltage from within the sampling range; and generating a histogram based on the one or more soft read samples, wherein determining the sampling range comprises: updating the histogram based on the first soft read sample, and determining the sampling range based on the histogram. 5. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs. 6. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)). 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hoai V. Ho whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /HOAI V HO/Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Jul 15, 2024
Application Filed
Aug 07, 2024
Response after Non-Final Action
Jan 29, 2026
Non-Final Rejection — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12597450
PULSE BASED MULTI-LEVEL CELL PROGRAMMING
2y 5m to grant Granted Apr 07, 2026
Patent 12592266
MEMORY DEVICE INCLUDING VOLTAGE GENERATING CIRCUIT AND OPERATION METHOD OF MEMORY DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12592265
SEMICONDUCTOR DEVICE AND TRAINING METHOD OF THE SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12593432
SEMICONDUCTOR DEVICE INCLUDING LAYER COMPRISING MEMORY CELL
2y 5m to grant Granted Mar 31, 2026
Patent 12588512
GENERATION OF PHYSICALLY UNCLONABLE FUNCTION USING ONE-TIME-PROGRAMMABLE MEMORY DEVICES WITH BACKSIDE INTERCONNECT STRUCTURES
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
98%
With Interview (+5.5%)
1y 11m
Median Time to Grant
Low
PTA Risk
Based on 1091 resolved cases by this examiner. Grant probability derived from career allow rate.

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