DETAILED ACTION
This Office Action is in response to the Amendment filed on 02/02/2026.
In the filed response, no claims have been amended.
Accordingly, Claims 1-20 have been examined and are pending. This Action is made FINAL.
Information Disclosure Statement
1. The information disclosure statement (IDS) was submitted on 02/02/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
2. Applicant’s arguments, see pgs. 9-11, filed 02/02/2026, with respect to the prior art rejections of the instant claims under 35 U.S.C. 102(a)(1), 102(a)(2), and 103 have been fully considered and are persuasive. Therefore, the prior art rejections have been withdrawn. As to the rejections, under 35 U.S.C. 112(b), Applicant’s arguments (see pg. 8) have been fully considered and are persuasive. Therefore, the rejections under 35 U.S.C. 112(b) have also been withdrawn. The foregoing rejections were also discussed during the interview dated 12 January 2026. Please see attached interview summary. However, upon further consideration of Applicant’s filed IDS (above), a new ground(s) of rejection is made in view of document EP-3258691-A1 (Hitachi Information & Telecommunication ENG LTD [JP]) 20 December 2017, hereinafter referred to as Saito. Please see examiner’s response below.
3. After carefully considering Applicant’s filed IDS on 02/02/2026, the examiner finds prior art Saito to be relevant art in light of the claims, given their broadest reasonable interpretation (BRI). Further relied on is the work of Watanabe et al. US 2008/0063082 A1 which was also identified in the IDS above. For the reasons elaborated on below, this office action is made final.
4. The Examiner is available to discuss the matters of this office action to help move the Instant Application forward. Please refer to the conclusion to this office action regarding scheduling interviews.
5. Accordingly, Claims 1-20 have been examined and are pending.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5-9, 11, 13, and 15-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Saito et al. EP-3258691-A1 (IDS dated 02/02/2026), hereinafter referred to as Saito, since Saito discloses a means for reducing the power consumption in an image compression/decompression device (fig. 1) according to the use purpose of a user, in which a resolution, a frame rate, and a bit rate are considered (e.g. abstract). Please see below for details.
Regarding Claim 1, (Original): Given the broadest reasonable interpretation (BRI) of the following limitations, Saito teaches and/or suggests “An apparatus configured to code video data [See for e.g. fig. 1 with respect to a device for performing image compression and decompression], the apparatus comprising: a video syntax processing (VSP) engine configured to process the video data at a syntax element level [¶0016-¶0017 describe variable length encoding/decoding processing for performing entropy encoding. Also note ¶0085 regarding CABAC. The foregoing aligns with the VSP performing tasks such as entropy coding (e.g. CABAC) as shown in ¶0045 of the filed specification). Refer to elements 124 and 125 in for e.g. figs. 1 and 15B.]; a video pixel processing (VPP) engine configured to process the video data at a pixel level [¶0016-¶0017 further describe image processing units as shown in figs. 1 and 15B (e.g. elements 101-104) which undertake a motion compensation process. Said image processing is at a pixel level (e.g. ¶0083). Also note the various processing stages in fig. 4]; and a controller configured to control a power of the VSP engine based on the VSP engine being idle.” [Given the BRI of the limitation, please see for e.g. ¶0079-¶0082 with respect to controlling the above processing according to power control, where said control can be performed individually. Power switching via power supply control unit according to the presence or absence of an operation is illustrated in fig. 15B]
Regarding Claim 3, (Original): Saito teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Saito further teaches and/or suggests “wherein the VSP engine and the VPP engine are configured to encode the video data [As to the foregoing processing, see fig. 1 with further reference to figs. 11-12], wherein the VSP engine and the VPP engine are configured to process a same frame of the video data [Same citations above], wherein the VPP engine is configured to start processing the same frame of the video data before the VSP engine [Figs. 11-12 show that image processing units begin processing before the variable length encoding/decoding processing], wherein the VSP engine is in a power off state when the VPP engine starts processing the same frame of the video data [See fig. 11. Also refer to for e.g. ¶0082], and wherein the controller is configured to power on the VSP engine at a time after the VPP engine has started processing the same frame of the video data [See the timing chart of the image compression process in fig. 12] based on a relative processing speed of the VSP engine and the VPP engine. [Regarding processing speeds, see for e.g. ¶0083]
Regarding Claim 5, (Original): Saito teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Saito further teaches and/or suggests “further comprising a memory configured to store syntax element data generated by the VSP engine [See fig. 6 with respect to the use of external memory by both processing units during a decompression operation. Element 124 stores processed data in intermediate buffer 310], wherein the VSP engine and the VPP engine are configured to decode the video data [Same as above], wherein the VSP engine and the VPP engine are configured to process different frames of the video data in parallel [See Saito’s parallel arrangement depicted in figs. 9 and 10 which illustrate compression and decompression operations, respectively, for processing different frames of video data], wherein the VSP engine is configured to store frames of syntax element data in the memory [Please note the use of memory shown in the above figures], and wherein the controller is configured to power off the VSP engine based on the memory having greater than a first threshold number of frames of syntax element data.” [Although not explicit, when considering the foregoing operations, please see for e.g. ¶0062 regarding buffer control between image processing and the variable length encoding/decoding processing. Also note figs. 15A-15B with respect to power control. Controlling power to the processors in order to prevent overflow/underflow of the buffer would be considered within the level of skill in the art]
Regarding Claim 6, (Original): Saito teaches and/or suggests all the limitations of claim 5, and is analyzed as previously discussed with respect to that claim. Saito further teaches and/or suggests “wherein the VPP engine is configured to process the frames of syntax element data in the memory [See figs. 5-6 along with figs. 9-10 with respect to the memory shown], and wherein the controller is configured to power on the VSP engine based on the memory having less than a second threshold number of frames of syntax element data.” [Although not explicit, when considering the foregoing operations, please see for e.g. ¶0062 regarding buffer control between image processing and the variable length encoding/decoding processing. Also note figs. 15A-15B with respect to power control. Controlling power to the processors in order to prevent overflow/underflow of the buffer would be considered within the level of skill in the art]
Regarding Claim 7, (Original): Saito teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Saito further teaches and/or suggests “a memory configured to store syntax element data generated by the VSP engine [See figs. 5-6 and 9-10 with respect to the memory shown], wherein the VSP engine and the VPP engine are configured to encode the video data [Same as above, where figs. 5 and 9 pertain to compression], wherein the VSP engine and the VPP engine are configured to process different frames of the video data in parallel [See the parallel arrangement in fig. 9 for processing different frames of video data], wherein the VPP engine is configured to store frames of syntax element data in the memory [Note the use of an intermediate buffer for storing output from the image processing units as shown], and wherein the controller is configured to power on the VSP engine based on the memory having greater than a first threshold number of frames of syntax element data.” [Although not explicit, when considering the foregoing operations, please see for e.g. ¶0062 regarding buffer control between image processing and the variable length encoding/decoding processing. Also note figs. 15A-15B with respect to power control. Controlling power to the processors in order to prevent overflow/underflow of the buffer would be considered within the level of skill in the art]
Regarding Claim 8, (Original): Saito teaches and/or suggests all the limitations of claim 7, and is analyzed as previously discussed with respect to that claim. Saito further teaches and/or suggests “wherein the VSP engine is configured to process the frames of syntax element data in the memory [See figs. 5-6 along with figs. 9-10 with respect to the memory shown], and wherein the controller is configured to power off the VSP engine based on the memory having zero frames of syntax element data.” [Although not explicit, when considering the foregoing operations, please see for e.g. ¶0062 regarding buffer control between image processing and the variable length encoding/decoding processing. Also note figs. 15A-15B with respect to power control. Controlling power to the processors in order to prevent overflow/underflow of the buffer would be considered within the level of skill in the art]
Regarding Claim 9, (Original): Saito teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Saito further teaches and/or suggests “wherein the VSP engine is configured to perform context adaptive binary arithmetic coding (CABAC) [See for e.g. ¶0084-¶0085 for support] and operates at a first processing speed based on bits of data [Same citation as above, where processing time changes significantly according to the number of bits to be processed], and wherein the VPP engine is configured to perform one or more of transform processing, prediction, or filtering [See the stage process names listed in for e.g. figs. 4 and 8 (e.g. de-blocking filter). Also refer to ¶0029-¶0030 and ¶0083], and operates at a second processing speed based on pixels of data, wherein the second processing speed is slower than the first processing speed.” [Please refer to ¶0029-¶0030 and ¶0083 for support. Also note ¶0035 with respect to the resolution, frame rate and bitrate being variably input]
Regarding claim 11, claim 11 is rejected under the same art and evidentiary limitations as determined for the apparatus of Claim 1.
Regarding claim 13, claim 13 is rejected under the same art and evidentiary limitations as determined for the apparatus of Claim 3.
Regarding claim 15, claim 15 is rejected under the same art and evidentiary limitations as determined for the apparatus of Claim 5.
Regarding claim 16, claim 16 is rejected under the same art and evidentiary limitations as determined for the apparatus of Claim 6.
Regarding claim 17, claim 17 is rejected under the same art and evidentiary limitations as determined for the apparatus of Claim 5, since encoding and decoding are inverse operations of each other, where compressed video data can be decompressed and viewed at a destination device. See for e.g. the encoding and decoding operations illustrated in figs. 5 and 6 of Saito, respectively.
Regarding claim 18, claim 18 is rejected under the same art and evidentiary limitations as determined for the apparatus of Claim 8.
Regarding claim 19, claim 19 is rejected under the same art and evidentiary limitations as determined for the apparatus of Claim 9.
Regarding claim 20, claim 20 is rejected under the same art and evidentiary limitations as determined for the apparatus of Claim 1.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Saito, in view of Watanabe et al. US 2008/0063082 A1, hereinafter referred to as Watanabe.
Regarding Claim 2, (Original): Saito teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Saito further teaches and/or suggests “wherein the VSP engine and the VPP engine are configured to decode the video data [As to the foregoing processing, see fig. 1 with further reference to figs. 13-14], wherein the VSP engine and the VPP engine are configured to process a same frame of the video data [Same citations above], wherein the VSP engine is configured to start processing the same frame of the video data before the VPP engine [Please refer to the processing flowchart and timing chart shown in figs. 13 and 14, respectively, which show the variable length encoding/decoding processing starting before the first to fourth image processing. For additional support, please refer to Watanabe below] wherein the VSP engine is configured to send an interrupt to the controller when finished processing the same frame of the video data [See processing operations shown in fig. 13. An end instruction is given following the decompression process], and wherein the controller is configured to power off the VSP engine based on the interrupt.” [If the end instruction is given (Y), the variable length encoding/decoding processing unit controller goes into an idle state (fig. 13). Also please note fig. 15B with reference to ¶0079-¶0082, where power is not unnecessarily supplied to those units not in the operation state] Although Saito’s teachings are deemed relevant given the BRI of the aforementioned features, the work of Watanabe from the same or similar field of endeavor is also relied on to further teach and/or suggest “wherein the VSP engine is configured to start processing the same frame of the video data before the VPP engine” [See for e.g. the timing chart in fig. 17 (e.g. ¶0125-¶0130) where variable-length decoding operations begin before image decoding. Watanabe also describes deactivating some of the processing units which can help reduce power consumption (¶0135)] Recognizing the teachings of Watanabe above, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the operations of Watanabe’s parallel arrangement of a MPEG decoder (fig. 9), with the power control circuitry of Saito (e.g. fig. 1) for reducing power consumption of processing units not in an operation state, which can help reduce power consumption by deactivating some of the processing units (see for e.g. ¶0135 of Watanabe).
Regarding claim 12, claim 12 is rejected under the same art and evidentiary limitations as determined for the apparatus of Claim 2.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Saito, in further view of NPL Leibson S. “Anatomy of a hardware video codec” dated 05/11/2007, hereinafter referred to as Leibson.
Regarding Claim 10, (Original): Saito teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Although Saito’s teachings do not explicitly refer to “wherein the apparatus is a mobile communications device.” it would be within the level of skill in the art to have an image compression/decompression device as taught by Saito, in the form of a mobile communication device. Nonetheless and in the spirit of compact prosecution, the work of Leibson from the same or similar field of endeavor is relied on to teach and/or suggest “wherein the apparatus is a mobile communications device.” [Regarding Leibson’s hardware video codec, See fig. 3 for the Diamond Video Engine which is disclosed as being in volume production inside of mobile-phone SOCs (pg. 9 just below fig. 6)] Given Leibson’s teachings above of a hardware video codec, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the image compression/decompression device of Saito with the hardware video Codec of Leibson to help exploit the parallelism inherent in video compression and video decompression algorithms; as such, power distribution can be minimized and clock rates kept low when decoding standard-definition video (e.g. pgs. 5-6).
Allowable Subject Matter
8. Claims 4 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In light of the specification, the Examiner finds the claimed invention to be patentably distinct from the prior art of records. The prior art of record, taken individually or in combination fail to explicitly teach or render obvious within the context of the respective independent claims the limitations:
4. The apparatus of claim 3, wherein to power on the VSP engine at the time after the VPP engine has started processing the same frame of the video data based on the relative processing speed of the VSP engine and the VPP engine, the controller is configured to: power on the VSP engine at the time after the VPP engine has started processing the same frame of the video data based on an equation: t1 = t0 + α(C1-C0), where t1 is the time to power on the VSP engine, t0 is a time the VPP engine has started processing the same frame of video data, α is a control parameter between 0 and 1, inclusive, C0 is a completion time of the VSP engine, and C1 is a completion time of the VPP engine.
14. The method of claim 13, wherein powering on, by the controller, the VSP engine at the time after the VPP engine has started processing the same frame of the video data based on the relative processing speed of the VSP engine and the VPP engine comprises: powering on, by the controller the VSP engine at the time after the VPP engine has started processing the same frame of the video data based on an equation: t1 = t0 + α (C1-C0), where t1 is the time to power on the VSP engine, t0 is a time the VPP engine has started processing the same frame of video data, α is a control parameter between 0 and 1, inclusive, C0 is a completion time of the VSP engine, and C1 is a completion time of the VPP engine.
Conclusion
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on 02/02/2026 prompted the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A HANSELL JR. whose telephone number is (571)270-0615. The examiner can normally be reached Mon - Fri 10 am- 7 pm.
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/RICHARD A HANSELL JR./Primary Examiner, Art Unit 2486
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