DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed July 15, 2024 has been considered by the Examiner.
Claim Objections
3. The numbering of claims is not in accordance with 37 CFR 1.126 which requires the original numbering of the claims to be preserved throughout the prosecution. When claims are canceled, the remaining claims must not be renumbered. When new claims are presented, they must be numbered consecutively beginning with the number next following the highest numbered claims previously presented (whether entered or not).
Misnumbered claims 1 (second occurrence) -19 have been renumbered to 2-20.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9-12 and 14-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Morgan et al (US 9,930,772; hereinafter Morgan).
Regarding claim 1, Morgan discloses a printed circuit board (500) of an information handling system, the printed circuit board (500) comprising: a first differential pair (520A) fabricated on the printed circuit board (500), the first differential pair (520A) includes: a first via (512) connected to a first signal trace (514) on the printed circuit board (500; see figure 7); and a second via (512) connected to a second trace (514) on the printed circuit board (500; see figure 7); and a second differential pair (520B) fabricated on the printed circuit board (500; see figure 7), the second differential pair (520B) includes: a third via (512) connected to a third signal trace (514) on the printed circuit board (500; see figure 7); a fourth via (512) connected to a fourth trace (514) on the printed circuit board (500; see figure 7), wherein the third and fourth vias have an orthogonal via pattern (see figure 7); and a shield (506) located between the first via and the third and fourth vias (see figure 7).
Regarding claim 2, Morgan discloses the printed circuit board (500), wherein the third and fourth vias (512; see figure 7; part of 520B) and the shield (506) form a shielded vertical conductive structure (see figure 7 or figure 1; notice the ground shield 118).
Regarding claim 3, Morgan discloses the printed circuit board (500), wherein a crosstalk from the third and fourth vias is symmetrical with respect to the first via (column 11 lines 49-52 or column 4 lines 10-21).
Regarding claim 4, Morgan discloses the printed circuit board (500), further comprises: a third differential pair (520C; see figure 7) fabricated on the printed circuit board (500), the third differential pair (520C) includes: a fifth via (512) connected to a fifth signal trace (514) on the printed circuit board (see figure 7); a sixth via (512) connected to a sixth trace (514) on the printed circuit board (500), wherein the fifth and sixth vias have an orthogonal via pattern (see figure 7); and a second shield (506) located between the second via and the fifth and sixth vias (see figure 7).
Regarding claim 5, Morgan discloses the printed circuit board (500), wherein the fifth and sixth vias (see figure 7; part of 520c) and the second shield (506) form a shielded vertical conductive structure (see figure 7 or see figure 1; notice ground shield 118).
Regarding claim 6, Morgan discloses the printed circuit board, wherein the second shield (506) provides common noise rejection between the third differential pair and the first differential pair (column 11 lines 49-52 or column 4 lines 10-21; “balance the impedance”).
Regarding claim 7, Morgan discloses the printed circuit board, wherein a crosstalk from the fifth and sixth vias (see figure 7; part of 520C) is symmetrical with respect to the second via (see figure 7; part of 520A).
Regarding claim 9, Morgan discloses the printed circuit board (500) wherein a third layout of the third differential pair (520C) has a same width as the second layout of the second differential pair (520B; see figure 7).
Regarding claim 10, Morgan discloses the printed circuit board (500), wherein the shield (506) provides common noise rejection between the second differential pair and the first differential pair (column 11 lines 49-52 or column 4 lines 10-21).
Regarding claim 11, Morgan disclose an information handling system (see figure 7) comprising: a printed circuit board (500) including: a first differential pair (520A) fabricated on the printed circuit board (see figure 7), the first differential pair (520A) includes: a first via (512) connected to a first signal trace (514) on the printed circuit board (500); and a second via (512) connected to a second trace (514) on the printed circuit board (see figure 7); a first shielded vertical conductive slot (506), the first shielded vertical conductive slot (506) includes: a third via (512) connected to a third signal trace (514) of a second differential pair (520B) on the printed circuit board (500); a fourth via (512) connected to a fourth trace (514) of the second differential pair (520B) on the printed circuit board (500), wherein the third and fourth vias have an orthogonal via pattern (see figure 7); and a first shield (506) located between the first via and the third and fourth vias (see figure 7); and a second shielded vertical conductive slot (see figure 7), the second shielded vertical conductive slot (506) includes: a fifth via connected to a fifth signal trace of a third differential pair (520C) on the printed circuit board (500); a sixth via connected to a sixth trace of the third differential pair on the printed circuit board (500), wherein the fifth and sixth vias have an orthogonal via pattern (see figure 7); and a second shield (506) located between the second via and the fifth and sixth vias (see figure 7)
Regarding claim 12, Morgan discloses the information handling system (see figure 7), wherein a crosstalk from the third and fourth vias is symmetrical with respect to the first via (see figure 7; column 11 lines 49-52 or column 4 lines 10-21).
Regarding claim 14, Morgan discloses the information handling system (see figure 7), wherein a third layout of the third differential pair (520C) has a same width as the second layout of the second differential pair (520B).
Regarding claim 15, Morgan discloses the information handling system (see figure 7), wherein a crosstalk from the fifth and sixth vias is symmetrical with respect to the second via (see figure 7; column 11 lines 49-52 or column 4 lines 10-21) .
Regarding claim 16, Morgan discloses the information handling system (see figure 7), wherein the first shield (506) provides common noise rejection between the second differential pair and the first differential pair (see figure 7; column 11 lines 49-52 or column 4 lines 10-21; “balance the impedance”).
Regarding claim 17, Morgan discloses the information handling system (see figure 7), wherein the second shield provides common noise rejection between the third differential pair and the first differential pair (see figure 7; column 11 lines 49-52 or column 4 lines 10-21; “balance the impedance”).
Regarding claim 18, Morgan discloses a method (see figure 7) comprising: fabricating first and second vias in a printed circuit board (500) of an information handling system; plating the first via (512) with a first conductive material (column 8 lines 1-20); plating the second via (512) with a second conductive material (column 8 lines 1-20); routing a first trace (514) of a first differential pair (520A) to the first conductive material of the first via (see figure 7); routing a second trace (514) of the first differential pair (520A) to the second conductive material of the second via (see figure 7); fabricating a shielded vertical conductive structure (506) in the printed circuit board (500) of the information handling system, wherein the shielded vertical conductive structure (506) includes: third and fourth vias (512) and a shield (506); plating the third via with a third conductive material; plating the fourth via with a fourth conductive material (see figure 7); plating the shield (506) with a fifth conductive material; routing a third trace (514) of a second differential pair (520B) to the third conductive material of the third via (see figure 7); and routing a second trace (514) of the second differential pair (520B) to the fourth conductive material of the fourth via (see figure 7).
Regarding claim 19, Morgan discloses the method (see figure 7), wherein the third and fourth vias have an orthogonal via pattern (see figure 7).
Regarding claim 20, Morgan discloses the method (see figure 7), wherein the shield (506) is located between the first via and the third and fourth vias (see figure 7).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Morgan et al (US 9,930,772; hereinafter Morgan).
Regarding claim 8, Morgan discloses the claimed invention except for a first layout of the first differential pair is wider than a second layout of the second differential pair. It would have been an obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the first layout of the first differential pair wider than a second layout of the second differential pair to reduce space and improve signaling. Furthermore, it has been held that such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Also, Morgan states in column 13 lines 43-48 “Dimensions, types of materials, orientations of the various components, and the number and positions of the various components described herein are intended to define parameters of certain embodiments, and are by no means limiting and are merely exemplary embodiments”.
Regarding claim 13, Morgan discloses the claimed invention except for a first layout of the first differential pair is wider than a second layout of the second differential pair. It would have been an obvious to one of ordinary skill in the art before the effecting filing date of the claimed invention to make the first layout of the first differential pair wider than a second layout of the second differential pair to reduce space and improve signaling. Furthermore, it has been held that such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Also, Morgan states in column 13 lines 43-48 “Dimensions, types of materials, orientations of the various components, and the number and positions of the various components described herein are intended to define parameters of certain embodiments, and are by no means limiting and are merely exemplary embodiments”.
Conclusion
6. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Smith et al (US 12,114,419), Pritchard et al (US 11,758,644), Sinha et al (US 11,160,163), Chengson et al (US 10,231,325), Aizawa et al (US 9,923,309), Rose et al (US 9,560,741), Kim et al (US 8,885,357), Jeon (US 8,715,006), Bopp et al (US 8,568,177), Goergen et al (US 8,119,921) and Nakamura (US 7,317,166) disclose a printed circuit board.
7. Any inquiry concerning this communication should be directed to Angel R. Estrada at telephone number (571) 272-1973. The Examiner can normally be reached on Monday-Friday (8:30am -5:00pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Imani N. Hayman can be reached on (571) 270-5528. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) OR 571-272-1000.
July 28, 2026
/ANGEL R ESTRADA/Primary Examiner, Art Unit 2841
