Prosecution Insights
Last updated: April 19, 2026
Application No. 18/773,168

BIDIRECTIONAL RF CIRCUIT AND METHOD OF USE

Non-Final OA §103§DP
Filed
Jul 15, 2024
Examiner
TRA, ANH QUAN
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Reach Power Inc.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
78%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allow Rate
807 granted / 1110 resolved
+4.7% vs TC avg
Moderate +5% lift
Without
With
+5.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
38 currently pending
Career history
1148
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
57.6%
+17.6% vs TC avg
§102
24.9%
-15.1% vs TC avg
§112
7.8%
-32.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1110 resolved cases

Office Action

§103 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11722125 and claims 1-20 of U.S. Patent No. 12068749. Although the claims at issue are not identical, they are not patentably distinct from each other because the patents’ claims and application’s claims recite similar limitations. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. (US 20190245587) in view of Shin et al. (US 20200021254). As to claim 1, Chu et al.’s figure 4 or 5 shows a bidirectional circuit system comprising: an RF power terminal (21); a DC terminal electrically coupled to the RF power terminal (VDD); and an RF signal input terminal (22); wherein the system is operable between: an amplifier mode, in which the circuit is configured to: receive an RF input signal (transmit signal) at the RF signal input terminal, receive a DC power input at the DC terminal, generate an amplified signal (first output signal) based on the RF signal input, and provide the amplified signal at the RF power terminal. The figure fails to show a rectifier circuit. However, Shin et al.’s figure 2 shows a similar device that comprising clamping circuit 160 coupled to node 110-3 or clamping circuit 40 coupled to node 20 in order to limit the amplitude of signals at nodes 110 or 20. Therefore, it would have been obvious to one having ordinary skill in the art to add clamping diode to node 23 for the purpose of limiting the amplitude of signal at node 23. Therefore, the modified Chu et al.’s figure further shows a rectifier mode, in which the circuit is configured to: receive an RF power input (receive signal) at the RF power terminal, rectify (by the added clamping circuit) the RF power input to generate a DC power output, and provide the DC power output at the DC terminal (since the added clamping circuit is also coupled to VDD). Claim(s) 2 and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. (US 20190245587) in view of Shin et al. (US 20200021254) and Labadie et al. (US 11043985). As to claim 2, the modified Chu et al.’s figure fails to show that switches are coupled to the inputs and outputs the circuit. However, Labadie et al.’s figure 3 shows a bidirectional amplifier circuit comprising switches (308 and 310) coupled to the inputs and outputs of amplifier circuit (between 308 and 310) for selectively switch operation mode. Therefore, it would have been obvious to one having ordinary skill in the art to add switches coupled to the inputs and outputs of Chu et al.’s amplifier for the purpose of selectively switching its operation mode, thereby reducing interference. Thus, the modified Chu et al.’s figure shows a mode control element (not shown circuit that controls the added switches orfurther includes the switches) electrically coupled between the RF signal input terminal, the RF power terminal, and the DC terminal, wherein the mode control element is operable to switch the system between operation in the amplifier mode and operation in the rectifier mode. As to claim 14, the modified Chu et al.’s figure shows that the system is operable to: operate in the amplifier mode during an amplification time period; operate in the rectifier mode during a rectification time period after the amplification time period; and between the amplification time period and the rectification time period, switch operation from the amplifier mode to the rectifier mode. As to claim 15, the modified Chu et al.’s figure shows that the system is further operable to, after the rectification time period, switch operation from the rectifier mode to the amplifier mode. As to claim 16, the modified Chu et al.’s figure 5 shows a bidirectional circuit system comprising: a transistor (M1. Shin et al.’s figure 4 shows transistor 113-5 is used for used as a switch in amplifier circuit. Therefore, it would have been obvious to one having ordinary skill in the art to use transistor for Chu et al.’s M1 for the purpose of saving space) comprising: a switching terminal (G), a first switched terminal (D), and a second switched terminal (S); an RF power terminal (node between L and C in Chu et al.’s 24) electrically coupled to the first switched terminal; a DC terminal (at VDD) electrically coupled, via a low-pass filter (3, C3 and L1), to the RF power terminal and the first switched terminal; an RF signal input terminal (input of the added switch that is coupled to terminal 22 for switching mode); and a mode control element (the added switches) comprising a first (output of the added switch) and second terminal (input of the added switch), the first terminal electrically coupled to the switching terminal, the second terminal electrically coupled to the RF signal input terminal, wherein the mode control element comprises a switch operable between: a first configuration, in which the switch electrically connects the first terminal to the second terminal; and a second configuration, in which the switch does not electrically connect the first terminal to the second terminal. Allowable Subject Matter Claims 3-13 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH-QUAN TRA whose telephone number is (571)272-1755. The examiner can normally be reached Mon-Fri from 8:00 A.M.-5:00 P.M. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached at 571-272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /QUAN TRA/ Primary Examiner Art Unit 2842
Read full office action

Prosecution Timeline

Jul 15, 2024
Application Filed
Feb 06, 2026
Non-Final Rejection — §103, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
78%
With Interview (+5.3%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 1110 resolved cases by this examiner. Grant probability derived from career allow rate.

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