DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The amendment filed March 16, 2026 has been entered. Claims 2-21 remain pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-4, 8-11, 13-17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hoshikawa et al. (US 2016/0070507, as presented in applicant’s IDS) in view of Subbarao et al. (US 2020/0393994, as presented in applicant’s IDS), Jayaraman et al. (US 2016/0162215), Mishra et al. (US 2021/0303185, as presented in applicant’s IDS), and Byun (US 2020/0387447, as presented in applicant’s IDS).
Regarding claim 2, Hoshikawa teaches a memory system (Fig. 1, memory system 100), comprising:
a memory device comprising a plurality of resource groups (Fig. 1, memory system 100 contains planes #P1-#P4, including memory arrays MA1-MA4, see also [0023]); and
processing circuitry coupled with the plurality of memory devices (Fig, 1, controller 20) and configured to cause the memory system to:
configure a first resource group of the plurality of resource groups for single-level programming and a second resource group of the plurality of resource groups for multi-level programming (in a third embodiment, Hoshikawa discloses where an MLC/SLC mode is set for each plane, see “when the parallel read and the parallel write are performed among the plurality of planes, the SLC/MLC mode is designated in units of planes…. When a parallel access is performed, a command issuing circuit 21 of the controller 20 issues an SLC/MLC command, which indicates which one of the SLC and MLC modes is used for each plane, to the NAND 10. Thereafter, the command issuing circuit 21 of the controller 20 issues a read command or a write command to the NAND 20,” [0056]; in the example of Fig. 12, planes #P1-#P3 are configured as MLC, reading upon the second resource group configured for multi-level programming and plane #P4 is configured as SLC, reading upon the first resource group configured for single-level programming);
write, in accordance with a single-level programming operation, a first set of data to a first virtual block that spans the first resource group (“Thereafter, the command issuing circuit 21 of the controller 20 issues a read command or a write command to the NAND 20,” [0056], where in the example of Fig. 12, a single plane #P4 is shown to be in SLC mode; Hoshikawa earlier disclosed how multiplane commands are performed based on page addresses, see [0033], where each plane contains blocks containing pages, see [0023], using logical to physical mapping tables, see [0028]; therefore, writing data to #P4 as the only plane in SLC mode means writing to the one logical block in the only plane in SLC mode, i.e. the logical block in #P4 spans #P4, reading upon the limitation).
Hoshikawa fails to teach where the memory system comprises a plurality of memory devices, each comprising a plurality of resource groups (as cited and seen above, Hoshikawa only shows one system with multiple planes and memory arrays, but does not clearly distinguish each plane as a separate device), as well as where the write operation is performed during a duration in accordance with a plurality of sequential single-level programming operations, wherein the memory system executes in an active state during the duration.
Hoshikawa also fails to teach the processing circuitry configured to cause the memory system to
transfer during the duration and in accordance with a single multi-level programming operation, a second set of data from the first resource group or the second resource group to a second virtual block that spans the second resource group in accordance with the first resource group being configured for the single-level programming and the second resource group being configured for the multi-level programming, wherein the plurality of sequential single-level programming operations are performed concurrently with the single multi-level programming operation during the duration in accordance with the memory system executing in the active state during the duration.
Subbarao’s disclosure relates to managing a memory system and as such comprises analogous art in the same field of endeavor.
As part of this disclosure, Subbarao depicts a memory sub-system, see Fig. 1, where one memory sub-system controller is able to manage multiple memory devices, see devices 102 and 104. Each of the memory devices is disclosed to include different arrays of memory cells, including SLC/MLC embodiments, see [0026], where a dynamic data placer is able to place data into the memory devices, also called media units, see [0034] and Fig. 2. Subbarao then goes on to depict how each of the media units contains multiple dies/planes, see Fig. 3.
An obvious modification can be identified: incorporating Subbarao’s disclosure of multiple memory devices, each with multiple dies and planes, into Hoshikawa’s disclosure. Such a modification reads upon the limitation where the memory system comprises a plurality of memory devices, each including a plurality of resource groups.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Subbarao’s disclosure of multiple memory devices into Hoshikawa’s system, as having multiple memory devices expands the capacity that Hoshikawa’s system is able to manage as well as expanding the processing throughput while the controller is still able to manage placement and routing of the data via the dynamic data placer.
The combination of Hoshikawa and Subbarao still fails to teach the transfer limitation and the duration/plurality of sequential single-level operations. Examiner notes that while Subbarao’s disclosure relates to parallel operations to different memory devices, see [0014], all the operations described are writing operations, with no disclosure of anything approaching a transfer operation.
Jayaraman’s disclosure relates to providing operations to a storage device, and as such comprises analogous art.
As part of this disclosure, Jayaraman describes different kind of operations, including folding and wear leveling/garbage collection, where “During a folding operation, an internal transfer may occur at the memory 104 where data stored at SLC pages is read and stored at one or more MLC pages. During a wear-leveling operation and/or a garbage collection operation, data may be transferred within the memory 104 for purposes of equalizing wear of different regions of the memory 104 and/or for gathering defragmented data into one or more consolidated regions of the memory 104,” [0032]. Jayaraman also discloses that folding operations can be scheduled to perform concurrently with SLC writes if a power consumed does not exceed a peak power constraint, see [0040,0041] for more generally scheduling a second memory operation including compaction operations in parallel with a first memory operation including writes. More specifically, Jayaraman discloses that “In some implementations, the first memory operation 162 may include a first set of one or more memory operations to be executed at the first meta plane 130, such as a set of write operations to write data to the erased meta block… The controller 120 may determine one or more idle time periods associated with the second set of dies (associated with the second meta plane 166) during the particular time period. A power consumption during each of the one or more idle time periods may be less than a threshold amount of power. The controller 120 may identify a candidate operation (e.g., a second memory operation 164) to be performed during at least one idle time period of the one or more idle time periods. The controller 120 may identify a candidate operation (e.g., a second memory operation 164) to be performed during at least one idle time period of the one or more idle time periods. The second memory operation 164 may be … a folding operation,” [0040,0041], teaching a set of write operations with a second single folding operation, see also “The controller 120 may access the second memory operation parameters 184 to determine a peak power of the second memory operation 164 and may predict whether concurrent execution of the second memory operation 164 and the first memory operation 162 during the at least one idle time period would result in a peak power of the memory 104 to exceed a peak power threshold. If execution of the second memory operation 164 and the first memory operations 164 is determined to be less than or equal to the peak power threshold, the controller 120 may schedule the second memory operation 164 to begin at a second die of the second set of dies during the at least one idle time period (e.g., during the execution time period of the first memory operation 162),” [0042] teaching that the first memory operation and second memory operation are performed concurrently during the idle time period, where the idle time period is identified with respect to the second set of dies associated with the second meta plane 166, see [0041], while the first memory operation is identified with respect to the first set of dies associated with the first meta plane 130, see [0040]. To clarify, Jayaraman discloses the ability to track idleness at a per die level based on a die’s activity, see [0037] where die0 141 is in an idle state while die5 146 is in an active state while executing a second memory operation, see also example in [0054] where while SLC operations are performed at memory dies 141-144, then those dies are active, while other dies 145-148 that are not active because they do not have currently scheduled SLC write operations are identified as idle. Therefore, with respect to identification of idle times in [0040,0041], then Jayaraman is identifying whether the second set of dies does not currently have memory operations scheduled, and the power constraint provides that concurrent execution would not exceed the power threshold, so Jayaraman can schedule the second operations to be performed with the actively scheduled first memory operations. In other words, the memory system is still active overall, not idle overall.
Jayaraman goes through a number of implementations of the first and second memory operations, including one where “the first memory operation 162 (e.g., a first set of operations) may include a set of SLC write operations and the second memory operation 164 may include a MLC write operation, such as a folding operation,” [0044]. Further, while not relied upon for the folding operations, with respect to a set of SLC write operations, Figs. 2 and 3 show that SLC writes can be written in a sequential series of programming operations.
An obvious modification can be identified: incorporating Jayaraman’s disclosure of folding and wear leveling/garbage collection operations, and in particular that memory operations can be scheduled in parallel during an idle period with respect to the second dies, while the memory system overall is active, such as a set of SLC write operations and an MLC folding operation. Such a modification reads upon providing a plurality of single-level programming operations (Jayaraman discloses a set of SLC writes), and the transfer operation (folding transfers data from the first resource group to the second group according to multi-level programming operation, and garbage collection of MLC cells would mean transferring data from the second resource group to the second group according to multi-level programming operations), as well as where this occurs at concurrently with the plurality of single-level programming operations (the folding operations are disclosed to occur concurrent to the SLC writes) during a same duration (Jayaraman identifies in [0042] that an idle time period in dies to perform the second memory operation concurrent with the execution of the first memory operation).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Jayaraman’s disclosure of providing folding and compaction operations generally, and more specifically incorporating memory operations like folding and compaction operations concurrent to writes into Hoshikawa’s system, as folding operations can improve storage density for data and compaction operations improve the block usage and lifetime by periodically moving valid data and erasing blocks, and providing concurrent memory operations allows for an increased data rate of the memory system.
The combination of Hoshikawa, Subbarao, and Jayaraman still fails to teach where the transfer operation is directed to a second virtual block that spans the second set of planes (given the example of Hoshikawa Fig. 12, the pages within each plane are understood to be considered separate blocks, and Jayaraman is silent on logical/virtual blocks, let alone which planes they span; Subbarao does disclose zones containing multiple blocks, based on logical block addresses, see Fig. 4 and [0049-0061]; however, the main disclosure of Subbarao focuses on a multi-pass operation, where while the operation can be directed to pages across different planes/dies, see Figs. 6 and 7, the logical pages/blocks themselves do not span different planes; Subbarao also discloses multi-plane pages in [0075], which suggests logical structures that can span multiple planes, but this is the only recitation with no defined terms, so there is not enough detail in the disclosure to render the feature obvious).
Mishra’s disclosure is related to logical organization of storage memory planes, and as such comprises analogous art as directed to the same field of endeavor.
As part of this disclosure, Mishra discloses a memory array (Fig. 3, array 300) comprising multiple dies, which are divided into planes, see [0132], and in particular shows multiple LEB’s, called logical erase blocks, where a logical erase block is defined as “a set of logical pages that span planes, memory die, and/or chips”, [0058].
An obvious modification can be identified: incorporating Mishra’s logical organization to provide plane-spanning blocks to Hoshikawa’s system. Such a modification reads upon the second logical block spanning planes.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Mishra’s logical grouping of pages that span planes into a logical block into Hoshikawa’s system, as the plane-spanning blocks provide a level of redundancy and backup by ensuring that some data will survive in case a plane/die suffers data loss.
The combination of Hoshikawa, Subbarao, Jayaraman, and Mishra fails to teach where the second virtual block spans the second set of planes (as seen in Fig. 3, Mishra’s logical erase blocks span all planes present, with no disclosure present to narrow the spanning to the claimed second resource group, where Hoshikawa shows the second resource group as three out of the four planes present).
Byun’s disclosure relates to organizing memory blocks, and as such comprises analogous art.
As part of this disclosure, Byun shows a memory device (Fig. 2, device 150) comprising multiple planes (planes 00, 01, 10, 11), with blocks inside. Notably, Byun depicts multiple super blocks comprising a different number of blocks (see super block A1 containing a block from plane 00 and 01, A2 containing a block from planes 10 and 11, super block C containing a block from all planes, B1 containing a block from plane 00 and 10, and B2 containing a block from plane 01 and 11).
An obvious modification can be identified: incorporating Byun’s ability to group blocks from different planes in various configurations into Hoshikawa’s system as modified by Mishra. Such a modification reads upon the limitation where the second virtual block spans the second resource group, as Byun provides the ability to alter how many blocks/planes make up a given super block/logical block.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Byun’s flexible block/plane configuration, as this allows for suitable die/plane configurations based on design considerations, see [0051,0053], allowing for a more versatile system.
Regarding claim 3, the combination of Hoshikawa, Subbarao, Jayaraman, Mishra, and Byun teaches the memory system of claim 2, and Hoshikawa teaches wherein the processing circuitry is further configured to cause the memory system to:
receive, from a host device, a third set of data (“The controller 20 performs process corresponding to various types of commands according to the commands received from the host 1. The command process includes a process of reading data from the NAND 10, a process of writing data in the NAND 10, and the like,” [0030]); and
write, in accordance with a second single-level programming operation and before the first resource group is configured for the single-level programming and the second resource group is configured for the multi-level programming, the third set of data to a third virtual block that spans the plurality of resource groups (“Thereafter, the command issuing circuit 21 of the controller 20 issues a read command or a write command to the NAND 20,” [0056]; “On the other hand, when receiving the SLC/MLC command, a command decoder 15 included in the peripheral circuits in the NAND 10 decodes the SLC/MLC command, and instructs each of the planes #P1 to #P4 to operate in any one of the SLC and MLC modes based on the decoding result. Then, the command decoder decodes the read command or the write command thus received, and outputs the decoding result to each of the planes #P1 to #P4,” [0057]; Hoshikawa teaches that a SLC/MLC command can designate any plane in any one of the SLC/MLC modes; therefore, one command can operate all planes in a SLC mode, with the claim 2 rationale from Mishra and Byun showing the ability to designate a logical erase block/super block spanning the plurality of planes).
Regarding claim 4, the combination of Hoshikawa, Subbarao, Jayaraman, Mishra, and Byun teaches the memory system of claim 3, wherein the processing circuitry is further configured to cause the memory system to:
write, in accordance with a second multi-level programming operation and before the first resource group is configured for the single-level programming and the second resource group is configured for the multi-level programming, a fourth set of data to a fourth virtual block that spans the plurality of resource groups (“Thereafter, the command issuing circuit 21 of the controller 20 issues a read command or a write command to the NAND 20,” [0056]; “On the other hand, when receiving the SLC/MLC command, a command decoder 15 included in the peripheral circuits in the NAND 10 decodes the SLC/MLC command, and instructs each of the planes #P1 to #P4 to operate in any one of the SLC and MLC modes based on the decoding result. Then, the command decoder decodes the read command or the write command thus received, and outputs the decoding result to each of the planes #P1 to #P4,” [0057]; Hoshikawa teaches that a SLC/MLC command can designate any plane in any one of the SLC/MLC modes; therefore, one command can operate all planes in a MLC mode, with the claim 1 rationale from Mishra and Byun showing the ability to designate a logical erase block/super block spanning the plurality of planes).
Regarding claim 8, the combination of Hoshikawa, Subbarao, Jayaraman, Mishra, and Byun teaches the memory system of claim 2, and further teaches wherein:
the first resource group is configured for the single-level programming for a first duration;
the second resource group is configured for the single-level programming for the first duration;
the write of the first set of data to the first virtual block occurs during the first duration; and
the transfer of the second set of data to the second virtual block occurs during the first duration.
Following the claim 2 rationale, Hoshikawa provides that the configuration of planes occurs in response to a plane configuration decoding for commands, see [0056], reading upon the configuration of the resource groups and writing of the data for a first duration; further, Hoshikawa discloses “On the other hand, when receiving the SLC/MLC command, a command decoder 15 included in the peripheral circuits in the NAND 10 decodes the SLC/MLC command, and instructs each of the planes #P1 to #P4 to operate in any one of the SLC and MLC modes based on the decoding result” [0057], teaching that a SLC/MLC command can designate any plane in any one of the SLC/MLC modes. While not explicitly disclosed, Hoshikawa’s system with 4 planes necessarily only has 5 configuration options, 0 planes in SLC mode up through 4 planes in SLC mode, meaning one of the potential SLC/MLC commands that are taught is 4 SLC plane configuration, reading upon the second resource group also being configured in single-level programming. Jayaraman [0040,0041,0055,0056] was relied upon to provide for a concurrent folding operation, i.e. the transfer of the second set of data occurs during the same first duration as the write of the first set of data, reading upon the limitation of the claim.
Regarding claim 9, the combination of Hoshikawa, Subbarao, Jayaraman, Mishra, and Byun teaches the memory system of claim 2, and Hoshikawa teaches wherein the processing circuitry is further configured to cause the memory system to:
configure, after the transfer of the second set of data to the second virtual block, the second resource group for the single-level programming and the first resource group for the multi-level programming for at least a second duration (“Thereafter, the command issuing circuit 21 of the controller 20 issues a read command or a write command to the NAND 20,” [0056]; “On the other hand, when receiving the SLC/MLC command, a command decoder 15 included in the peripheral circuits in the NAND 10 decodes the SLC/MLC command, and instructs each of the planes #P1 to #P4 to operate in any one of the SLC and MLC modes based on the decoding result. Then, the command decoder decodes the read command or the write command thus received, and outputs the decoding result to each of the planes #P1 to #P4,” [0057]; Hoshikawa teaches that a SLC/MLC command can designate any plane in any one of the SLC/MLC modes; therefore, one command can operate the planes in a reverse of the situation of the claim 2 rationale/Fig. 12, where instead of planes #P1-P3 in MLC and #P4 in SLC, planes #P1-P3 are in SLC and #P4 in MLC, reading upon the limitation of the claim; regarding the timing, as Hoshikawa provides for this to occur whenever a parallel access is provided, this can be a parallel access after the one in the Fig. 12 example).
Regarding claim 10, the combination of Hoshikawa, Subbarao, Jayaraman, Mishra, and Byun teaches the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
configure, after the transfer of the second set of data to the second virtual block, a third resource group of the plurality of resource groups for the single-level programming and a fourth resource group of the plurality of resource groups for the multi-level programming for at least a second duration (“Thereafter, the command issuing circuit 21 of the controller 20 issues a read command or a write command to the NAND 20,” [0056]; “On the other hand, when receiving the SLC/MLC command, a command decoder 15 included in the peripheral circuits in the NAND 10 decodes the SLC/MLC command, and instructs each of the planes #P1 to #P4 to operate in any one of the SLC and MLC modes based on the decoding result. Then, the command decoder decodes the read command or the write command thus received, and outputs the decoding result to each of the planes #P1 to #P4,” [0057]; Hoshikawa teaches that a SLC/MLC command can designate any plane in any one of the SLC/MLC modes; Subbarao’s disclosure in the claim 2 rationale also provided for where each memory device has planes, see Figs. 1 and 3, so then an SLC/MLC command from Hoshikawa can occur within each respective memory device, i.e. one memory device can have the first and second resource group, while another memory device has the third and fourth resource groups, reading upon the limitation of the claim; regarding the timing, as Hoshikawa provides for this to occur whenever a parallel access is provided, this can be a parallel access after the one in the Fig. 12 example relied upon in claim 2).
Regarding claim 11, the combination of Hoshikawa, Subbarao, Jayaraman, Mishra, and Byun teaches the memory system of claim 10, wherein:
the first resource group is configured for the single-level programming for a first duration;
the second resource group is configured for the single-level programming for the first duration;
the third resource group is configured for the single-level programming for the second duration that is after the first duration; and
the fourth resource group is configured for the multi-level programming for the second duration that is after the first duration.
Following the claims 2 and 10 rationales, Hoshikawa provides that the configuration of planes occurs in response to a plane configuration decoding for commands, see [0056], reading upon the configuration of the first and second resource groups for a first duration; further, Hoshikawa discloses “On the other hand, when receiving the SLC/MLC command, a command decoder 15 included in the peripheral circuits in the NAND 10 decodes the SLC/MLC command, and instructs each of the planes #P1 to #P4 to operate in any one of the SLC and MLC modes based on the decoding result” [0057], teaching that a SLC/MLC command can designate any plane in any one of the SLC/MLC modes. While not explicitly disclosed, Hoshikawa’s system with 4 planes necessarily only has 5 configuration options, 0 planes in SLC mode up through 4 planes in SLC mode, meaning one of the potential SLC/MLC commands that are taught is 4 SLC plane configuration, reading upon the second resource group also being configured in single-level programming. Subbarao Figs. 1 and 3 provided for separate devices with separate plane groupings, allowing for the third and fourth resource groups to be configured, with Hoshikawa’s disclosure providing for a per-command basis of configuring the planes, allowing for a future configuration of a different memory device, reading upon the configuration of the third and fourth resource groups after the first duration.
Regarding claim 13, the combination of Hoshikawa, Subbarao, Jayaraman, Mishra, and Byun teaches the memory system of claim 2, but Hoshikawa, Subbarao, Jayaraman, and Mishra fail to teach the memory system further comprising:
a plurality of channels coupled with the plurality of resource groups and the processing circuitry, wherein each channel of the plurality of channels is coupled with a respective resource group of the plurality of resource groups.
As part of Byun’s disclosure, Byun provides for two channels to input/output data to the memory device, see Fig. 2 channels 0 and 1.
An obvious modification can be identified: incorporating Byun’s multiple channels into Hoshikawa’s system. Such a modification reads upon the limitation of the claim, as Byun shows each channel coupled with a resource group in the plurality of resource groups (channel 0 coupled to planes 00 and 01 and channel 1 coupled to planes 10 and 11).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Byun’s multichannel system, as this allows for a channel interleaving scheme to aid with a simultaneous/parallel access to memory blocks within super memory blocks, see [0057].
Regarding claim 14, the combination of Hoshikawa, Subbarao, Jayaraman, Mishra, and Byun teaches the memory system of claim 2, but Hoshikawa, Subbarao, Jayaraman, and Mishra fail to teach the memory system further comprising:
a plurality of channels coupled with the plurality of resource groups and the processing circuitry, wherein each channel of the plurality of channels is coupled with a at least two resource groups of the plurality of resource groups
As part of Byun’s disclosure, Byun provides for two channels to input/output data to the memory device, see Fig. 2 channels 0 and 1.
An obvious modification can be identified: incorporating Byun’s multiple channels into Hoshikawa’s system. The Byun Fig. 2 example shows channel 0 coupled to planes 00 and 01 and channel 1 coupled to planes 10 and 11. Recalling from the claim 2 rationale, two examples of a super memory block is B1, with block 002 and 102 from planes 00 and 10 respectively and B2, with block 012 and 112 from planes 01 and 11 respectively. Hoshikawa also discloses in [0057] that “On the other hand, when receiving the SLC/MLC command, a command decoder 15 included in the peripheral circuits in the NAND 10 decodes the SLC/MLC command, and instructs each of the planes #P1 to #P4 to operate in any one of the SLC and MLC modes based on the decoding result”. Consequently, one possible command from Hoshikawa can result in B1 being in SLC mode and B2 in MLC mode. These therefore teach the limitation, as channel 0 is coupled to plane 00 from the first resource group and 01 from the second resource group, and channel 1 is coupled to plane 10 from the first resource group and 11 from the second resource group. Such a modification reads upon the limitation of the claim, as Byun shows each channel coupled with both resource groups in the plurality of resource groups (channel 0 coupled to planes 00 and 01 and channel 1 coupled to planes 10 and 11).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Byun’s multichannel system, as this allows for a channel interleaving scheme to aid with a simultaneous/parallel access to memory blocks within super memory blocks, see [0057].
Claim 15 recites instructions identical to the functional configurations of the memory system of claim 2 and can be rejected according to the rationale of claim 2. Hoshikawa fails to teach where the functional limitations are found in a non-transitory computer-readable medium storing comprising instructions, which, when executed by processing circuitry of a memory system, cause the memory system to perform the functional limitations.
Subbarao’s disclosure relates to a memory system and as such comprises analogous art in the same field of endeavor.
As part of this disclosure, Subbarao provides that “A non-transitory computer storage medium can be used to store instructions of the firmware of a memory sub-system (e.g., 110). When the instructions are executed by the controller 115 and/or the processing device 117, the instructions cause the controller 115 and/or the processing device 117 to perform a method discussed above,” [0101].
An obvious combination can be identified: combining Subbarao’s disclosure of instructions embodied on a non-transitory computer storage medium to be executed by a controller with Hoshikawa’s system. Such a combination reads upon the non-transitory, computer-readable medium storing code.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine Subbarao’s instruction embodiment with Hoshikawa’s system. Both disclosures are available as prior art, and as Subbarao’s disclosure demonstrates that the instructions are meant to be executed to perform the same procedures/processes disclosed in Subbarao related to storing data within a storage device with SLC/MLC memory cells, i.e. the same kind of memory technology as Hoshikawa’s memory system, then one of ordinary skill in the art would recognize that the ability to provide a system’s functions as instructions stored in code/memory is a predictable combination.
Claims 16 and 17 are rejected according to the same rationale of claims 3 and 4.
Claim 19 is a method claim that recites steps identical to the functional limitations of the memory system of claim 2, and as such can be rejected according to the same rationale of claim 2.
Claim 20 is rejected according to the same rationale of claim 3.
Claims 5-7, 12, 18, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Hoshikawa in view of Subbarao, Jayaraman, Mishra, and Byun, and further in view of Kurita et al. (US 2021/0405900, as presented in applicant’s IDS).
Regarding claim 5, the combination of Hoshikawa, Subbarao, Jayaraman, Mishra, and Byun teaches the memory system of claim 2, and Hoshikawa further teaches wherein, to configure the first resource group and the second resource group, the processing circuitry is further configured to cause the memory system to:
allocate, in accordance with a utilization of the plurality of resource groups satisfying a threshold, a first plane of a plurality of planes in the memory system and a second plane of the plurality of planes for the single-level programming; and
allocate, in accordance with the utilization of the plurality of resource groups satisfying the threshold, a third plane of the plurality of planes and a fourth plane of the plurality of planes for the multi-level programming, wherein:
the first resource group comprises the first plane and the second plane, and
the second resource group comprises the third plane and the fourth plane, as follows.
Hoshikawa discloses “On the other hand, when receiving the SLC/MLC command, a command decoder 15 included in the peripheral circuits in the NAND 10 decodes the SLC/MLC command, and instructs each of the planes #P1 to #P4 to operate in any one of the SLC and MLC modes based on the decoding result” [0057], teaching that a SLC/MLC command can designate any plane in any one of the SLC/MLC modes.
While not explicitly disclosed, Hoshikawa’s system with 4 planes necessarily only has 5 configuration options, 0 planes in SLC mode up through 4 planes in SLC mode, meaning one of the potential SLC/MLC commands that are taught is a 2 SLC/2 MLC plane configuration.
The combination fails to teach where the allocations occur in accordance with the utilization of the plurality of resource groups satisfying a threshold.
Kurita’s disclosure relates to operating memory between SLC and MLC modes, and as such comprises analogous art.
As part of this disclosure, Kurita provides for the ability to determine when to use SLC and TLC modes in writing data. In Fig. 10, Kurita sets a write mode as default to SLC (steps S126, S132), and later determines whether the write data exceeds the writable SLC size or the number of free blocks in the free block pool is insufficient (step S214). Based on this evaluation, the controller writes data in either the SLC mode (no branch back to steps S135/S136) or sets the write mode to TLC mode and writes data into TLC write destination block.
An obvious modification can be identified: incorporating Kurita’s determination of write size vs. the SLC write size and free blocks in a free block pool to determine whether to utilize SLC or TLC programming. Such a modification reads upon the limitation of the claim, as the assessment of the data write size reads upon how the planes are utilized and compares it to a threshold (writable data size in SLC mode). The alternate comparison of free blocks in the free block pool also relates to how the planes are utilized and presents a threshold for use. Such a modification then provides a basis to determine how many planes to designate for SLC/MLC modes.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Kurita’s SLC data size/free block pool considerations into Hoshikawa’s system, as Kurita’s factor provides for the ability to assess how efficient the system is being with storing data, as well as a mechanism to handle different efficiency scenarios.
Regarding claim 6, the combination of Hoshikawa, Subbarao, Jayaraman, Mishra, Byun, and Kurita teaches the memory system of claim 5, and the combination further teaches wherein:
the first virtual block spans the first plane and the second plane of the first resource group, and
the second virtual block spans the third plane and the fourth plane of the second resource groups (as discussed in the claim 2 rationale, Mishra Fig. 3 depicts logical blocks that span multiple planes, where Byun Fig. 2 shows the ability to configure how many blocks that a larger super block includes; in particular, where Byun’s A1 and A2 blocks depict the super block as spanning two planes each; as such, the combination disclosed in the claim 2 rationale reads upon the limitation of the claim, with further support provided by the claim 5 rationale discussion on how Hoshikawa’s disclosure provides for multiple permutations of the number and configuration of planes in SLC/MLC mode, including a 2 SLC/2 MLC configuration).
Regarding claim 7, the combination of Hoshikawa, Subbarao, Jayaraman, Mishra, and Byun teaches the memory system of claim 2, but fails to teach wherein the processing circuitry is further configured to cause the memory system to:
determine whether a utilization of the plurality of resource groups satisfies a threshold, wherein configuring the first resource group for the single-level programming and the second resource group for the multi-level programming is in accordance with determining that the utilization satisfies the threshold.
Kurita’s disclosure relates to operating memory between SLC and MLC modes, and as such comprises analogous art.
As part of this disclosure, Kurita provides for the ability to determine when to use SLC and TLC modes in writing data. In Fig. 10, Kurita sets a write mode as default to SLC (steps S126, S132), and later determines whether the write data exceeds the writable SLC size or the number of free blocks in the free block pool is insufficient (step S214). Based on this evaluation, the controller writes data in either the SLC mode (no branch back to steps S135/S136) or sets the write mode to TLC mode and writes data into TLC write destination block.
An obvious modification can be identified: incorporating Kurita’s determination of write size vs. the SLC write size and free blocks in a free block pool to determine whether to utilize SLC or TLC programming. Such a modification reads upon the limitation of the claim, as the assessment of the data write size reads upon how the planes are utilized and compares it to a threshold (writable data size in SLC mode). The alternate comparison of free blocks in the free block pool also relates to how the planes are utilized and presents a threshold for use. Such a modification then provides a basis to determine how many planes to designate for SLC/MLC modes.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Kurita’s SLC data size/free block pool considerations into Hoshikawa’s system, as Kurita’s factor provides for the ability to assess how efficient the system is being with storing data, as well as a mechanism to handle different efficiency scenarios.
Regarding claim 12, the combination of Hoshikawa, Subbarao, Jayaraman, Mishra, and Byun teaches the memory system of claim 10, but fails to teach wherein:
the first resource group is configured for the single-level programming and the second resource group is configured for the multi-level programming, in accordance with a first utilization of the plurality of resource groups exceeding a first threshold; and
the third resource group is configured for the single-level programming and the fourth resource group is configured for the multi-level programming, in accordance with a second utilization of the plurality of resource groups exceeding a second threshold.
Kurita’s disclosure relates to operating memory between SLC and MLC modes, and as such comprises analogous art.
As part of this disclosure, Kurita provides for the ability to determine when to use SLC and TLC modes in writing data. In Fig. 10, Kurita sets a write mode as default to SLC (steps S126, S132), and later determines whether the write data exceeds the writable SLC size or the number of free blocks in the free block pool is insufficient (step S214). Based on this evaluation, the controller writes data in either the SLC mode (no branch back to steps S135/S136) or sets the write mode to TLC mode and writes data into TLC write destination block.
An obvious modification can be identified: incorporating Kurita’s determination of write size vs. the SLC write size and free blocks in a free block pool to determine whether to utilize SLC or TLC programming. Such a modification reads upon the limitation of the claim, as the assessment of the data write size reads upon how the planes are utilized and compares it to a threshold (writable data size in SLC mode). The alternate comparison of free blocks in the free block pool also relates to how the planes are utilized and presents a threshold for use. Such a modification then provides a basis to determine how to designate the planes in SLC/MLC modes. Further, Kurita’s process is done on a device basis, see how Fig. 1 only depicts one flash memory device, so incorporating Kurita’s determination can also happen on a per-device basis, i.e. each of the memory devices can apply this determination, allowing for a second utilization of a different memory device to be compared to a second threshold.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Kurita’s SLC data size/free block pool considerations into Hoshikawa’s system, as Kurita’s factor provides for the ability to assess how efficient the system is being with storing data, as well as a mechanism to handle different efficiency scenarios.
Claims 18 and 21 are rejected according to the same rationale of claim 5.
Response to Arguments
Applicant's arguments filed November 7, 2025 have been fully considered and are moot in part and unpersuasive in part.
The arguments are moot in part, as additional citations to Jayaraman are provided to reject the newly amended limitations concerning the active state of the memory system and the applicant has not had opportunity to fully address the specific citations.
The arguments are unpersuasive in part, as upon review, the references to idle time period in Jayaraman are understood to be provided with respect to the particular dies/meta planes that are considering scheduling concurrent execution of memory operations, while the memory dies/meta planes with already scheduled operations are considered active see [0037,0040,0041,0054]. The arguments pointing out that Jayaraman and the prior office action repeatedly cite to identifying idle times is therefore unpersuasive given the additional context.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/A.D.H./Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139