DETAILED ACTION
Claims 1 – 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over:
Claims 1-20 of US. Patent 11,747,856 B2.
Claims 1-17 of US. Patent 11,487,316 B2.
Claims 1-20 of US. Patent 11,619,965 B2.
Claims 1-20 of US. Patent 12,135,580B2.
Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims are directed to substantially the same subject matter involving a selecting the clock candidate from a plurality of clock candidates based on the first clock frequency wherein selecting the clock candidate comprises comparing the data bit of a plurality of data bits.
Instant Application 18773471
US Patent 12135580
1. An electronic device comprising: circuitry configured to: receive a first clock, the first clock configured to operate at a frequency; and receive a second clock and a third clock, wherein:
the second clock is configured to operate at the frequency of the first clock and further configured to operate with a first phase shift with respect to the first clock,
the third clock is configured to operate at the frequency of the first clock and further configured to operate with a second phase shift with respect to the first clock, and
each of the second clock and the third clock is associated with a respective clock candidate selected from a plurality of clock candidates;
wherein: each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;
the selecting the respective clock candidate associated with the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock; and
the selecting the respective clock candidate associated with the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.
1. An electronic device comprising: circuitry configured to: receive a first clock, the first clock configured to operate at a frequency; and receive a second clock and a third clock,
the second clock and the third clock generated based on the first clock, wherein:
the second clock is configured to operate at the frequency of the first clock and further configured to operate with a first phase shift with respect to the first clock,
the third clock is configured to operate at the frequency of the first clock and further configured to operate with a second phase shift with respect to the first clock, and
the second clock and third clock are selected from a plurality of clock candidates;
wherein: each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;
the selecting the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock; and
the selecting the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.
Instant Application 18773471
US Patent No. 11,747,856 B2
1. An electronic device comprising: circuitry configured to: receive a first clock, the first clock configured to operate at a frequency; and receive a second clock and a third clock, wherein:
the second clock is configured to operate at the frequency of the first clock and further configured to operate with a first phase shift with respect to the first clock,
the third clock is configured to operate at the frequency of the first clock and further configured to operate with a second phase shift with respect to the first clock, and
each of the second clock and the third clock is associated with a respective clock candidate selected from a plurality of clock candidates;
wherein: each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;
the selecting the respective clock candidate associated with the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock; and
the selecting the respective clock candidate associated with the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.
1. An electronic device comprising: first circuitry configured to synchronize with a first clock, the first clock configured to operate at a frequency; and second circuitry configured to generate a second clock and a third clock based on the first clock, wherein:
the second clock is configured to operate at the frequency of the first clock and further configured to operate with a first phase shift with respect to the first clock,
the third clock is configured to operate at the frequency of the first clock and further configured to operate with a second phase shift with respect to the first clock, and
the second clock and third clock are selected from a plurality of clock candidates;
wherein: each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;
selecting the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock; and
selecting the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.
Instant Application 18773471
US Patent No. 11,487,316 B2
1. An electronic device comprising: circuitry configured to: receive a first clock, the first clock configured to operate at a frequency; and receive a second clock and a third clock, wherein:
the second clock is configured to operate at the frequency of the first clock and further configured to operate with a first phase shift with respect to the first clock,
the third clock is configured to operate at the frequency of the first clock and further configured to operate with a second phase shift with respect to the first clock, and
each of the second clock and the third clock is associated with a respective clock candidate selected from a plurality of clock candidates; wherein: each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;
the selecting the respective clock candidate associated with the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock; and
the selecting the respective clock candidate associated with the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.
1. An electronic device comprising: first circuitry configured to synchronize with a first clock, the first clock configured to operate at a frequency; second circuitry configured to generate a second clock and a third clock based on the first clock, wherein:
the second clock is configured to operate at the frequency of the first clock and further configured to operate with a first phase shift with respect to the first clock,
the third clock is configured to operate at the frequency of the first clock and further configured to operate with a second phase shift with respect to the first clock, and
the second clock and third clock are selected from a plurality of clock candidates, the plurality of clock candidates associated with a plurality of phase shifts relative to the first clock;
third circuitry configured to synchronize with the second clock; a data bus electronically coupled between the first circuitry and the third circuitry, wherein the first circuitry is further configured to transmit data to the third circuitry via the data bus; and a first latch configured to receive the data and synchronize with the third clock, wherein the third clock is selected from the plurality of clock candidates based on a latency between the first circuitry and the first latch.
Instant Application 18773471
US Patent 11,619,965 B2
1. An electronic device comprising: circuitry configured to: receive a first clock, the first clock configured to operate at a frequency; and receive a second clock and a third clock, wherein:
the second clock is configured to operate at the frequency of the first clock and further configured to operate with a first phase shift with respect to the first clock,
the third clock is configured to operate at the frequency of the first clock and further configured to operate with a second phase shift with respect to the first clock, and
each of the second clock and the third clock is associated with a respective clock candidate selected from a plurality of clock candidates;
wherein: each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;
the selecting the respective clock candidate associated with the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock; and
the selecting the respective clock candidate associated with the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.
1. An electronic device comprising: first circuitry configured to synchronize with a first clock, the first clock configured to operate at a frequency; second circuitry configured to generate a second clock and a third clock based on the first clock, wherein:
the second clock is configured to operate at the frequency of the first clock and further configured to operate with a first phase shift with respect to the first clock,
the third clock is configured to operate at the frequency of the first clock and further configured to operate with a second phase shift with respect to the first clock, and
the second clock and third clock are selected from a plurality of clock candidates; and third circuitry configured to synchronize with the second clock,
wherein: each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;
selecting the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock; and
selecting the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.
Claims 11 and 20 are rejected for the same reasons as set forth in claim 1.
All other dependent claims are rejected for their dependency.
Conclusion
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/PHIL K NGUYEN/Primary Examiner, Art Unit 2176