DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-17 are pending in this application.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 07/22/2025 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The terms "high voltage" and/or “low voltage” in claims 1, 2, 6-8, and 12-14 are relative terms which renders the claims indefinite. The terms "low voltage" and “high voltage” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitations "high voltage monitor” and “low voltage monitor” have been rendered indefinite by the use of the terms “high voltage” and/or “low voltage” because without a reference, any voltage can be explained as high voltage or low voltage. For the purposes of examination, the examiner has interpreted "high voltage monitor" and “low voltage monitor” to be a voltage detector with a threshold voltage. Claims 3-5, 9-11, and 15-17 are rejected based on their dependency on claims 1, 2, 7, 8, or 12-14.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 5-7, 11-13, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukuhara et al. European Patent Document EP 3713033 A1 (hereinafter “Fukuhara”) and further in view of Tsai et al. U.S. Patent Application 2002/0130645 (hereinafter “Tsai”).
Regarding claim 1, Fukuhara teaches a power supply over-voltage protection (OVP) system (refer to fig.3), comprising: a transistor (i.e. FET 40)(fig.3) having: a source terminal (implicit)(refer to terminal of FET 40 connected to current detector 30)(fig.3) configured to connect to a power supply output terminal (i.e. converter output terminal 21)(fig.3) of a power supply (i.e. converter 20)(fig.3); a drain terminal (implicit)(refer to terminal of FET 40 connected to output terminal 11) configured to connect to a system load (refer to load 70)(fig.2); and a body diode forward voltage drop (refer to body diode of FET 40)(fig.3) between the source terminal and the drain terminal (implicit); a low voltage monitor circuit (i.e. voltage monitor 50 and switching element Q14)(fig.3) connected between the source terminal and a gate terminal of the transistor (implicit), the low voltage monitor circuit being configured to monitor a source voltage at the source terminal (refer to [0043]) and provide a gate control signal to the gate terminal (refer to [0043]), the gate control signal determined by the source voltage (refer to [0043]); and a second monitor circuit (i.e. current detector 30)(fig.3) connected to the source terminal (implicit) and configured to be connected to a control circuit within the power supply (refer to feedback terminal 23)(fig.3), the second monitor circuit being configured to provide a power supply control signal to the power supply (refer to current signal ID)(fig.4); however, Fukuhara does not teach wherein the second monitor circuit is a high voltage monitor circuit, the high voltage monitor circuit being configured to monitor the source voltage at the source terminal and the power supply control signal determined by the source voltage. However, Tsai teaches wherein the second monitor circuit is a high voltage monitor circuit (i.e. comparator 207)(fig.2), the high voltage monitor circuit being configured to monitor the source voltage at the source terminal (refer to abstract)(the voltage at the output of the buck converter is monitored) and the power supply control signal determined by the source voltage (implicit)(refer to comparator 207)(fig.2). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Fukuhara to include the high voltage monitor circuit of Tsai to provide the advantage of protecting the load from overvoltages, thereby protecting the load and the transistor from damage.
Regarding claim 5, Fukuhara and Tsai teach the power supply OVP system of claim 1, wherein the transistor is a metal oxide semiconductor field effect transistor (MOSFET) (i.e. Fukuhara FET 40)(fig.3).
Regarding claim 6, Fukuhara teaches a power supply over-voltage protection (OVP) system (refer to fig.3), comprising: a low voltage monitor circuit (i.e. FET 40, voltage monitor 50, and switching element Q14)(fig.3) configured to connect between a power supply output terminal (i.e. converter output terminal 21)(fig.3) of a power supply (i.e. converter 20)(fig.3) and a system load (refer to load 70)(fig.2), the low voltage monitor circuit configured to monitor a power supply output voltage at the power supply output terminal (refer to [0043]) and provide a load voltage to the system load (refer to [0043]), the load voltage determined by a level of the power supply output voltage relative to a first threshold voltage level (refer to [0043]); and a second monitor circuit (i.e. current detector 30)(fig.3) configured to be connected between the power supply output terminal of the power supply (implicit) and a control circuit within the power supply (refer to feedback terminal 23)(fig.3); however, Fukuhara does not teach wherein the second monitor circuit is a high voltage monitor circuit, the high voltage monitor circuit configured to monitor the power supply output voltage at the power supply output terminal and turn off the power supply output voltage via the control circuit within the power supply when the power supply output voltage is equal to or greater than a second threshold voltage level. However, Tsai teaches wherein the second monitor circuit is a high voltage monitor circuit (i.e. comparator 207)(fig.2), the high voltage monitor circuit configured to monitor the power supply output voltage at the power supply output terminal (implicit)(refer to comparator 207)(fig.2)(refer also to abstract) and turn off the power supply output voltage via the control circuit within the power supply (refer to abstract) when the power supply output voltage is equal to or greater than a second threshold voltage level (refer to Vref2)(fig.2)(refer also to abstract). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Fukuhara to include the high voltage monitor circuit of Tsai to provide the advantage of protecting the load from overvoltages, thereby protecting the load from damage.
Regarding claim 6, Fukuhara teaches a power supply over-voltage protection (OVP) system, comprising: a low voltage monitor circuit configured to connect between a power supply output terminal of a power supply and a system load, the low voltage monitor circuit configured to monitor a power supply output voltage at the power supply output terminal and provide a load voltage to the system load, the load voltage determined by a level of the power supply output voltage relative to a first threshold voltage level; and a high voltage monitor circuit configured to be connected between the power supply output terminal of the power supply and a control circuit within the power supply, the high voltage monitor circuit configured to monitor the power supply output voltage at the power supply output terminal and turn off the power supply output voltage via the control circuit within the power supply when the power supply output voltage is equal to or greater than a second threshold voltage level.
Regarding claim 7, Fukuhara and Tsai teach the power supply OVP system of claim 6, wherein the low voltage monitor circuit comprises a transistor (i.e. Fukuhara FET 40)(fig.3), the transistor having: a source terminal (implicit)(refer to terminal of FET 40 connected to current detector 30)(fig.3) configured to connect to the power supply output terminal (i.e. converter output terminal 21)(fig.3) of the power supply (i.e. converter 20)(fig.3); a drain terminal (implicit)(refer to terminal of FET 40 connected to output terminal 11) configured to connect to the system load (refer to load 70)(fig.2); and a body diode forward voltage drop (refer to body diode of FET 40)(fig.3) between the source terminal and the drain terminal (implicit).
Regarding claim 11, Fukuhara and Tsai teach the power supply OVP system of claim 7, wherein the transistor is a metal oxide semiconductor field effect transistor (MOSFET) (i.e. Fukuhara FET 40)(fig.3).
Regarding claim 12, Fukuhara teaches a power supply over-voltage protection (OVP) system (refer to fig.3), comprising: a power supply (i.e. converter 20)(fig.3); a low voltage monitor circuit (i.e. FET 40, voltage monitor 50, and switching element Q14)(fig.3) connected between a power supply output terminal (i.e. converter output terminal 21)(fig.3) of the power supply (i.e. converter 20)(fig.3) and a system load terminal (i.e. output terminal 11)(fig.3)(refer also to load 70)(fig.2), the low voltage monitor circuit configured to monitor a power supply output voltage at the power supply output terminal (refer to [0043]) and provide a load voltage to the system load terminal (refer to [0043]), the load voltage determined by a level of the power supply output voltage relative to a first threshold voltage level (refer to [0043]); and a second monitor circuit (i.e. current detector 30)(fig.3) connected between the power supply output terminal of the power supply (implicit) and a control circuit within the power supply (refer to feedback terminal 23)(fig.3); however, Fukuhara does not teach wherein the second monitor circuit is a high voltage monitor circuit, the high voltage monitor circuit configured to monitor the power supply output voltage at the power supply output terminal and turn off the power supply output voltage via the control circuit within the power supply when the power supply output voltage is equal to or greater than a second threshold voltage level. However, Tsai teaches wherein the second monitor circuit is a high voltage monitor circuit (i.e. comparator 207)(fig.2), the high voltage monitor circuit configured to monitor the power supply output voltage at the power supply output terminal (implicit)(refer to comparator 207)(fig.2)(refer also to abstract) and turn off the power supply output voltage via the control circuit within the power supply (refer to abstract) when the power supply output voltage is equal to or greater than a second threshold voltage level (refer to Vref2)(fig.2)(refer also to abstract). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Fukuhara to include the high voltage monitor circuit of Tsai to provide the advantage of protecting the load from overvoltages, thereby protecting the load from damage.
Regarding claim 13, Fukuhara and Tsai teach the power supply OVP system of claim 12, wherein the low voltage monitor circuit comprises a transistor (i.e. Fukuhara FET 40)(fig.3), the transistor having: a source terminal (implicit)(refer to terminal of FET 40 connected to current detector 30)(fig.3) connected to the power supply output terminal (i.e. converter output terminal 21)(fig.3) of the power supply (i.e. converter 20)(fig.3); a drain terminal (implicit)(refer to terminal of FET 40 connected to output terminal 11) connected to the system load terminal (refer to output terminal 11)(fig.3); and a body diode forward voltage drop (refer to body diode of FET 40)(fig.3) between the source terminal and the drain terminal (implicit).
Regarding claim 16, Fukuhara and Tsai teach the power supply OVP system of claim 12, wherein the control circuit within the power supply is a direct current (DC) to DC converter that supplies power to the power supply output terminal (refer to Fukuhara converter 20)(fig.3)(refer also to Fukuhara [0044]).
Regarding claim 17, Fukuhara and Tsai teach the power supply OVP system of claim 13, wherein the transistor is a metal oxide semiconductor field effect transistor (MOSFET) (i.e. Fukuhara FET 40)(fig.3).
Allowable Subject Matter
Claims 2-4, 8-10, 14, and 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claims 2-4 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 2, especially wherein the low voltage monitor circuit, upon determining the source voltage to be below a first threshold voltage level, causes the gate control signal to keep the transistor on; and upon determining the source voltage to be equal to or greater than the first threshold voltage level and less than a second threshold voltage level, causes the gate control signal to turn the transistor off; and wherein, the high voltage monitor circuit, upon determining the source voltage to be equal to or greater than the second threshold voltage level, causes the control circuit within the power supply to turn off power delivered to the power supply output terminal. Claims 3 and 4 are indicated as containing allowable subject matter based on their dependency on claim 2. Claims 8-10 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 8, especially wherein: the low voltage monitor circuit, upon determining the power supply output voltage to be less than the first threshold voltage level, provides a gate control signal to a gate terminal of the transistor to keep the transistor on; upon determining the power supply output voltage to be equal to or greater than the first threshold voltage level and less than a second threshold voltage level, provides a gate control signal to the gate terminal of the transistor to turn the transistor off. Claims 9 and 10 are indicated as containing allowable subject matter based on their dependency on claim 8. Claims 14 and 15 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim14, especially wherein: the low voltage monitor circuit, upon determining the power supply output voltage to be less than the first threshold voltage level, provides a gate control signal to a gate terminal of the transistor to keep the transistor on; upon determining the power supply output voltage to be equal to or greater than the first threshold voltage level and less than a second threshold voltage level, provides a gate control signal to the gate terminal of the transistor to turn the transistor off. Claim 15 is indicated as containing allowable subject matter based on its dependency on claim 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN J COMBER whose telephone number is (571)272-6133. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEVIN J COMBER/Primary Examiner, Art Unit 2838