DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10, 15 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al (US 2014/0239293 A1).
Regarding claim 1, Yamazaki et al discloses a thin film transistor (Figure 1C, reference 200), comprising: a first active layer (Figure 1C, reference 106) disposed on a side of a substrate (Figure 1C, reference 100), the first active layer (Figure 1C, reference 106b) including a first surface away (Figure 1C, uppermost portion of reference 106b) from the substrate (Figure 1C, reference 100); a second active layer (Figure 1C, reference 106a) disposed on a side of the first active layer (Figure 1C, uppermost portion of reference 106b) away from the substrate (Figure 1C, reference 100), the second active layer (Figure 1C, reference 106a) including a second surface (Figure 1C, lowermost portion of reference 106a) in contact with the first surface (Figure 1C, uppermost portion of reference 106b); a first electrode (Figure 1C, reference 116), wherein the first electrode (Figure 1C, reference 116), the first active layer (Figure 1C, reference 106b) and the second active layer (Figure 106a) have an overlapping region (paragraph 0066) among orthographic projections of the first electrode (Figure 1C, reference 116), the first active layer (Figure 1C, reference 106b) and the second active layer (Figure 1C, reference 106a) on the substrate (Figure 1C, reference 100); a second electrode (Figure 1C, reference 112a), wherein the second electrode (Figure 1C, reference 112a) the first active layer (Figure 1C, reference 106b) and the second active layer (Figure 1C, reference 106a) have an overlapping region (paragraph 0066) among orthographic projections of the second electrode (Figure 1C, reference 112a), the first active layer (Figure 1C, reference 106b) and the second active layer )Figure 1C, reference 16a) on the substrate (Figure 1C, reference 100); and a third electrode (Figure 1C, reference 112b), wherein the third electrode (Figure 1C, reference 112b), the first active layer (Figure 1C, reference 106b) and the second active layer (Figure 1C, reference 106a) have an overlapping region (paragraph 0066) among orthographic projections of the third electrode (Figure 1C, reference 112b), the first active layer (Figure 1C, reference 106b) and the second active layer (Figure 1C, reference 106a) on the substrate (Figure 1C, reference 100), and the third electrode (Figure 1C, reference 112b) is opposite to the second electrode (Figure 1C, reference 112a); wherein the second surface (Figure 1C, reference 106a) is located within the first surface (Figure 1C, reference 106b), and a distance between at least part of a border of the second surface (Figure 1C, reference 106a) and a border of the first surface (Figure 1C, reference 106b) is less than or equal to 0.5µm (paragraph 0135).
Regarding claim 2, Yamazaki et al discloses wherein an orthographic projection, on the substrate, of a surface of the first active layer close to the second active layer covers an orthographic projection, on the substrate, of a surface of the second active layer close to the first active layer (Figure 1C).
Regarding claim 3, Yamazaki et al discloses wherein the second surface includes a first region (Figure 1C, reference 106a), and an orthographic projection of the first region (Figure 1C, reference 106a) on the substrate (Figure 1C, reference 100) completely overlaps with an orthographic projection of the first electrode (Figure 1C, reference 116) on the substrate (Figure 1C, reference 100); a distance between a border of the first region (Figure 1C, reference 106a) and the border of the first surface (Figure 1C, uppermost portion of reference 106b) is less than or equal to 0.5µm (paragraph 0135).
Regarding claim 4, Yamazaki et al discloses wherein an included angle between a sidewall of the first active layer and the substrate is in a range of 10º to 90º; and/or, an included angle between a sidewall of the second active layer and the substrate is in a range of 10º to 90º (Figure 1C).
Regarding claim 5, Yamazaki et al discloses wherein the first electrode (Figure 1C, reference 116) is disposed on a side of the second active layer (Figure 1C, uppermost portion of reference 106a) away from the substrate (Figure 1C, reference 100); a carrier mobility of the first active layer is less than that of the second active layer, and a conduction band of the first active layer is greater than that of the second active layer (paragraphs 0055 and 0065-0069).
Regarding claim 6, Yamazaki et al discloses wherein a ratio of a thickness of the first active layer (Figure 1C, reference 16b) to a thickness of the second active layer (Figure 1C, reference 106a) is in a range of 2 to 5 (paragraphs 0065, 0068 and 0074).
Regarding claim 7, Yamazaki et al discloses wherein the thickness of the second active layer is greater than or equal to 5 nm; and/or the thickness of the first active layer is greater than or equal to 20 nm; and/or a sum of the thickness of the first active layer and the thickness of the second active layer is in a range of 30 nm to 50 nm (Figure 1C, reference 106; paragraphs 0065, 0068 and 0074).
Regarding claim 8, Yamazaki et al discloses further comprising: a third active layer (Figure 1C, reference 108) disposed on a side of the second active layer (Figure 1C, uppermost portion of reference 106a) away from the substrate (Figure 1C, reference 100), the third active layer (Figure 1C, reference 18) including a third surface (Figure 1C, lowermost portion of reference 108) in contact with the second active layer (Figure 1C, uppermost portion of reference 106a), wherein the second active layer (Figure 1C, uppermost portion of reference 106a) further includes a fourth surface (Figure 1C, left/right side surface of reference 106a) in contact with the third surface (Figure 1C, reference 108), the third surface (Figure 1C, reference 108) is located within the fourth surface (Figure 1C, left side surface of reference 106a), and a distance between a border of the third surface (Figure 1C, reference 108) and a border of the fourth surface (Figure 1C, left/right side surface of reference 106a) is less than or equal to 0.5µm (paragraph 0222).
Regarding claim 9, Yamazaki et al discloses wherein an included angle between a sidewall of the third active layer and the substrate is in a range of 10º to 90º; and/or a thickness of the third active layer is in a range of 5 nm to 10 nm; and/or a sum of a thickness of the first active layer, a thickness of the second active layer, and a thickness of the third active layer is in a range of 30 nm to 50 nm (paragraph 0064).
Regarding claim 10, Yamazaki et al discloses wherein a material of the first active layer includes indium gallium zinc oxide, praseodymium-doped indium zinc oxide, or aluminum-doped indium tin zinc oxide (Figure 1C, reference 106b; paragraphs 0052-0056, 0061 and 0062); and/or a material of the second active layer (Figure 1C, reference 106a) includes indium zinc oxide, indium gallium oxide, indium gallium tin oxide or indium tin zinc oxide (paragraphs 0052-0056, 0061 and 0062); and/or a material of the third active layer (Figure 1C, reference 108) includes indium gallium zinc oxide, praseodymium-doped indium zinc oxide, or aluminum-doped indium tin zinc oxide (paragraphs 0052-0056, 0061 and 0062).
Regarding claim 15, Yamazaki et al discloses an array substrate, comprising: a substrate; a plurality of thin film transistors each according to claim 1, the plurality of thin film transistors being disposed on a side of the substrate (Figures 15-17).
Regarding claim 20, Yamazaki et al discloses A display apparatus, comprising: the array substrate according to claim 15 (Figure 18A).
Allowable Subject Matter
Claims 11-14 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose nor fairly suggest a thin film transistor, comprising: wherein the first electrode is disposed on a side of the first active layer close to the substrate; a carrier mobility of the first active layer is greater than that of the second active layer, and a conduction band of the first active layer is less than that of the second active layer (claim 11) and further comprising: a conductive layer disposed on a side of the plurality of thin film transistors away from the substrate and connected to the plurality of thin film transistors; and a light-emitting chip disposed on the side of the plurality of thin film transistors away from the substrate, wherein the conductive layer includes pads, and a pad is connected to the light-emitting chip, wherein the array substrate has an array region and a bonding region; the array substrate further comprises a driving circuit, and the plurality of thin film transistors are located in the driving circuit; the driving circuit includes a source-drain conductive layer including pins located in the bonding region, the pins being configured to be connected to a circuit board, wherein a reducibility of a material of the source-drain conductive layer is lower than that of a material of the conductive layer (claim 15), incorporated inro the independent claim and in the context of its recited apparatus, along with its depending claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MONICA D HARRISON/ Primary Examiner, Art Unit 2815
mdh
October 9, 2026
Prosecution Insights