DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to Application 18/773721 filed on July 16, 2024 in which Claims 1-20 are presented for examination.
Status of Claims
Claims 1, 2, 5, 8, 10 and 17 have been amended. Claims 1-20 are pending, of which claims 1-20 are rejected under 103.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 10, 12 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US Patent Application 2022/0208293) in view of Ivanov (US Patent Application 2017/0344299).
Claim 1, Hong teaches a method of operating a memory device including a memory cell array (Hong, Fig 4. Paragraph [0081] “The memory cell array may include a plurality of memory cells (e.g., a memory cell MC).”) and a memory circuit (Hong, Paragraph [0003] "A memory system may include various electronic circuits to store data and to output the stored data, and may be implemented on a single electronic device or over a plurality of electronic devices."), the method comprising: receiving an operation command from a controller (Hong, Paragraph [0070] " As the read request is received from the host, the memory controller may provide the read command to a memory device in which the requested data is stored. Accordingly, the memory device which has received the read command may perform the first operation by an internal function circuit."); performing a normal operation using the first device information in response to the operation command, wherein the normal operation including a read operation or a program operation on the memory cell array (Hong, Paragraph [0008] " The first function circuit may perform a first operation based on data stored in the memory device to generate first processed data, in response to the read command."); receiving a first command from the controller (Hong, Paragraph [0070] " As the read request is received from the host, the memory controller may provide the read command to a memory device in which the requested data is stored. Accordingly, the memory device which has received the read command may perform the first operation by an internal function circuit."); wherein the first device information includes information about an operation parameter (Hong, Paragraph [0071] "For example, the status information STAT may include information associated with at least one of various conditions, e.g., whether the memory devices include the internal function circuits (i.e., whether each of the memory devices supports the first operation), whether performing the first operation in each of the memory devices is enabled, a type of the first operation, the capability of each of the internal function circuits, a condition of each of the memory devices where the first operation is performed, and/or the like.") and an operating frequency of the memory device (Hong, Paragraph [0072] "For example, the condition of each of the memory devices where the first operation is performed may be associated with various factors such as a communication bandwidth, a device temperature, an expected remaining lifespan, and/or the like. ", Examiner interprets communication bandwidth as operating frequency.).
Hong does not explicitly teach storing first device information in the memory circuit; determining, in response to the first command, whether first device information stored in the memory circuit has an error; receiving, in response to the determining that the first device information has the error, a reset command from the controller; and performing a refresh operation on the memory circuit in response to the reset command.
However, Ivanov teaches storing first device information in the memory circuit (Ivanov, Paragraph [0049] "the operational parameters and/or instructions executable by the control system may be stored in the memory device.”); determining, in response to the first command, whether first device information stored in the memory circuit has an error (Ivanov, Paragraph [0003], [0021], [0025], [0038], [0049] "However, memory errors may occur in data stored in the memory device and, thus, affect operation of the control system and/or the automation system. For example, when the memory device includes DRAM, a fixed memory error may occur when gradual decrease in voltage of a storage capacitor causes the indicated value of a corresponding data bit to flip (e.g., from “1” to “0” or vice versa).”); receiving, in response to the determining that the first device information has the error, a reset command from the controller (Ivanov, Paragraph [0021], [0029], [0049] "in some embodiments, refreshing the memory device (e.g., DRAM) may facilitate reducing likelihood and/or number of fixed memory errors that occur in the memory device.”); and performing a refresh operation on the memory circuit in response to the reset command (Ivanov, Paragraph [0029] " In other words, refreshing the memory device may be used to supplement the error correction process, which may facilitate improving operational reliability of the control system and/or the automation system.”).
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with performing a refresh operation as taught by Ivanov because the harden latches help increase reliability against errors. (Ivanov, Paragraph [0029] " In other words, refreshing the memory device may be used to supplement the error correction process, which may facilitate improving operational reliability of the control system and/or the automation system.”).
Claim 10, Hong teaches a method of operating a controller to control a memory device including a memory cell array and a memory circuit (Hong, Fig 4. Paragraph [0081] “The memory cell array may include a plurality of memory cells (e.g., a memory cell MC).”), the method comprising: transmitting an operation command for performing a normal operation using the device information to the memory device, wherein the normal operation including a read operation or a program operation on the memory cell array (Hong, Paragraph [0008] " The first function circuit may perform a first operation based on data stored in the memory device to generate first processed data, in response to the read command."); transmitting a first command to the memory device (Hong, Paragraph [0070] " As the read request is received from the host, the memory controller may provide the read command to a memory device in which the requested data is stored. Accordingly, the memory device which has received the read command may perform the first operation by an internal function circuit."); transmitting a status read command to the memory device (Hong, Paragraph [0070] " As the read request is received from the host 1100, the memory controller may provide the read command to a memory device in which the requested data is stored. Accordingly, the memory device which has received the read command may perform the first operation by an internal function circuit."); receiving status information from the memory device (Hong, Paragraph [0008] "The memory controller may provide the read command to the memory device in response to a read request received from a host, such that the data is output to the memory device. The memory controller may receive status information associated with performing the first operation."); wherein the device information includes information about an operation parameter (Hong, Paragraph [0071] "For example, the status information STAT may include information associated with at least one of various conditions, e.g., whether the memory devices include the internal function circuits (i.e., whether each of the memory devices supports the first operation), whether performing the first operation in each of the memory devices is enabled, a type of the first operation, the capability of each of the internal function circuits, a condition of each of the memory devices where the first operation is performed, and/or the like.") and an operating frequency of the memory device (Hong, Paragraph [0072] "For example, the condition of each of the memory devices where the first operation is performed may be associated with various factors such as a communication bandwidth, a device temperature, an expected remaining lifespan, and/or the like. ", Examiner interprets communication bandwidth as operating frequency.).
Hong does not explicitly teach storing device information in the memory circuit; determining whether an error is present in the device information stored in the memory circuit included in the memory device based on the status information; and transmitting, in response to determining that the error is present in the device information, a reset command for refreshing the memory circuit to the memory device.
However, Ivanov teaches storing device information in the memory circuit (Ivanov, Paragraph [0049] "the operational parameters and/or instructions executable by the control system may be stored in the memory device.”); determining whether an error is present in the device information stored in the memory circuit included in the memory device based on the status information (Ivanov, Paragraph [0003], [0021], [0025], [0038], [0049] "However, memory errors may occur in data stored in the memory device and, thus, affect operation of the control system and/or the automation system. For example, when the memory device includes DRAM, a fixed memory error may occur when gradual decrease in voltage of a storage capacitor causes the indicated value of a corresponding data bit to flip (e.g., from “1” to “0” or vice versa).”); and transmitting, in response to determining that the error is present in the device information, a reset command for refreshing the memory circuit to the memory device (Ivanov, Paragraph [0021], [0029], [0049] "in some embodiments, refreshing the memory device (e.g., DRAM) may facilitate reducing likelihood and/or number of fixed memory errors that occur in the memory device.”).
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with performing a refresh operation as taught by Ivanov because the harden latches help increase reliability against errors. (Ivanov, Paragraph [0029] " In other words, refreshing the memory device may be used to supplement the error correction process, which may facilitate improving operational reliability of the control system and/or the automation system.”).
Claim 12, most of the limitations of this claim has been noted in the rejection of Claim 10. Hong further teaches the status information includes information about a cyclic redundancy check (CRC)-check result of the device information stored in the memory circuit (Hong, Paragraph [0125] “Accordingly, when the status information STAT3 indicates that performing the first error processing operation is enabled, the variable ECC circuit may operate in the second manner (e.g., in the CRC manner) to detect more errors." Fig. 10 showcases that the STAT3 (status information) is taken from Memory device”).
Claim 17, Hong teaches a method of operating a storage device which includes a memory device including a memory cell array and a memory circuit and a controller (Hong, Paragraph [0003] "A memory system may include various electronic circuits to store data and to output the stored data, and may be implemented on a single electronic device or over a plurality of electronic devices."), the method comprising: transmitting, by the controller, an operation command to a controller (Hong, Paragraph [0070] " As the read request is received from the host 1100, the memory controller may provide the read command to a memory device in which the requested data is stored. Accordingly, the memory device which has received the read command may perform the first operation by an internal function circuit."); performing, by the memory device, a normal operation using the device information in response to the operation command, wherein the normal operation including a read operation or a program operation on the memory cell array (Hong, Paragraph [0008] " The first function circuit may perform a first operation based on data stored in the memory device to generate first processed data, in response to the read command."); receiving, by the controller, a result of the CRC-check operation from the memory device (Hong, Paragraph [0136] “As such, the memory controller may output the error detection result according to the second error processing operation. When the manner of the second error processing operation is changed, the error detection result may be changed.”); wherein the device information includes information about an operation parameter (Hong, Paragraph [0071] "For example, the status information STAT may include information associated with at least one of various conditions, e.g., whether the memory devices include the internal function circuits (i.e., whether each of the memory devices supports the first operation), whether performing the first operation in each of the memory devices is enabled, a type of the first operation, the capability of each of the internal function circuits, a condition of each of the memory devices where the first operation is performed, and/or the like.") and an operating frequency of the memory device (Hong, Paragraph [0072] "For example, the condition of each of the memory devices where the first operation is performed may be associated with various factors such as a communication bandwidth, a device temperature, an expected remaining lifespan, and/or the like. ", Examiner interprets communication bandwidth as operating frequency.).
Hong does not explicitly teach storing device information in the memory circuit; transmitting, by the controller, a first command for initiating a cyclic redundancy check (CRC)-check operation to the memory device; performing, by the memory device, the CRC-check operation a cyclic redundancy check (CRC)-check operation on the device information stored in the memory circuit of the memory device in response to the first command; transmitting, by the controller, a reset command to the memory device in response to the result of the CRC-check operation indicating that an error is present in the device information; and performing, by the memory device, a refresh operation on the memory device in response to the reset command.
However, Ivanov teaches storing device information in the memory circuit (Ivanov, Paragraph [0049] "the operational parameters and/or instructions executable by the control system may be stored in the memory device.”); transmitting, by the controller, a first command for initiating a cyclic redundancy check (CRC)-check operation to the memory device (Ivanov, Paragraph [0055] “the memory device may augment the stored data with error check data before outputting to the processing device.”); performing, by the memory device, the CRC-check operation a cyclic redundancy check (CRC)-check operation on the device information stored in the memory circuit of the memory device in response to the first command (Ivanov, Paragraph [0055] “the memory device may perform a hash function on the stored data to determine a hash function result (e.g., error check data), such as a parity bit, checksum bits, cyclic redundancy bits, a hash value, and/or the like, which may be concatenated and output with the stored data.”); transmitting, by the controller, a reset command to the memory device in response to the result of the CRC-check operation indicating that an error is present in the device information (Ivanov, Paragraph [0003], [0021], [0025], [0038], [0049] "However, memory errors may occur in data stored in the memory device and, thus, affect operation of the control system and/or the automation system. For example, when the memory device includes DRAM, a fixed memory error may occur when gradual decrease in voltage of a storage capacitor causes the indicated value of a corresponding data bit to flip (e.g., from “1” to “0” or vice versa).”); and performing, by the memory device, a refresh operation on the memory device in response to the reset command (Ivanov, Paragraph [0021], [0029], [0049] "in some embodiments, refreshing the memory device (e.g., DRAM) may facilitate reducing likelihood and/or number of fixed memory errors that occur in the memory device.”).
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with performing a refresh operation as taught by Ivanov because the harden latches help increase reliability against errors. (Ivanov, Paragraph [0029] " In other words, refreshing the memory device may be used to supplement the error correction process, which may facilitate improving operational reliability of the control system and/or the automation system.”).
Claim(s) 2, 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US Patent Application 2022/0208293) in view of Ivanov (US Patent Application 2017/0344299) and further in view of Bowman (US Patent Application 2017/0060673).
Claim 2, most of the limitations of this claim has been noted in the rejection of Claim 1. The combination of teachings does not explicitly teach wherein the storing of the first device information includes storing the first device information in a plurality of latch circuits of the memory circuit by programming a plurality of programmable electrical fuses of the memory circuit.
However, Bowman teaches wherein the storing of the first device information includes storing the first device information in a plurality of latch circuits of the memory circuit (Bowman, Paragraph [0003] "The logic is configured to store the parity check data in a first latch of the plurality of latches." FIG.6 illustrates the hardened latches are part of the check bit. ") by programming a plurality of programmable electrical fuses of the memory circuit (Bowman, Paragraph [0020] "To help identify soft errors in the parity data stored in the registers, the processor stores parity check data in the hardened latches" Examiner interprets storing the parity data to indicate programming/writing to hardened latches.).
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with hardened latches as taught by Bowman because the harden latches help increase reliability against errors. (Bowman, Paragraph [0014], “In one embodiment, to reduce the likelihood that the parity check data becomes corrupted, the computing system stores this data in hardened latches which are less susceptible to soft errors than other types of memory elements such as RAM.”)
Claim 8, most of the limitations of this claim has been noted in the rejection of Claim 1. Hong further teaches receiving a second command (Hong, Paragraph [0061] "Each of the memory devices may output stored data, in response to a read command received from the memory controller.") and an updated device information from the controller; and performing, in response to the second command (Hong, Paragraph [0071] " For example, the status information STAT may include information associated with at least one of various conditions, e.g., whether the memory devices include the internal function circuits (i.e., whether each of the memory devices supports the first operation), ..."), an operation of programming the updated device information in the memory cell array (Hong Paragraph [0076]"For example, when the status information STAT is changed from first information to second information, context of the second processed data pDAT may be changed from first context to second context which is different from the first context.").
The combination of teachings does not explicitly teach generating an updated parity of the updated device information, and writing the updated device information and the updated parity in the memory circuit as the first device information and a first parity stored in the memory circuit.
However, Bowman teaches generating an updated parity (Bowman, Paragraph [0041] "Later, when performing the second partial write, the computing system generates a second parity value for the data in the second partial write and stores this value in a second parity entry in the register. When retrieving the first and second parity values to perform error correction, the parity values can be combined to yield a combined parity value for the data in both the first and second partial writes." Examiner interpret the combined parities to mean updated parity data.”) of the updated device information (Bowman, Paragraph [0015] and FIG. 6 "The parity data helps the processor detect, and possibly correct, soft errors in the data entry" Examiner interpret the possible correction in data entry as an update, and additionally FIG.6 illustrates that data entry is stored with the parity data.), and writing the updated device information and the updated parity in the memory circuit as the first device information and a first parity stored in the memory circuit. (Bowman, Paragraph [0043] "Moreover, the computing system also generates separate parity check values for each of the partial writes. For example, the parity check bit corresponds to the first parity value stored in entry, while the parity check bit corresponds to the second parity value stored in entry. Thus, when reading out the data stored in register 600, the computing system can reference the parity check bits to ensure the parity values in entries were not corrupted. As described above, the parity check bits are stored in hardened latches, and thus, are less susceptible to soft errors than the data stored in the register." Reference indicates that register is the first parity register location.)
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with multiple parity bits as taught by Bowman in order to identify if an error has occurred in a created parity bit. (Bowman, Paragraph [0026], “The parity check data is used by the processor to determine whether there is an error in the parity data stored in the parity entry”).
Claim 9, most of the limitations of this claim has been noted in the rejection of Claim 1. Hong further teaches performing an initialization operation on the memory device (Hong, Paragraph [0169], “For example, when the memory devices and the memory controller are physically connected or when communication between the memory devices and the memory controller is reset, a connection initialization operation may be performed.”).
The combination of teachings does not explicitly teach wherein the performing of the initialization operation includes: generating a second parity based on second device information stored in the memory cell array; and writing the second device information and the second parity in the memory circuit as the first device information and a first parity related to the first device information.
However, Bowman teaches wherein the performing of the initialization operation includes: generating a second parity based on second device information stored in the memory cell array (Bowman, Paragraph [0003] & Paragraph [0041] "According to one embodiment of the present invention, an integrated circuit includes a memory including a plurality of registers, each register includes a data entry and a parity entry." and "Later, when performing the second partial write, the computing system generates a second parity value for the data in the second partial write and stores this value in a second parity entry in the register."); and writing the second device information and the second parity in the memory circuit as the first device information and a first parity related to the first device information (Bowman, Paragraph [0043] " Moreover, the computing system also generates separate parity check values for each of the partial writes. For example, the parity check bit corresponds to the first parity value stored in entry, while the parity check bit corresponds to the second parity value stored in entry. Thus, when reading out the data stored in register, the computing system can reference the parity check bits to ensure the parity values in entries were not corrupted. As described above, the parity check bits are stored in hardened latches, and thus, are less susceptible to soft errors than the data stored in the register." Reference indicates that register 600 is the first parity register location.)
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with multiple parity bits as taught by Bowman in order to identify if an error has occurred in a created parity bit. (Bowman, Paragraph [0026], “The parity check data is used by the processor to determine whether there is an error in the parity data stored in the parity entry”).
Claim(s) 3, 11, 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US Patent Application 2022/0208293) in view of Ivanov (US Patent Application 2017/0344299) and further in view of Kim (US Patent Application 2022/0208293).
Claim 3, most of the limitations of this claim has been noted in the rejection of Claim 1. The combination of teachings does not explicitly teach the first command is a reserved command defined in a memory interface protocol between the controller and the memory device, a vendor command, or a combination of at least two operation commands defined in the memory interface protocol.
However, Kim teaches the first command is a reserved command defined in a memory interface protocol between the controller and the memory device (Kim, Paragraph [0074] "The control logic circuit includes a command decoder that decodes the command CMD received from the memory controller and a mode register that sets an operation mode of the semiconductor memory device."), a vendor command, or a combination of at least two operation commands defined in the memory interface protocol (Kim, Paragraph [0063] & [0064] " When the command CMD from the memory controller corresponds to a self-refresh entry command, the control logic circuit may apply the second refresh control signal IREF2 to the refresh control circuit and the second refresh control signal IREF2 is activated from a time point when the control logic circuit receives the self-refresh entry command to a time point when control logic circuit receives a self-refresh exit command. The refresh control circuit may sequentially increase or decrease the refresh row address REF_ADDR in response to receiving the first refresh control signal IREF1 or during the second refresh control signal IREF2 is activated.").
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the error locator as taught by Kim with the memory controller of Hong because identification of error locations within memory during a scrubbing operation. (Kim, Paragraph [0052] " … the first memory cell row in the fault address register 580 as a row fault address based on the number of error occurrences in the first memory cell row during the first interval in the scrubbing operation")
Claim 11 is the method corresponding to the method of Claim 3 and is therefore rejected under the same reasons set forth in the rejection of Claim 3.
Claim 18 is the method corresponding to the method of Claim 3 and is therefore rejected under the same reasons set forth in the rejection of Claim 3.
Claim 16, most of the limitations of this claim has been noted in the rejection of Claim 10. The combination of teachings does not explicitly teach detecting whether a driving time of the memory device reaches a reference time, wherein the transmitting of the first command to the memory device is performed in response to detecting that the driving time of the memory device reaches the reference time.
However, Kim teaches detecting whether a driving time of the memory device reaches a reference time (Kim, Paragraph [0171] " In FIG. 22A, tRFC denotes a refresh cycle and means a time for refreshing one memory cell row, and tREFI denotes a refresh interval and means an interval between two consecutive refresh commands." Examiner interprets reaching two consecutive refresh commands as the reached reference time.), wherein the transmitting of the first command to the memory device is performed in response to detecting that the driving time of the memory device reaches the reference time (Kim, Paragraph [0172] " Referring to FIG. 22A, it is noted that the scrubbing control circuit 500 designates at least one memory cell row, on which the ECC circuit performs the scrubbing operation SCRB S times whenever the normal refresh operation NREF is performed on memory cell rows N times in response to the refresh command." ).
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with detecting whether a driving time of the memory device reaches a reference time as taught by Kim in order to determine a time for a refresh operation. (Kim, Paragraph [0172] " Referring to FIG. 22A, it is noted that the scrubbing control circuit 500 designates at least one memory cell row, on which the ECC circuit performs the scrubbing operation SCRB S times whenever the normal refresh operation NREF is performed on memory cell rows N times in response to the refresh command.").
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US Patent Application 2022/0208293) in view of Ivanov (US Patent Application 2017/0344299) and further in view of Seno (US Patent Application 2022/0413748).
Claim 4, most of the limitations of this claim has been noted in the rejection of Claim 1. Ivanov further teaches the determining of whether the first device information has the error includes: performing a CRC-check operation on the first device information based on a first parity stored in the memory circuit (Ivanov, Paragraph [0055] "Additionally or alternatively, the memory device may perform a hash function on the stored data to determine a hash function result (e.g., error check data), such as a parity bit, checksum bits, cyclic redundancy bits, a hash value, and/or the like, which may be concatenated and output with the stored data.");
The combination of teachings does not explicitly teach writing a result of the CRC-check operation in a status register; receiving a status read command from the controller; and transmitting a value of the status register to the controller in response to the status read command.
However, Seno teaches writing a result of the CRC-check operation in a status register (Seno, Paragraph [0043] "Then, the status register of the embodiment will be described. As shown in Table 1, the status register holds the CRC error information based on the CRC processing unit, which includes, for example, whether the CRC result is passed or failed, the number of CRC retries, a measured time of the timer (used for subsequent judgment of whether the predetermined time Tn is reached) etc."); receiving a status read command from the controller (Seno, Paragraph [0044] FIG. 9, " FIG. 9 is a flowchart illustrating a method of reading data from the status register. After the user inputs a reading command of the status register to the flash memory, the controller accesses the status register according to an interpretation result of the reading command, and outputs the CRC error information or the ECC information held in the status register through the input/output circuit."); and transmitting a value of the status register to the controller in response to the status read command (Seno, Paragraph [0044] FIG. 9, " FIG. 9 is a flowchart illustrating a method of reading data from the status register. After the user inputs a reading command of the status register to the flash memory, the controller accesses the status register according to an interpretation result of the reading command, and outputs the CRC error information or the ECC information held in the status register through the input/output circuit 120.")
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with status registers as taught by Seno because the status registers hold information pertaining to the CRC error, including results indicating a pass or fail. (Seno, Paragraph [0043], “ As shown in Table 1, the status register holds the CRC error information based on the CRC processing unit, which includes, for example, whether the CRC result is passed or failed, the number of CRC retries,… .”)
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US Patent Application 2022/0208293) in view of Ivanov (US Patent Application 2017/0344299) in view of Hasegawa (US Patent Application 2012/0278663) in view of Kim (US Patent Application 2022/0208293) and further in view of Bowman (US Patent Application 2017/0060673).
Claim 5, most of the limitations of this claim has been noted in the rejection of Claim 1. The combination of teachings does not explicitly teach storing second device information in the memory cell array , wherein the performing of the refresh operation on the memory circuit in response to the reset command includes: reading the second device information stored in the memory cell array; generating a second parity of the second device information; and writing the second parity and the second device information in the memory circuit as the first device information and a first parity related to the first device information.
However, Hasegawa teaches storing second device information in the memory cell array (Hasegawa, Paragraph [0007], “This technology controls an access to a memory array space composed of a plurality of data storage apparatuses and accumulates operation performance data from each data storage apparatus in a history log. This technology analyzes the operation performance data in order to detect the abnormal operation of the data storage apparatus and starts a correction process of the data storage apparatus in response to the analysis.”)
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with storing device information as taught by Hasegawa in order to determine fault operational data for a memory device. (Hasegawa, Paragraph [0007], “This technology controls an access to a memory array space composed of a plurality of data storage apparatuses and accumulates operation performance data from each data storage apparatus in a history log. This technology analyzes the operation performance data in order to detect the abnormal operation of the data storage apparatus and starts a correction process of the data storage apparatus in response to the analysis.”).
The combination of teachings does not explicitly the performing of the refresh operation on the memory circuit in response to the reset command includes: reading the second device information stored in the memory cell array; generating a second parity of the second device information; and writing the second parity and the second device information in the memory circuit as the first device information and a first parity related to the first device information.
However, Kim teaches performing of the refresh operation on the memory circuit in response to the reset command (Kim Paragraph [0062-0064] "The refresh control circuit may sequentially output the refresh row address REF_ADDR in response to a first refresh control signal IREF1 or a second refresh control signal IREF2 from the control logic circuit.") includes: reading the second device information stored in the memory cell array (Kim, Paragraph [0053] "The control logic circuit may control the ECC circuit to perform the error detection and correction operation on the second memory cell row in the second interval of the scrubbing operation." Examiner interprets performing error correction and detection to indicate reading information. )
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with a scrubbing control circuit as taught by Kim because the scrubbing circuit generates scrubbing locations for memory refresh operations. (Kim, Paragraph [0008], “The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row selected from the plurality of memory cell rows based on refresh row addresses for refreshing the memory cell rows.”)
The combination of teachings does not explicitly teach generating a second parity of the second device information; and writing the second parity and the second device information in the memory circuit as the first device information and a first parity related to the first device information.
However, Bowman teaches explicitly teach generating a second parity of the second device information (Bowman, Paragraph [0041] "Later, when performing the second partial write, the computing system generates a second parity value for the data in the second partial write and stores this value in a second parity entry in the register."); and writing the second parity and the second device information in the memory circuit as the first device information and a first parity related to the first device information .” (Bowman, Paragraph [0043] " Moreover, the computing system also generates separate parity check values for each of the partial writes. For example, the parity check bit corresponds to the first parity value stored in entry, while the parity check bit corresponds to the second parity value stored in entry. Thus, when reading out the data stored in register, the computing system can reference the parity check bits to ensure the parity values in entries were not corrupted. As described above, the parity check bits are stored in hardened latches, and thus, are less susceptible to soft errors than the data stored in the register." Reference indicates that register is the first parity register location. ).
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with multiple parity bits as taught by Bowman in order to identify if an error has occurred in a created parity bit. (Bowman, Paragraph [0026], “The parity check data is used by the processor to determine whether there is an error in the parity data stored in the parity entry.”)
Claim(s) 6, 13 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US Patent Application 2022/0208293) in view of Ivanov (US Patent Application 2017/0344299) and further in view of Uribe (US Patent Application 2023/0205615).
Claim 6, most of the limitations of this claim has been noted in the rejection of Claim 1. The combination of teachings does not explicitly teach receiving the first command from the controller which detects an input/output exception occurring during an operation of the memory device.
However, Uribe teaches receiving the first command from the controller which detects an input/output exception occurring during an operation of the memory device (Uribe, Paragraph [0032] "For example, the memory device may include circuitry configured to detect the occurrence of an error associated with a power supply of the memory device, an error associated with a clock of the memory device, an error associated with an access operation performed on the memory device, or the like. In some examples, multiple errors may be detected or errors may be detected in parallel (e.g., an error associated with a clock of the memory device may be detected upon receiving an access command).”).
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with detecting an access failure as taught by Uribe in order to identify an error stored in a memory device. (Uribe, Paragraph [0032] "For example, the memory device may include circuitry configured to detect the occurrence of an error associated with a power supply of the memory device, an error associated with a clock of the memory device, an error associated with an access operation performed on the memory device, or the like. In some examples, multiple errors may be detected or errors may be detected in parallel (e.g., an error associated with a clock of the memory device may be detected upon receiving an access command).
Claim 13, most of the limitations of this claim has been noted in the rejection of Claim 10. Ivanov further teaches wherein the transmitting of the first command to the memory device is performed in response to detecting that the input/output exception occurs in the memory device (Ivanov, Paragraph [0021], [0029], [0049] " To facilitate meeting higher operational reliability standards, likelihood and/or number of memory errors occurring in data output (e.g., read) from the memory device may be reduced. For example, likelihood and/or number of fixed memory errors (e.g., resulting from gradual decrease in stored voltage) occurring may be reduced by refreshing (e.g., rewriting stored data) the memory device (e.g., DRAM).)
The combination of teachings does not explicitly teach detecting whether an input/output exception occurs in an operation of the memory device.
However, Uribe teaches detecting whether an input/output exception occurs in an operation of the memory device (Uribe, Paragraph [0032] "For example, the memory device may include circuitry configured to detect the occurrence of an error associated with a power supply of the memory device, an error associated with a clock of the memory device, an error associated with an access operation performed on the memory device, or the like. In some examples, multiple errors may be detected or errors may be detected in parallel (e.g., an error associated with a clock of the memory device may be detected upon receiving an access command).”).
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with detecting an access failure as taught by Uribe in order to identify an error stored in a memory device. (Uribe, Paragraph [0032] "For example, the memory device may include circuitry configured to detect the occurrence of an error associated with a power supply of the memory device, an error associated with a clock of the memory device, an error associated with an access operation performed on the memory device, or the like. In some examples, multiple errors may be detected or errors may be detected in parallel (e.g., an error associated with a clock of the memory device may be detected upon receiving an access command).
Claim 19 is the method corresponding to the method of Claim 13 and is therefore rejected under the same reasons set forth in the rejection of Claim 13.
Claim(s) 7, 15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US Patent Application 2022/0208293) in view of Ivanov (US Patent Application 2017/0344299) and further in view of Veches (US Patent Application 2023/0395116).
Claim 7, most of the limitations of this claim has been noted in the rejection of Claim 1. The combination of teachings does not explicitly teach the first command is received from the controller which detects that the memory device is in an idle time period.
However, Veches teaches the first command is received from the controller which detects that the memory device is in an idle time period (Veches Paragraph [0012] "For example, a host device may determine that data in a memory bank is no longer in use and send a reset command indicating the memory device to update the refresh region to an unused state containing no memory row addresses" Examiner interprets the memory bank no longer in use as an idle memory device.)
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with components of the host as taught by Veches in order to identify if a memory device is in idle state or is not being used allowing the host to free up the memory regions. (Veches, Paragraph [0057], “For example, a host device may determine that data in a memory bank is no longer in use and send a reset command indicating the memory device to update the refresh region to an unused state containing no memory row addresses.”)
Claim 15, detecting whether the memory device is in an idle time period, wherein the transmitting of the first command is performed in response to detecting that the memory device is in the idle time period.
However, Veches teaches detecting whether the memory device is in an idle time period (Veches, Paragraph [0057], “For example, a host device may determine that data in a memory bank is no longer in use and send a reset command indicating the memory device to update the refresh region to an unused state containing no memory row addresses.”), wherein the transmitting of the first command is performed in response to detecting that the memory device is in the idle time period (Veches Paragraph [0012] "For example, a host device may determine that data in a memory bank is no longer in use and send a reset command indicating the memory device to update the refresh region to an unused state containing no memory row addresses." Examiner interprets the memory bank no longer in use as an idle memory device.)
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with components of the host as taught by Veches in order to identify if a memory device is in idle state or is not being used allowing the host to free up the memory regions. (Veches, Paragraph [0057], “For example, a host device may determine that data in a memory bank is no longer in use and send a reset command indicating the memory device to update the refresh region to an unused state containing no memory row addresses.”)
Claim 20 is the method corresponding to the method of Claim 15 and is therefore rejected under the same reasons set forth in the rejection of Claim 15.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US Patent Application 2022/0208293) in view of Ivanov (US Patent Application 2017/0344299) and further in view of Uribe (US Patent Application 2023/0205615) and further in view of Aoki (US Patent Application 2006/0092828).
Claim 14, most of the limitations of this claim has been noted in the rejection of Claim 13. The combination of teachings does not explicitly teach performing, in response to the detecting of the input/output exception and determining that the error is absent from the device information, a recovery operation on the memory device.
However, Aoki teaches performing, in response to the detecting of the input/output exception and determining that the error is absent from the device information, a recovery operation on the memory device (Aoki, Paragraph [0055], “More specifically, the failure recovery detection unit periodically performs an I/O processing to the path where a failure has been detected by the failure detection unit, and checks whether normal processing has been performed to determine whether the failure has been recovered. When the normal processing has been performed, the failure recovery detection unit notifies the failure recovery information including the path ID to the path information management unit.”)
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with performing a recovery operation as taught by Aoki in order to perform normal processing. (Aoki, Paragraph [0055], “More specifically, the failure recovery detection unit periodically performs an I/O processing to the path where a failure has been detected by the failure detection unit, and checks whether normal processing has been performed to determine whether the failure has been recovered. When the normal processing has been performed, the failure recovery detection unit notifies the failure recovery information including the path ID to the path information management unit.”)
Response to Arguments
Applicant's arguments filed July 16, 2024 have been fully considered but they are not persuasive.
Applicant’s arguments, see pages, filed November 25, 2025, with respect to the rejection(s) of claim(s) 1, 10 and 17 under Hong and Kim have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ivanov.
Applicant’s arguments, see pages, filed November 25, 2025, with respect to the rejection(s) of claim(s) 6, 13 and 19 under Jeong have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Uribe.
Applicant’s arguments, see pages, filed November 25, 2025, with respect to the rejection(s) of claim(s) 14 under Jeong have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Aoki.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
Miller et al. (US 2022/0165163 A1) teaches power module and/or an input/output node (e.g., input/output node operating in the T2 network) can readthe fault information stored in fault status storage to determine current fault conditions (if any) present within the power system of unmanned system. In some examples, some or all of the status data in fault status storage can be remotely reset or cleared to indicate a de-asserted status; e.g., to clear stored fault condition data once one or more fault conditions have been corrected.
Rangarajan et al. (US 2014/0006879 A1) teaches the additional data may include, for example, the source of the poisoned data and/or suggestions for handling the poisoned data. The memory controller may then, in turn, write the poisoned data to the system memory in a write operation. This writing operation may include writing the poisoned data to the system memory such that it includes a poison signature to identify the poisoned (bad or corrupted) nature of the data and/or a hint based on the additional data regarding the poisoned data.
Communication
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/SARAI E BUTLER/Primary Examiner, Art Unit 2114
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