DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is Non-Final.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 07/16/2024 is in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. It has been placed in the application file and the information referred to therein has been considered on the merits.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 5, 10 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “first device information” in line 4, there is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation “second device information” in line 4, there is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation “device information” in line 6, there is insufficient antecedent basis for this limitation in the claim.
Claim 17 recites the limitation “device information” in line 5, there is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,3,10-12, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 20190179699 A1), hereinafter “Hong”, in view of Kim et at. (US 20220208293 A1) hereinafter “Kim”.
With regards to Claim 1, Hong teaches:
“A method of operating a memory device including a memory cell array” (Hong, Fig 4. Paragraph [0081]) “and a memory circuit,” (Hong, Paragraph [0003] "A memory system may include various electronic circuits to store data and to output the stored data, and may be implemented on a single electronic device or over a plurality of electronic devices.") “the method comprising: receiving a first command from a controller;” (Hong, Paragraph [0070] " As the read request is received from the host 1100, the memory controller 2300 may provide the read command to a memory device in which the requested data is stored. Accordingly, the memory device which has received the read command may perform the first operation by an internal function circuit.") “determining, in response to the first command, “ (Hong, Paragraph [0008] "The memory controller may provide the read command to the memory device in response to a read request received from a host, such that the data is output to the memory device. The memory controller may receive status information associated with performing the first operation.") “whether first device information stored in the memory circuit has an error;” (Hong, Paragraph [0008] & [0009] " The memory device may perform a first error processing operation based on data stored in the memory device to generate first processed data.") .
Hong does not explicitly teach: “receiving, in response to the determining that the first device information has the error, a reset command from the controller; and performing a refresh operation on the memory circuit in response to the reset command,”
Kim teaches: “receiving, in response to the determining that the first device information has the error,” (Kim, Paragraph [0052] " … the first memory cell row in the fault address register 580 as a row fault address based on the number of error occurrences in the first memory cell row during the first interval in the scrubbing operation") “a reset command from the controller;” (Kim Paragraph [0062-0064] "The refresh control circuit 385 may sequentially output the refresh row address REF_ADDR in response to a first refresh control signal IREF1 or a second refresh control signal IREF2 from the control logic circuit 210.") “and performing a refresh operation on the memory circuit in response to the reset command,” (Kim Paragraph [0062-0064] "The refresh control circuit 385 may sequentially output the refresh row address REF_ADDR in response to a first refresh control signal IREF1 or a second refresh control signal IREF2 from the control logic circuit 210.").
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with a scrubbing control circuit as taught by Kim because the scrubbing circuit generates scrubbing locations for memory refresh operations. (Kim, Paragraph [0008], “The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row selected from the plurality of memory cell rows based on refresh row addresses for refreshing the memory cell rows. ”)
Kim does not explicitly teach:
“wherein the first device information includes information about an operation parameter and an operating frequency of the memory device.”
Hong teaches:
“wherein the first device information includes information about an operation parameter” (Hong, Paragraph [0071] "For example, the status information STAT may include information associated with at least one of various conditions, e.g., whether the memory devices 2110, 2120, and 2190 include the internal function circuits 2111, 2121, and 2191 (i.e., whether each of the memory devices 2110, 2120, and 2190 supports the first operation), whether performing the first operation in each of the memory devices 2110, 2120, and 2190 is enabled, a type of the first operation, the capability of each of the internal function circuits 2111, 2121, and 2191, a condition of each of the memory devices 2110, 2120, and 2190 where the first operation is performed, and/or the like.") “and an operating frequency of the memory device.” (Hong, Paragraph [0072] "For example, the condition of each of the memory devices 2110, 2120, and 2190 where the first operation is performed may be associated with various factors such as a communication bandwidth, a device temperature, an expected remaining lifespan, and/or the like. ", Examiner interprets communication bandwidth as operating frequency.)
With regards to claim 3,
Hong does not explicitly teach:
“The method of claim 1, wherein the first command is a reserved command defined in a memory interface protocol between the controller and the memory device, a vendor command, or a combination of at least two operation commands defined in the memory interface protocol.”
Kim teaches:
“The method of claim 1, wherein the first command is a reserved command defined in a memory interface protocol between the controller and the memory device,” (Kim, Paragraph [0074] "The control logic circuit 210 includes a command decoder 211 that decodes the command CMD received from the memory controller 100 and a mode register 212 that sets an operation mode of the semiconductor memory device 200."), “a vendor command, or a combination of at least two operation commands defined in the memory interface protocol.” (Kim, Paragraph [0063] & [0064] " When the command CMD from the memory controller 100 corresponds to a self-refresh entry command, the control logic circuit 210 may apply the second refresh control signal IREF2 to the refresh control circuit 385 and the second refresh control signal IREF2 is activated from a time point when the control logic circuit 210 receives the self-refresh entry command to a time point when control logic circuit 210 receives a self-refresh exit command. The refresh control circuit 385 may sequentially increase or decrease the refresh row address REF_ADDR in response to receiving the first refresh control signal IREF1 or during the second refresh control signal IREF2 is activated.")
With regards to claim 10, Hong teaches:
“A method of operating a controller to control a memory device,” (Hong, Paragraph [0003] "A memory system may include various electronic circuits to store data and to output the stored data, and may be implemented on a single electronic device or over a plurality of electronic devices.") the method comprising: transmitting a first command to the memory device; “(Hong, Paragraph [0070] " As the read request is received from the host 1100, the memory controller 2300 may provide the read command to a memory device in which the requested data is stored. Accordingly, the memory device which has received the read command may perform the first operation by an internal function circuit.") “transmitting a status read command to the memory device;” (Hong, Paragraph [0070] " As the read request is received from the host 1100, the memory controller 2300 may provide the read command to a memory device in which the requested data is stored. Accordingly, the memory device which has received the read command may perform the first operation by an internal function circuit.") “receiving status information from the memory device;” (Hong, Paragraph [0008] "The memory controller may provide the read command to the memory device in response to a read request received from a host, such that the data is output to the memory device. The memory controller may receive status information associated with performing the first operation.") “determining whether an error is present in device information stored in a memory circuit included in the memory device based on the status information;” (Hong, Paragraph [0008] & [0009] " The memory device may perform a first error processing operation based on data stored in the memory device to generate first processed data." Reference further describes that the data stored in the memory devices is status information associated with performing the first operation. )
Hong does not explicitly teach:
“and transmitting, in response to determining that the error is present in the device information, a reset command for refreshing the memory circuit to the memory device, wherein the device information includes information about an operation parameter and an operating frequency of the memory device.”
Kim teaches:
“and transmitting, in response to determining that the error is present in the device information,” (Kim, Paragraph [0052] " … the first memory cell row in the fault address register 580 as a row fault address based on the number of error occurrences in the first memory cell row during the first interval in the scrubbing operation") “a reset command for refreshing the memory circuit to the memory device,” (Kim Paragraph [0062-0064] "The refresh control circuit 385 may sequentially output the refresh row address REF_ADDR in response to a first refresh control signal IREF1 or a second refresh control signal IREF2 from the control logic circuit 210.")
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with a scrubbing control circuit as taught by Kim because the scrubbing circuit generates scrubbing locations for memory refresh operations. (Kim, Paragraph [0008], “The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row selected from the plurality of memory cell rows based on refresh row addresses for refreshing the memory cell rows. ”)
Kim does not explicitly teach:
“wherein the device information includes information about an operation parameter and an operating frequency of the memory device.”
Hong teaches:
“wherein the device information includes information about an operation parameter” (Hong, Paragraph [0071] "For example, the status information STAT may include information associated with at least one of various conditions, e.g., whether the memory devices 2110, 2120, and 2190 include the internal function circuits 2111, 2121, and 2191 (i.e., whether each of the memory devices 2110, 2120, and 2190 supports the first operation), whether performing the first operation in each of the memory devices 2110, 2120, and 2190 is enabled, a type of the first operation, the capability of each of the internal function circuits 2111, 2121, and 2191, a condition of each of the memory devices 2110, 2120, and 2190 where the first operation is performed, and/or the like.") and an operating frequency of the memory device.” (Hong, Paragraph [0072] "For example, the condition of each of the memory devices 2110, 2120, and 2190 where the first operation is performed may be associated with various factors such as a communication bandwidth, a device temperature, an expected remaining lifespan, and/or the like. ", Examiner interprets communication bandwidth as operating frequency.)
With regards to claim 11, Hong does not explicitly teach:
“The method of claim 10, wherein the first command is a reserved command defined in a memory interface protocol between the controller and the memory device, a vendor command, or a combination of at least two operation commands defined in the memory interface protocol.”
Kim teaches:
“The method of claim 10, wherein the first command is a reserved command defined in a memory interface protocol between the controller and the memory device,” (Kim, Paragraph [0074] "The control logic circuit 210 includes a command decoder 211 that decodes the command CMD received from the memory controller 100 and a mode register 212 that sets an operation mode of the semiconductor memory device 200."), “a vendor command, or a combination of at least two operation commands defined in the memory interface protocol.” (Kim, Paragraph [0063] & [0064] " When the command CMD from the memory controller 100 corresponds to a self-refresh entry command, the control logic circuit 210 may apply the second refresh control signal IREF2 to the refresh control circuit 385 and the second refresh control signal IREF2 is activated from a time point when the control logic circuit 210 receives the self-refresh entry command to a time point when control logic circuit 210 receives a self-refresh exit command. The refresh control circuit 385 may sequentially increase or decrease the refresh row address REF_ADDR in response to receiving the first refresh control signal IREF1 or during the second refresh control signal IREF2 is activated.")
With regards to claim 12, Hong teaches:
“The method of claim 10, wherein the status information includes information about a cyclic redundancy check (CRC)-check result of the device information stored in the memory circuit.” ( Hong, Paragraph [0125] Accordingly, when the status information STAT3 indicates that performing the first error processing operation is enabled, the variable ECC circuit 3310 may operate in the second manner (e.g., in the CRC manner) to detect more errors." Fig. 10 showcases that the STAT3 (status information) is taken from Memory device 3100).
With regards to claim 16, Hong does not explicitly teach:
“The method of claim 10, further comprising: detecting whether a driving time of the memory device reaches a reference time, wherein the transmitting of the first command to the memory device is performed in response to detecting that the driving time of the memory device reaches the reference time.”
Kim teaches:
“The method of claim 10, further comprising: detecting whether a driving time of the memory device reaches a reference time,” (Kim, Paragraph [0171] " In FIG. 22A, tRFC denotes a refresh cycle and means a time for refreshing one memory cell row, and tREFI denotes a refresh interval and means an interval between two consecutive refresh commands." Examiner interprets reaching two consecutive refresh commands as the reached reference time.) “wherein the transmitting of the first command to the memory device is performed in response to detecting that the driving time of the memory device reaches the reference time.” (Kim, Paragraph [0172] " Referring to FIG. 22A, it is noted that the scrubbing control circuit 500 designates at least one memory cell row, on which the ECC circuit performs the scrubbing operation SCRB S times whenever the normal refresh operation NREF is performed on memory cell rows N times in response to the refresh command." )
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with a scrubbing control circuit as taught by Kim because the scrubbing circuit generates scrubbing locations for memory refresh operations. (Kim, Paragraph [0008], “The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row selected from the plurality of memory cell rows based on refresh row addresses for refreshing the memory cell rows. ”)
With regards to claim 17, Hong teaches:
“An method of operating a storage device which includes a memory device and a controller,” (Hong, Paragraph [0003] "A memory system may include various electronic circuits to store data and to output the stored data, and may be implemented on a single electronic device or over a plurality of electronic devices.") “the method comprising: transmitting, by the controller, a first command to the memory device;” (Hong, Paragraph [0070] " As the read request is received from the host 1100, the memory controller 2300 may provide the read command to a memory device in which the requested data is stored. Accordingly, the memory device which has received the read command may perform the first operation by an internal function circuit.") “performing, by the memory device, a cyclic redundancy check (CRC)-check operation (Hong, Paragraph [0122] “ he ECC circuits 3111, 3121, and 3191 may be enabled according to an operation policy of the memory system 3000 and/or the host 1100.”, Paragraph [0124] “ For example, the variable ECC circuit 3310 may perform the second error processing operation in a cyclic redundancy check (CRC) manner such that three or more error bits are detected without error correction.” Reference Hong, teaches memory device that can operate in different modalities.) on device information stored in a memory circuit of the memory device in response to the first command” (Hong, Paragraph [0070] " As the read request is received from the host 1100, the memory controller 2300 may provide the read command to a memory device in which the requested data is stored. Accordingly, the memory device which has received the read command may perform the first operation by an internal function circuit.") “receiving, by the controller, a result of the CRC-check operation from the memory device; (Hong, Paragraph [0136] “ As such, the memory controller 3300 may output the error detection result according to the second error processing operation. When the manner of the second error processing operation is changed, the error detection result may be changed.”)
Hong does not explicitly teach:
“transmitting, by the controller, a reset command to the memory device in response to the result of the CRC-check operation indicating that an error is present in the device information; and performing, by the memory device, a refresh operation on the memory device in response to the reset command, wherein the device information includes information about an operation parameter and an operating frequency of the memory device.”
Kim teaches:
“transmitting, by the controller, a reset command to the memory device in response to the result of the CRC-check operation” (Kim, Paragraph [0172] “Referring to FIG. 22A, it is noted that the scrubbing control circuit 500 designates at least one memory cell row, on which the ECC circuit performs the scrubbing operation SCRB S times whenever the normal refresh operation NREF is performed on memory cell rows N times in response to the refresh command.”) “Indicating that an error is present in the device information;” (Kim, Paragraph [0165] “The error locator 460 may generate an error position signal EPS indication a position of an error bit in the read data RMD to provide the error position signal EPS to the data corrector 470 when all bits of the syndrome SDR are not ‘zero’) and performing, by the memory device, a refresh operation on the memory device in response to the reset command,” (Kim Paragraph [0062-0064] "The refresh control circuit 385 may sequentially output the refresh row address REF_ADDR in response to a first refresh control signal IREF1 or a second refresh control signal IREF2 from the control logic circuit 210.")
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the error locator as taught by Kim with the memory controller of Hong because identification of error locations within memory during a scrubbing operation. (Kim, Paragraph [0052] " … the first memory cell row in the fault address register 580 as a row fault address based on the number of error occurrences in the first memory cell row during the first interval in the scrubbing operation")
Kim does not explicitly teach:
“wherein the device information includes information about an operation parameter and an operating frequency of the memory device.”
Hong teaches:
“wherein the device information includes information about an operation parameter” (Hong, Paragraph [0071] "For example, the status information STAT may include information associated with at least one of various conditions, e.g., whether the memory devices 2110, 2120, and 2190 include the internal function circuits 2111, 2121, and 2191 (i.e., whether each of the memory devices 2110, 2120, and 2190 supports the first operation), whether performing the first operation in each of the memory devices 2110, 2120, and 2190 is enabled, a type of the first operation, the capability of each of the internal function circuits 2111, 2121, and 2191, a condition of each of the memory devices 2110, 2120, and 2190 where the first operation is performed, and/or the like.") “and an operating frequency of the memory device.” (Hong, Paragraph [0072] "For example, the condition of each of the memory devices 2110, 2120, and 2190 where the first operation is performed may be associated with various factors such as a communication bandwidth, a device temperature, an expected remaining lifespan, and/or the like. ", Examiner interprets communication bandwidth as operating frequency.)
With regards to claim 18, Hong does not explicitly teach:
“The method of claim 17, wherein the first command is a reserved command defined in a memory interface protocol between the controller and the memory device, a vendor command, or a combination of at least two operation commands defined in the memory interface protocol.”
Kim teaches:
“The method of claim 10, wherein the first command is a reserved command defined in a memory interface protocol between the controller and the memory device,” (Kim, Paragraph [0074] "The control logic circuit 210 includes a command decoder 211 that decodes the command CMD received from the memory controller 100 and a mode register 212 that sets an operation mode of the semiconductor memory device 200."), “a vendor command, or a combination of at least two operation commands defined in the memory interface protocol.” (Kim, Paragraph [0063] & [0064] " When the command CMD from the memory controller 100 corresponds to a self-refresh entry command, the control logic circuit 210 may apply the second refresh control signal IREF2 to the refresh control circuit 385 and the second refresh control signal IREF2 is activated from a time point when the control logic circuit 210 receives the self-refresh entry command to a time point when control logic circuit 210 receives a self-refresh exit command. The refresh control circuit 385 may sequentially increase or decrease the refresh row address REF_ADDR in response to receiving the first refresh control signal IREF1 or during the second refresh control signal IREF2 is activated.")
Claim(s) 2, 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 20190179699 A1), hereinafter “Hong”, in view of Kim et at. (US 20220208293 A1) hereinafter “Kim”, further in view of Bowman et at. (US 20170060673 A1) hereinafter “Bowman”.
With respect to claim 2, Hong in view of Kim does not explicitly teach:
“The method of claim 1, further comprising: storing the first device information in a plurality of latch circuits of the memory circuit by programming a plurality of programmable electrical fuses of the memory circuit.”
Bowman teaches:
“The method of claim 1, further comprising: storing the first device information in a plurality of latch circuits of the memory circuit” (Bowman, Paragraph [0003] "The logic is configured to store the parity check data in a first latch of the plurality of latches." FIG.6 illustrates the hardened latches are part of the check bit. ") “by programming a plurality of programmable electrical fuses of the memory circuit.” (Bowman, Paragraph [0020] "To help identify soft errors in the parity data stored in the registers 120, the processor 105 stores parity check data 140 in the hardened latches" Examiner interprets storing the parity data to indicate programming/writing to hardened latches. )
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with hardened latches as taught by Bowman because the harden latches help increase reliability against errors. (Bowman, Paragraph [0014], “ In one embodiment, to reduce the likelihood that the parity check data becomes corrupted, the computing system stores this data in hardened latches which are less susceptible to soft errors than other types of memory elements such as RAM.”)
With regards to claim 5, Hong does not explicitly teach:
“The method of claim 1, wherein the performing of the refresh operation on the memory circuit in response to the reset command includes: reading second device information stored in the memory cell array; generating a second parity of the second device information; and writing the second parity and the second device information in the memory circuit as the first device information and a first parity related to the first device information.”
Hong in view of Kim teaches:
“The method of claim 1, wherein the performing of the refresh operation on the memory circuit in response to the reset command “ (Kim Paragraph [0062-0064] "The refresh control circuit 385 may sequentially output the refresh row address REF_ADDR in response to a first refresh control signal IREF1 or a second refresh control signal IREF2 from the control logic circuit 210.") includes: reading second device information stored in the memory cell array;” (Kim, Paragraph [0053] "The control logic circuit 210 may control the ECC circuit 400 to perform the error detection and correction operation on the second memory cell row in the second interval of the scrubbing operation." Examiner interprets performing error correction and detection to indicate reading information. )
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with a scrubbing control circuit as taught by Kim because the scrubbing circuit generates scrubbing locations for memory refresh operations. (Kim, Paragraph [0008], “The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row selected from the plurality of memory cell rows based on refresh row addresses for refreshing the memory cell rows. ”)
Hong in view of Kim, does not explicitly teach”
“ generating a second parity of the second device information; and writing the second parity and the second device information in the memory circuit as the first device information and a first parity related to the first device information.”
Hong in view of Kim, further in view of Bowman teaches:
“ generating a second parity of the second device information;” (Bowman, Paragraph [0041] "Later, when performing the second partial write, the computing system generates a second parity value for the data in the second partial write and stores this value in a second parity entry 610 in the register 600.") “and writing the second parity and the second device information in the memory circuit as the first device information and a first parity related to the first device information.” (Bowman, Paragraph [0043] " Moreover, the computing system also generates separate parity check values for each of the partial writes. For example, the parity check bit 620 corresponds to the first parity value stored in entry 605, while the parity check bit 625 corresponds to the second parity value stored in entry 610. Thus, when reading out the data stored in register 600, the computing system can reference the parity check bits 620, 625 to ensure the parity values in entries 605, 610 were not corrupted. As described above, the parity check bits 620, 625 are stored in hardened latches 615, and thus, are less susceptible to soft errors than the data stored in the register 600.", Reference indicates that register 600 is the first parity register location. )
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with multiple parity bits as taught by Bowman in order to identify if an error has occurred in a created parity bit. (Bowman, Paragraph [0026], “ The parity check data 140 is used by the processor to determine whether there is an error in the parity data stored in the parity entry 130”)
With respect to claim 8, Hong in view of Kim teaches:
“The method of claim 1, further comprising: receiving a second command “ (Hong, Paragraph [0061] "Each of the memory devices 2110, 2120, and 2190 may output stored data, in response to a read command received from the memory controller 2300.") and an update device information from the controller;” ; (Hong, Paragraph [0071] " For example, the status information STAT may include information associated with at least one of various conditions, e.g., whether the memory devices 2110, 2120, and 2190 include the internal function circuits 2111, 2121, and 2191 (i.e., whether each of the memory devices 2110, 2120, and 2190 supports the first operation), ...") “and performing, in response to the second command, an operation of programming the updated device information in the memory cell array,” (Hong Paragraph [0076]"For example, when the status information STAT is changed from first information to second information, context of the second processed data pDAT may be changed from first context to second context which is different from the first context.").
Hong does not explicitly teach:
“generating an updated parity of the updated device information, and writing the updated device information and the updated parity in the memory circuit as the first device information and a first parity stored in the memory circuit.”
Bowman teaches:
“generating an updated parity” (Bowman, Paragraph [0041] "Later, when performing the second partial write, the computing system generates a second parity value for the data in the second partial write and stores this value in a second parity entry 610 in the register 600. When retrieving the first and second parity values to perform error correction, the parity values can be combined to yield a combined parity value for the data in both the first and second partial writes." Examiner interpret the combined parities to mean updated parity data.) of the updated device information,” (Bowman, Paragraph [0015] and FIG. 6 "The parity data helps the processor 105 detect, and possibly correct, soft errors in the data entry 125" Examiner interpret the possible correction in data entry 125 as an update, and additionally FIG.6 illustrates that data entry 125 is stored with the parity data.) “and writing the updated device information and the updated parity in the memory circuit as the first device information and a first parity stored in the memory circuit.”(Bowman, Paragraph [0043] " Moreover, the computing system also generates separate parity check values for each of the partial writes. For example, the parity check bit 620 corresponds to the first parity value stored in entry 605, while the parity check bit 625 corresponds to the second parity value stored in entry 610. Thus, when reading out the data stored in register 600, the computing system can reference the parity check bits 620, 625 to ensure the parity values in entries 605, 610 were not corrupted. As described above, the parity check bits 620, 625 are stored in hardened latches 615, and thus, are less susceptible to soft errors than the data stored in the register 600.", Reference indicates that register 600 is the first parity register location. )
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with multiple parity bits as taught by Bowman in order to identify if an error has occurred in a created parity bit. (Bowman, Paragraph [0026], “ The parity check data 140 is used by the processor to determine whether there is an error in the parity data stored in the parity entry 130”)
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 20190179699 A1), hereinafter “Hong”, in view of Kim et at. (US 20220208293 A1) hereinafter “Kim” further in view of Seno et at. (US 20220413748 A1) hereinafter “Seno”.
With regards to claim 4, Hong in view of Kim teaches:
“The method of claim 1, wherein the determining of whether the first device information has the error (Hong, Paragraph [0008] & [0009] " The memory device may perform a first error processing operation based on data stored in the memory device to generate first processed data.") “includes: performing a CRC-check operation” (Hong, FIG. 10, Paragraph [0124] " For example, the variable ECC circuit 3310 which operates in the CRC manner may detect a first bit location error, a second bit location error, an odd bit location error, a burst error, and/or the like.") on the first device information based on a first parity stored in the memory circuit;” (Hong, FIG. 8, Paragraph [0105] " In some example embodiments, the memory devices 3120 and 3190 may be provided to store data. Meanwhile, the memory device 3110 may be provided to store parity which is referenced to process an error of data stored in the memory devices 3120 and 3190. This configuration will be described with reference to FIG. 8. ").
Hong does not explicitly teach:
“writing a result of the CRC-check operation in a status register; receiving a status read command from the controller; and transmitting a value of the status register to the controller in response to the status read command.”
Seno teaches:
“writing a result of the CRC-check operation in a status register;” Seno, Paragraph [0043] "Then, the status register 260 of the embodiment will be described. As shown in Table 1, the status register 260 holds the CRC error information based on the CRC processing unit 230, which includes, for example, whether the CRC result is passed or failed, the number of CRC retries, a measured time of the timer 250 (used for subsequent judgment of whether the predetermined time Tn is reached) etc.") “receiving a status read command from the controller;” (Seno, Paragraph [0044] FIG. 9, " FIG. 9 is a flowchart illustrating a method of reading data from the status register 260. After the user inputs a reading command of the status register 260 to the flash memory 100 (S300), the controller 150 accesses the status register 260 according to an interpretation result of the reading command (S310), and outputs the CRC error information or the ECC information held in the status register 260 through the input/output circuit 120 (S320).") “and transmitting a value of the status register to the controller in response to the status read command.” (Seno, Paragraph [0044] FIG. 9, " FIG. 9 is a flowchart illustrating a method of reading data from the status register 260. After the user inputs a reading command of the status register 260 to the flash memory 100 (S300), the controller 150 accesses the status register 260 according to an interpretation result of the reading command (S310), and outputs the CRC error information or the ECC information held in the status register 260 through the input/output circuit 120 (S320)."
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with status registers as taught by Seno because the status registers hold information pertaining to the CRC error, including results indicating a pass or fail. (Seno, Paragraph [0043], “ As shown in Table 1, the status register 260 holds the CRC error information based on the CRC processing unit 230, which includes, for example, whether the CRC result is passed or failed, the number of CRC retries,… .”)
Claim(s) 6,13,14,19 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 20190179699 A1), hereinafter “Hong”, in view of Kim et at. (US 20220208293 A1) hereinafter “Kim”, further in view of Jeong et at. (US 20240168846 A1) hereinafter “Jeong”.
With regards to claim 6, Hong in view of Kim does not explicitly teach:
“The method of claim 1, further comprising: receiving the first command from the controller which detects an input/output exception occurring during an operation of the memory device.”
Jeong teaches:
“The method of claim 1, further comprising: receiving the first command from the controller which detects an input/output exception occurring during an operation of the memory device.” (Jeong, Paragraph [0059] "… when an input/output (I/O) failure due to at least one error occurring in the memory device 1200 occurs while operating in a normal mode of the operating system 1201, the memory system 1000 may indicate a “hang up” state in which a suspended state and/or non-responsive state of the operating system 1201 and/or memory system 1000 ... when the memory controller 1100 does not receive an expected response from the memory device 1200 after and/or in response to a transmitted memory command, the memory controller 1100 may determine that the memory device 1200 is in the hang up state and/or has committed an error, etc. ")
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with the memory system as taught by Jeong in order to identify if a memory device is no longer responding or in idle. By doing so, the memory system is able to identify an operation frequency and error. (Jeong, Paragraph [0060], “ The memory controller 1100 may verify and/or determine the current operation frequency of the memory device 1200 through the memory reference code function, but is not limited thereto. The memory controller 1100 may store the verified and/or determined current operation frequency as an error frequency of the memory device 1200 in the crash dump register 1120, but is not limited thereto.”)
With regards to claim 13, Hong in view of Kim does not explicitly teach:
“The method of claim 10, further comprising: detecting whether an input/output exception occurs in an operation of the memory device, wherein the transmitting of the first command to the memory device is performed in response to detecting that the input/output exception occurs in the memory device.”
Jeong teaches:
“The method of claim 10, further comprising: detecting whether an input/output exception occurs in an operation of the memory device, .” (Jeong, Paragraph [0059] "… when an input/output (I/O) failure due to at least one error occurring in the memory device 1200 occurs while operating in a normal mode of the operating system 1201, the memory system 1000 may indicate a “hang up” state in which a suspended state and/or non-responsive state of the operating system 1201 and/or memory system 1000 ... when the memory controller 1100 does not receive an expected response from the memory device 1200 after and/or in response to a transmitted memory command, the memory controller 1100 may determine that the memory device 1200 is in the hang up state and/or has committed an error, etc. ") “wherein the transmitting of the first command to the memory device is performed in response to detecting that the input/output exception occurs in the memory device.” ( Jeong, Paragraph [0059] When the hang up state lasts longer than a second specified time period (e.g., a second threshold period of time), the memory controller 1100 may perform a rebooting operation, but is not limited thereto. When rebooting of the memory system 1000 is repeated more than a specified and/or desired number of times (e.g., a threshold number of times), the operating system 1201 may enter a safe mode wherein a set and/or reduced number of device drivers (e.g., a minimum number of drivers, etc.) are loaded and/or executed by the operating system 1201).
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with the memory system as taught by Jeong in order to identify if a memory device is no longer responding or in idle. By doing so, the memory system is able to identify an operation frequency and error. (Jeong, Paragraph [0060], “ The memory controller 1100 may verify and/or determine the current operation frequency of the memory device 1200 through the memory reference code function, but is not limited thereto. The memory controller 1100 may store the verified and/or determined current operation frequency as an error frequency of the memory device 1200 in the crash dump register 1120, but is not limited thereto.”)
With regards to claim 14, Hong does not explicitly teach:
“The method of claim 13, further comprising: performing, in response to the detecting of the input/output exception and determining that the error is absent from the device information, a recovery operation on the memory device.
Jeong teaches:
“The method of claim 13, further comprising: performing, in response to the detecting of the input/output exception” (Jeong, Paragraph [0059] "… when an input/output (I/O) failure due to at least one error occurring in the memory device 1200 occurs while operating in a normal mode of the operating system 1201, the memory system 1000 may indicate a “hang up” state in which a suspended state and/or non-responsive state of the operating system 1201 and/or memory system 1000 ... when the memory controller 1100 does not receive an expected response from the memory device 1200 after and/or in response to a transmitted memory command, the memory controller 1100 may determine that the memory device 1200 is in the hang up state and/or has committed an error, etc. ") “and determining that the error is absent from the device information, a recovery operation on the memory device.” (Jeong, Paragraph [0063] "The memory controller 1100 may determine whether the memory device 1200 operates normally (e.g., operates without errors, operates without entering a hang up state, etc.) with respect to each of a plurality of operation frequencies through the BIOS 1310. When the memory device 1200 operates normally at all of the plurality of operation frequencies, the memory controller 1100 may perform a booting operation of the operating system 1201 in a normal mode, etc.")
With regards to claim 19, Hong in view of Kim does not explicitly teach:
“The method of claim 17, further comprising: detecting, by the controller, an input/output exception of the memory device, wherein the transmitting, by the controller, the first command to the memory device is performed in response to the input/output exception of the memory device being detected.”
Jeong teaches:
“The method of claim 17, further comprising: detecting, by the controller, an input/output exception of the memory device,” (Jeong, Paragraph [0059] "… when an input/output (I/O) failure due to at least one error occurring in the memory device 1200 occurs while operating in a normal mode of the operating system 1201, the memory system 1000 may indicate a “hang up” state in which a suspended state and/or non-responsive state of the operating system 1201 and/or memory system 1000 ... when the memory controller 1100 does not receive an expected response from the memory device 1200 after and/or in response to a transmitted memory command, the memory controller 1100 may determine that the memory device 1200 is in the hang up state and/or has committed an error, etc. ") “wherein the transmitting, by the controller, the first command to the memory device is performed in response to the input/output exception of the memory device being detected.” (Jeong, Paragraph [0059] “For example, when there is no response from the memory device 1200 for a first specified time period (e.g., a first threshold period of time) at a selected specific and/or desired operation frequency, the memory controller 1100 may determine that the memory system 1000 is in the hang up state (e.g., a non-responsive state, etc.), or in other words, when the memory controller 1100 does not receive an expected response from the memory device 1200 after and/or in response to a transmitted memory command, the memory controller 1100 may determine that the memory device 1200 is in the hang up state and/or has committed an error, etc.”)
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with the memory system as taught by Jeong in order to identify if a memory device is no longer responding or in idle. By doing so, the memory system is able to identify an operation frequency and error. (Jeong, Paragraph [0060], “ The memory controller 1100 may verify and/or determine the current operation frequency of the memory device 1200 through the memory reference code function, but is not limited thereto. The memory controller 1100 may store the verified and/or determined current operation frequency as an error frequency of the memory device 1200 in the crash dump register 1120, but is not limited thereto.”)
Claim(s) 7, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 20190179699 A1), hereinafter “Hong”, in view of Kim et at. (US 20220208293 A1) hereinafter “Kim”, further in view of Veches et at. (US 20230395116 A1) hereinafter “Veches”.
With regards to claim 7, Hong does not explicitly teach:
“The method of claim 1, wherein the first command is received from the controller which detects that the memory device is in an idle time period.”
Veches teaches:
“The method of claim 1, wherein the first command is received from the controller which detects that the memory device is in an idle time period.” (Veches Paragraph [0012] "For example, a host device may determine that data in a memory bank is no longer in use and send a reset command indicating the memory device to update the refresh region to an unused state containing no memory row addresses" Examiner interprets the memory bank no longer in use as an idle memory device.)
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with components of the host as taught by Veches in order to identify if a memory device is in idle state or is not being used allowing the host to free up the memory regions. (Veches, Paragraph [0057], For example, a host device may determine that data in a memory bank is no longer in use and send a reset command indicating the memory device to update the refresh region to an unused state containing no memory row addresses.)
With regards to claim 15, Hong in view of Kim does not explicitly teach:
“The method of claim 10, further comprising: detecting whether the memory device is in an idle time period, wherein the transmitting of the first command is performed in response to detecting that the memory device is in the idle time period.”
Veches teaches:
“The method of claim 10, further comprising: detecting whether the memory device is in an idle time period,” (Veches, Paragraph [0057], For example, a host device may determine that data in a memory bank is no longer in use and send a reset command indicating the memory device to update the refresh region to an unused state containing no memory row addresses) “wherein the transmitting of the first command is performed in response to detecting that the memory device is in the idle time period.” (Veches Paragraph [0012] "For example, a host device may determine that data in a memory bank is no longer in use and send a reset command indicating the memory device to update the refresh region to an unused state containing no memory row addresses" Examiner interprets the memory bank no longer in use as an idle memory device.)
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with components of the host as taught by Veches in order to identify if a memory device is in idle state or is not being used allowing the host to free up the memory regions. (Veches, Paragraph [0057], For example, a host device may determine that data in a memory bank is no longer in use and send a reset command indicating the memory device to update the refresh region to an unused state containing no memory row addresses.)
With regards to claim 20, Hong in view of Kim does not explicitly teach:
“The method of claim 17, further comprising: detecting, by the controller, whether the memory device is in an idle time period,” (Veches, Paragraph [0057], For example, a host device may determine that data in a memory bank is no longer in use and send a reset command indicating the memory device to update the refresh region to an unused state containing no memory row addresses) “wherein the transmitting, by the controller, the first command to the memory device is performed in response to detecting that the memory device is in the idle time period of the memory device.” (Veches Paragraph [0012] "For example, a host device may determine that data in a memory bank is no longer in use and send a reset command indicating the memory device to update the refresh region to an unused state containing no memory row addresses" Examiner interprets the memory bank no longer in use as an idle memory device.)
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with components of the host as taught by Veches in order to identify if a memory device is in idle state or is not being used allowing the host to free up the memory regions. (Veches, Paragraph [0057], For example, a host device may determine that data in a memory bank is no longer in use and send a reset command indicating the memory device to update the refresh region to an unused state containing no memory row addresses.)
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 20190179699 A1), hereinafter “Hong”, in view of Kim et at. (US 20220208293 A1) hereinafter “Kim”, in view of Bowman et at. (US 20170060673 A1) hereinafter “Bowman”, further in view of Jeong et al. (US 20240168846 A1, herein after “Jeong”).
With regards to Claim 9, Hong in view of Kim does not explicitly teach:
“The method of claim 1, further comprising: performing an initialization operation on the memory device, wherein the performing of the initialization operation includes: generating a second parity based on second device information stored in the memory cell array; and writing the second device information and the second parity in the memory circuit as the first device information and a first parity related to the first device information.”
Hong in view Kim, further in view of Jeong teaches:
“The method of claim 1, further comprising: performing an initialization operation on the memory device, “ (Jeong, Paragraph [0056], "When the memory system 1000 boots, the BIOS 1310 initializes the memory controller 1100 and loads an operating system 1201 into the memory device 1200 to boot the memory system 1000, etc.)
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with the memory system as taught by Jeong in order to identify if a memory device is no longer responding or in idle. By doing so, the memory system is able to identify an operation frequency and error. (Jeong, Paragraph [0060], “ The memory controller 1100 may verify and/or determine the current operation frequency of the memory device 1200 through the memory reference code function, but is not limited thereto. The memory controller 1100 may store the verified and/or determined current operation frequency as an error frequency of the memory device 1200 in the crash dump register 1120, but is not limited thereto.”)
Hong in view Kim further in view of Jeong does not explicitly teach:
“wherein the performing of the initialization operation includes: generating a second parity based on second device information stored in the memory cell array; and writing the second device information and the second parity in the memory circuit as the first device information and a first parity related to the first device information.”
Hong in view of Jeong further in view of Bowman teaches:
“wherein the performing of the initialization operation includes: generating a second parity based on second device information stored in the memory cell array” (Bowman, Paragraph [0003] & Paragraph [0041] "According to one embodiment of the present invention, an integrated circuit includes a memory including a plurality of registers, each register includes a data entry and a parity entry." and "Later, when performing the second partial write, the computing system generates a second parity value for the data in the second partial write and stores this value in a second parity entry 610 in the register 600.") “and writing the second device information and the second parity in the memory circuit as the first device information and a first parity related to the first device information.” (Bowman, Paragraph [0043] " Moreover, the computing system also generates separate parity check values for each of the partial writes. For example, the parity check bit 620 corresponds to the first parity value stored in entry 605, while the parity check bit 625 corresponds to the second parity value stored in entry 610. Thus, when reading out the data stored in register 600, the computing system can reference the parity check bits 620, 625 to ensure the parity values in entries 605, 610 were not corrupted. As described above, the parity check bits 620, 625 are stored in hardened latches 615, and thus, are less susceptible to soft errors than the data stored in the register 600.", Reference indicates that register 600 is the first parity register location. )
Therefore, it would have been obvious before the effective filling date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the memory controller with multiple parity bits as taught by Bowman in order to identify if an error has occurred in a created parity bit. (Bowman, Paragraph [0026], “ The parity check data 140 is used by the processor to determine whether there is an error in the parity data stored in the parity entry 130”)
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
Park et al. (US 201990324854 A1) teaches the use of an ECC (Error correction code) circuit to retain data read from a memory in a latch circuit. Additionally, the latch circuit will house the parity data that is created from the read data. This operation occurs upon a received command.
Agarwal et al. (US 20240061741 A1) teaches a memory subsystem that includes memory devices with dynamically allocated space for improved reliably, availability and severability. The memory subsystem works with ECC in order to detect error bits on the device. Additionally, the memory device can receive command to refresh of the memory systems.
Tsien et al. (US 20230195644 A1) teaches detecting an idle condition in monitored traffic that causes a memory controller to command the volatile memory to enter a self-refresh mode.
Communication
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/S.D.R./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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