DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
The specification as filed fails to provide support for wherein a Ba content of the outer layer is higher than a Ba content of the inner layer (as recited in claim 14) and wherein a dimension of the inner layer in the width direction is larger than a dimension of the outer layer in the width direction (as recited in claim 18). The specification as filed contradicts said claim limitations.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 14 & 18 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The limitation wherein a Ba content of the outer layer is higher than a Ba content of the inner layer (as recited in claim 14) and wherein a dimension of the inner layer in the width direction is larger than a dimension of the outer layer in the width direction (as recited in claim 18) are not found in the parent application (PCT/JP2023/031211) and are thus considered new matter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 6-7, 9-12, & 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yokoto (US 2021/0134530).
In regards to claim 1, Yokota ‘530 discloses
A multilayer ceramic capacitor comprising:
a multilayer body (110 – fig. 1-3; [0042]) including an internal layer portion (110a – fig. 2-3; [0043]) in which a plurality of dielectric layers (130 – fig. 2-3; [0043]) and a plurality of internal electrode layers (140 – fig. 2-3; [0043]) are stacked in an alternating pattern, one pair of main surfaces (fig. 2-3) opposed to each other in a lamination direction, one pair of end surfaces (115 & 116 – fig. 3-4; [0040]) opposed to each other in a lengthwise direction orthogonal to the lamination direction, and one pair of side surfaces (113a & 114a – fig. 2-3; [0043]) opposed to each other in a width direction orthogonal to both the lamination direction and the lengthwise direction; and
one pair of external electrodes (121 & 1223 – fig. 1; [0039]) located on the respective end surfaces and connected to the internal electrode layers; wherein
the multilayer body includes one pair of side margin portions (110b & 110c – fig. 2; [0042]) on both sides of the internal layer portion in the width direction, and one pair of external layer portions (uppermost and lowermost dielectric 130 of 110a – fig. 2-3) on both sides of the internal layer portion in the lamination direction so as to be positioned between the side margin portions;
the one pair of side surfaces includes a first side surface and a second side surface (fig. 1-3);
the one pair of side margin portions includes a first side margin portion (110b) on the first side surface and a second side margin portion (110c) on the second side surface (fig. 2);
the multilayer ceramic capacitor further comprises:
a first cover region (110d – fig. 2-3; [0049] or 150d – fig. 2-3; [0057]) including an inorganic material ([0049]) and positioned on outer surfaces of the multilayer body so as to span boundaries between the first side margin portion and the respective external layer portions; and
a second cover region (110e– fig. 2-3; [0049] or 151d – fig. 2-3; [0057] or 150e – fig. 2-3; [0058]) including the inorganic material ([0049]) and positioned on outer surfaces of the multilayer body so as to span boundaries between the second side margin portion and the respective external layer portions; and
the end surfaces each include an uncovered section not covered with either the first cover region or the second cover region, and connected to the external electrodes at the uncovered sections (fig. 3-4).
In regards to claim 2, Yokota ‘530 discloses
The multilayer ceramic capacitor according to claim 1, wherein the inorganic material includes at least one of Si, Ti, Ba, or Zr ([0049]).
In regards to claim 4, Yokota ‘530 discloses
The multilayer ceramic capacitor according to claim 1, wherein a thickness of the first cover region (150d) is about 1 µm or greater and not greater than about 10 µm ([0124-0125]); and
a thickness of the second cover region (150e) is about 1 µm or greater and not greater than about 10 µm ([0124-0125]).
In regards to claim 6, Yokota ‘530 discloses
The multilayer ceramic capacitor according to claim 1, wherein a dimension of the first side margin portion in the width direction is about 5 µm or greater and not greater than about 40 µm ([0104-0106]); and
a dimension of the second side margin portion in the width direction is about 5 µm or greater and not greater than about 40 µm ([0104-0106]).
In regards to claim 7, Yokota ‘530 discloses
The multilayer ceramic capacitor according to claim 1, wherein each of the side margin portions includes a plurality of layers, an inner layer (150b & 150c – fig. 2; [0104]) that is closest to the internal layer portion among the plurality of layers and an outer layer (151b & 151c – fig. 2; [0104]) that is farthest from the internal layer portion among the plurality of layers.
In regards to claim 9, Yokota ‘530 discloses
The multilayer ceramic capacitor according to claim 7, wherein a dimension of the outer layer in the width direction is larger than a dimension of the inner layer in the width direction ([0110]).
In regards to claim 10, Yokota ‘530 discloses
The multilayer ceramic capacitor according to claim 9, wherein the dimension of the inner layer in the width direction is about 0.1 µm or greater and not greater than about 20 µm ([0105]); and
the dimension of the outer layer in the width direction is about 5 µm or greater and not greater than about 20 µm ([0106]).
In regards to claim 11, Yokota ‘530 discloses
The multilayer ceramic capacitor according to claim 1, wherein a thickness of each of the internal electrode layers is about 0.8 µm or less ([0070]).
In regards to claim 12, Yokota ‘530 discloses
The multilayer ceramic capacitor according to claim 7, wherein a thickness of each of the dielectric layers is about 0.55 µm or less ([0067]).
In regards to claim 16, Yokota ‘530 discloses
The multilayer ceramic capacitor according to claim 7, wherein the plurality of layers include differing amounts of resin ([0108]).
In regards to claim 17, Yokota ‘530 discloses
The multilayer ceramic capacitor according to claim 7, wherein the inner layer has a different amount of additive than the outer layer ([0108] – different amount of resin wherein resin is considered additive).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over 19-20 Yokota ‘530 in view of Kuroda et al. (US 5,812,363).
In regards to claim 19,
Yokota ‘530 fails to disclose wherein the plurality of internal electrodes includes floating internal electrode layers.
Kuroda ‘363 discloses an internal electrode structure includes floating internal electrode layers (fig. 4).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form internal electrodes of Yokota ‘530 to have a structure including floating electrodes as taught by Kuroda ‘363 as such a structure is taught to be an alternative internal electrode design to the dual structure design of Yokota ‘530 and the floating structure allows for the “capacitance subdivision” effect which enhances high voltage withstand characteristics.
In regards to claim 20,
Yokota ‘530 as modified by Kuroda ‘363 further discloses wherein the multilayer body includes a plurality of capacitor components between opposed ones of the plurality of internal electrodes and connected in series (fig. 4; C6:L1-16 of Kuroda ‘363).
Claim(s) 1-3, 5-13, 15, & 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 2017/0018363) in view of JP2018117139A hereafter referred to as Yagi.
In regards to claim 1,
Tanaka ‘363 discloses a multilayer ceramic capacitor comprising:
a multilayer body including an internal layer portion (26 – fig. 2; [0032]) in which a plurality of dielectric layers (20 – fig. 2-4; [0032]) and a plurality of internal electrode layers (22 & 24 – fig. 2-4; [0032]) are stacked in an alternating pattern, one pair of main surfaces opposed to each other in a lamination direction, one pair of end surfaces (13 & 14 – fig. 2; [0031]) opposed to each other in a lengthwise direction orthogonal to the lamination direction, and one pair of side surfaces opposed to each other in a width direction orthogonal to both the lamination direction and the lengthwise direction (seen in fig. 2-4); and
one pair of external electrodes (40 & 42 – fig. 1-2; [0029]) located on the respective end surfaces and connected to the internal electrode layers; wherein
the multilayer body includes one pair of side margin portions (32 & 34 – fig. 3; [0032]) on both sides of the internal layer portion in the width direction, and one pair of external layer portions (28 & 30 – fig. 2-3; [0032]) on both sides of the internal layer portion in the lamination direction so as to be positioned between the side margin portions;
the one pair of side surfaces includes a first side surface and a second side surface;
the one pair of side margin portions includes a first side margin portion (32) on the first side surface and a second side margin portion (34) on the second side surface. Tanaka ‘363 fails to disclose the multilayer ceramic capacitor further comprises: a first cover region including an inorganic material and positioned on outer surfaces of the multilayer body so as to span boundaries between the first side margin portion and the respective external layer portions; and a second cover region including the inorganic material and positioned on outer surfaces of the multilayer body so as to span boundaries between the second side margin portion and the respective external layer portions; and the end surfaces each include an uncovered section not covered with either the first cover region or the second cover region, and connected to the external electrodes at the uncovered sections.
Yagi discloses the multilayer ceramic capacitor further comprises: a first cover region (13a – fig. 1; [0035]) including an inorganic material and positioned on outer surfaces of the multilayer body so as to span boundaries between the first side margin portion and the respective external layer portions; and a second cover region (13b – fig. 1; [0035]) including the inorganic material and positioned on outer surfaces of the multilayer body so as to span boundaries between the second side margin portion and the respective external layer portions; and the end surfaces each include an uncovered section not covered with either the first cover region or the second cover region, and connected to the external electrodes at the uncovered sections (fig. 6).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form cover layers as taught by Yagi with the capacitor Tanaka ‘363 to obtain a capacitor wherein there is a high degree of freedom in setting the ESR.
In regards to claim 2,
Tanaka ‘363 as modified by Yagi further disclose wherein the inorganic material includes at least one of Si, Ti, Ba, or Zr ([0035] of Yagi).
In regards to claim 3,
Tanaka ‘363 as modified by Yagi further disclose wherein the first cover region has a loop shape surrounding an area in at least the lengthwise direction (fig. 6 of Yagi); and
the second cover region has a loop shape surrounding an area in at least the lengthwise direction (fig. 6 of Yagi).
In regards to claim 5,
Tanaka ‘363 as modified by Yagi further disclose wherein the multilayer ceramic capacitor has a substantially cuboid shape (fig. 1-4 of Tanaka ‘363).
Tanaka ‘363 as modified by Yagi fails to explicitly disclose a dimension of the first cover region in the width direction is about 10% or greater of a dimension of the multilayer body in the width direction and not greater than about 20% of the dimension of the multilayer body in the width direction; and a dimension of the second cover region in the width direction is about 10% or greater of the dimension of the multilayer body in the width direction and not greater than about 20% of the dimension of the multilayer body in the width direction. However, Yagi discloses the amount of coverable of the cover layers is a result effective variable, particularly for controlling ESR (fig. 9; [0062]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Tanaka ‘363 as modified by Yagi such that a dimension of the first cover region in the width direction is about 10% or greater of a dimension of the multilayer body in the width direction and not greater than about 20% of the dimension of the multilayer body in the width direction; and a dimension of the second cover region in the width direction is about 10% or greater of the dimension of the multilayer body in the width direction and not greater than about 20% of the dimension of the multilayer body in the width direction to obtain a desired ESR, as taught Yagi. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regards to claim 6,
Tanaka ‘363 as modified by Yagi further disclose wherein a dimension of the first side margin portion in the width direction is about 5 µm or greater and not greater than about 40 µm ([0097] of Tanaka ‘363); and
a dimension of the second side margin portion in the width direction is about 5 µm or greater and not greater than about 40 µm ([0097] of Tanaka ‘363).
In regards to claim 7,
Tanaka ‘363 as modified by Yagi further disclose wherein each of the side margin portions includes a plurality of layers, an inner layer (32b & 34b – fig. 3; [0043] of Tanaka ‘363) that is closest to the internal layer portion among the plurality of layers and an outer layer (32a & 34a – fig. 3; [0043] of Tanaka ‘363) that is farthest from the internal layer portion among the plurality of layers.
In regards to claim 8,
Tanaka ‘363 as modified by Yagi further disclose wherein each of the inner layer and the outer layer includes a ceramic, dielectric ceramic particles, and an additive between the dielectric ceramic particles ([0046] of Tanaka ‘363); and
the additive in the inner layer and in the outer layer are different from each other ([0052] of Tanaka ‘363).
In regards to claim 9,
Tanaka ‘363 as modified by Yagi further disclose wherein a dimension of the outer layer in the width direction is larger than a dimension of the inner layer in the width direction ([0097] of Tanaka ‘363).
In regards to claim 10,
Tanaka ‘363 as modified by Yagi further disclose wherein the dimension of the inner layer in the width direction is about 0.1 µm or greater and not greater than about 20 µm ([0097] of Tanaka ‘363); and
the dimension of the outer layer in the width direction is about 5 µm or greater and not greater than about 20 µm ([0097] of Tanaka ‘363).
In regards to claim 11,
Tanaka ‘363 as modified by Yagi further disclose wherein a thickness of each of the internal electrode layers is about 0.8 µm or less ([0038] of Tanaka ‘363).
In regards to claim 12,
Tanaka ‘363 as modified by Yagi further disclose wherein a thickness of each of the dielectric layers is about 0.55 µm or less ([0033] of Tanaka ‘363).
In regards to claim 13,
Tanaka ‘363 as modified by Yagi further disclose wherein an Si content of the outer layer is higher than an Si content of the inner layer ([0046] of Tanaka ‘363).
In regards to claim 15,
Tanaka ‘363 as modified by Yagi further disclose wherein the outer layer has fewer voids than the inner layer ([0053] of Tanaka ‘363).
In regards to claim 17,
Tanaka ‘363 as modified by Yagi further disclose wherein the inner layer has a different amount of additive than the outer layer ([0046] of Tanaka ‘363).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2007/0297119 – fig. 5 & 8 US 2015/0340155 – fig. 3
US 2017/0243697 – fig. 3 US 2020/0312569 – fig. 4
US 9,424,990 – fig. 6 JP2016201567A – fig. 1
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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/David M Sinclair/Primary Examiner, Art Unit 2848