DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 & 6-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka et al. (US 2017/0018363).
In regards to claim 1, Tanaka ‘363 discloses
A multilayer ceramic capacitor comprising:
a multilayer body (12 – fig. 1-3; [0029]) including a first main surface (17 – fig. 1-3; [0031]) and a second main surface (18 – fig. 1-3; [0031]) opposed to each other in a lamination direction, a first end surface (13 – fig. 1-3; [0031]) and a second end surface (14 – fig. 1-3; [0031]) opposed to each other in a lengthwise direction orthogonal to the lamination direction, and a first side surface (fig. 1-3; [0031]) and a second side surface (fig. 1-3; [0031]) opposed to each other in a width direction orthogonal to both the lamination direction and the lengthwise direction;
a first side margin portion (32– fig. 3; [0032]) on the first side surface;
a second side margin portion (34 – fig. 3; [0032]) on the second side surface;
a first external electrode (40b & 40c – fig. 2; [0055]) located on the respective first end surface; and
a second external electrode (42b & 42c – fig. 2; [0056]) located on the second end surface; wherein
the multilayer ceramic capacitor further comprises:
a first cover region (40a – fig. 1-2; [0055]) including an inorganic material ([0057]) and positioned on a boundary between the first side margin portion and the multilayer body (fig. 1-2; [0055]); and
a second cover region (42a – fig. 1-2; [0056]) including the inorganic material ([0057]) and positioned on a boundary between the second side margin portion and the multilayer body (fig. 1-2; [0056]); and
a portion of each of the first side surface, the first main surface, and the second main surface is exposed from the first cover region (seen in fig. 1-2).
In regards to claim 6, Tanaka ‘363 discloses
The multilayer ceramic capacitor according to claim 1, wherein a dimension of the first side margin portion in the width direction is about 5 µm or greater and not greater than about 40 µm ([0097]).
In regards to claim 7, Tanaka ‘363 discloses
The multilayer ceramic capacitor according to claim 1, wherein each of the side margin portions includes a plurality of layers, an inner layer (32b & 34b – fig. 3; [0043]) that is closest to the multilayer body among the plurality of layers and an outer layer (32a & 34a – fig. 3; [0043]) that is farthest from the multilayer body among the plurality of layers.
In regards to claim 8, Tanaka ‘363 discloses
The multilayer ceramic capacitor according to claim 7, wherein the multilayer body includes a ceramic, dielectric ceramic particles, and an additive between the dielectric ceramic particles ([0046]);
the additive is included in the inner layer and the outer layer ([0052]); and
the additive in the inner layer and in the outer layer are different from each other ([0052]).
In regards to claim 9, Tanaka ‘363 discloses
The multilayer ceramic capacitor according to claim 7, wherein a dimension of the outer layer in the width direction is larger than a dimension of the inner layer in the width direction ([0097]).
In regards to claim 10, Tanaka ‘363 discloses
The multilayer ceramic capacitor according to claim 9, wherein the dimension of the inner layer in the width direction is about 0.1 µm or greater and not greater than about 20 µm ([0097]); and
the dimension of the outer layer in the width direction is about 5 µm or greater and not greater than about 20 µm ([0097]).
In regards to claim 11, Tanaka ‘363 discloses
The multilayer ceramic capacitor according to claim 1, wherein the multilayer body includes an internal electrode layer; and a thickness of the internal electrode layer is about 0.8 µm or less ([0038]).
In regards to claim 12, Tanaka ‘363 discloses
The multilayer ceramic capacitor according to claim 7, wherein the multilayer body includes a dielectric layer; and a thickness of dielectric layer is about 0.55 µm or less ([0033]).
In regards to claim 13, Tanaka ‘363 discloses
The multilayer ceramic capacitor according to claim 7, wherein an Si content of the outer layer is higher than an Si content of the inner layer ([0046]).
In regards to claim 14, Tanaka ‘363 discloses
The multilayer ceramic capacitor according to claim 7, wherein a Ba content of the inner layer is higher than a Ba content of the outer layer ([0052]).
In regards to claim 15, Tanaka ‘363 discloses
The multilayer ceramic capacitor according to claim 7, wherein the outer layer has fewer voids than the inner layer ([0053]).
Tanaka ‘363 as modified by Yagi further disclose wherein the outer layer has fewer voids than the inner layer ([0053] of Tanaka ‘363).
In regards to claim 16, Tanaka ‘363 discloses
The multilayer ceramic capacitor according to claim 7, wherein the plurality of layers include differing amounts of resin ([0094]).
In regards to claim 17, Tanaka ‘363 discloses
The multilayer ceramic capacitor according to claim 7, wherein the inner layer has a different amount of additive than the outer layer ([0046]).
In regards to claim 18, Tanaka ‘363 discloses
The multilayer ceramic capacitor according to claim 7, wherein a dimension of the outer layer in the width direction is larger than a dimension of the inner layer in the width direction ([0044]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 & 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over 19-20 Tanaka ‘363 in view of Sakatsume et al. (US 2017/0345570).
In regards to claim 2,
Tanaka ‘363 fails to disclose wherein the inorganic material includes at least one of Si, Ti, Ba, or Zr.
Sakastume ‘570 discloses a cover region (21 – fig. 1; [0029]) wherein the inorganic material includes at least one of Si, Ti, Ba, or Zr ([0019]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the cover region of Tanaka ‘363 using a composition as taught by Sakastume ‘570 to obtain capacitor wherein the cover region has good adhesion to the body while preventing discontinuities in the plating layer.
In regards to claim 4,
Tanaka ‘363 fails to disclose wherein a thickness of the first cover region is about 1 µm or greater and not greater than about 10 µm.
Sakastume ‘570 discloses wherein a thickness of the first cover region (21 – fig. 1; [0029]) is about 1 µm or greater and not greater than about 10 µm ([0018]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the cover region of Tanaka ‘363 using a thickness as taught by Sakastume ‘570 to obtain capacitor with a small size and good volume efficiency.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over 19-20 Tanaka ‘363 in view of Kuroda et al. (US 5,812,363).
In regards to claim 19,
Tanaka ‘363 fails to disclose wherein the multilayer body includes floating internal electrode layers.
Kuroda ‘363 discloses an internal electrode structure includes floating internal electrode layers (fig. 4).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form internal electrodes of Tanaka ‘363 to have a structure including floating electrodes as taught by Kuroda ‘363 as such a structure is taught to be an alternative internal electrode design to the dual structure design of Tanaka ‘363 and the floating structure allows for the “capacitance subdivision” effect which enhances high voltage withstand characteristics.
Allowable Subject Matter
Claim(s) 3 & 5 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest (in combination with the other claim limitations) wherein the first cover region has a loop shape surrounding an area in at least the lengthwise direction (claim 3) & wherein the multilayer ceramic capacitor has a substantially cuboid shape; and a dimension of the first cover region in the width direction is about 10% or greater of a dimension of the multilayer body in the width direction and not greater than about 20% of the dimension of the multilayer body in the width direction (claim 5).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David M Sinclair/Primary Examiner, Art Unit 2847
Prosecution Insights